2 * linux/arch/arm/plat-omap/dma.c
4 * Copyright (C) 2003 - 2008 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Graphics DMA and LCD DMA graphics tranformations
8 * by Imre Deak <imre.deak@nokia.com>
9 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
10 * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
11 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
13 * Copyright (C) 2009 Texas Instruments
14 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
16 * Support functions for the OMAP internal DMA channels.
18 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
19 * Converted DMA library into DMA platform driver.
20 * - G, Manjunath Kondaiah <manjugk@ti.com>
22 * This program is free software; you can redistribute it and/or modify
23 * it under the terms of the GNU General Public License version 2 as
24 * published by the Free Software Foundation.
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/sched.h>
31 #include <linux/spinlock.h>
32 #include <linux/errno.h>
33 #include <linux/interrupt.h>
34 #include <linux/irq.h>
36 #include <linux/slab.h>
37 #include <linux/delay.h>
39 #include <asm/system.h>
40 #include <mach/hardware.h>
47 #ifndef CONFIG_ARCH_OMAP1
48 enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
49 DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
52 enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
55 #define OMAP_DMA_ACTIVE 0x01
56 #define OMAP2_DMA_CSR_CLEAR_MASK 0xffffffff
58 #define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
60 static struct omap_system_dma_plat_info *p;
61 static struct omap_dma_dev_attr *d;
63 static int enable_1510_mode;
66 static struct omap_dma_global_context_registers {
68 u32 dma_ocp_sysconfig;
70 } omap_dma_global_context;
72 struct dma_link_info {
74 int no_of_lchs_linked;
85 static struct dma_link_info *dma_linked_lch;
87 #ifndef CONFIG_ARCH_OMAP1
89 /* Chain handling macros */
90 #define OMAP_DMA_CHAIN_QINIT(chain_id) \
92 dma_linked_lch[chain_id].q_head = \
93 dma_linked_lch[chain_id].q_tail = \
94 dma_linked_lch[chain_id].q_count = 0; \
96 #define OMAP_DMA_CHAIN_QFULL(chain_id) \
97 (dma_linked_lch[chain_id].no_of_lchs_linked == \
98 dma_linked_lch[chain_id].q_count)
99 #define OMAP_DMA_CHAIN_QLAST(chain_id) \
101 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) == \
102 dma_linked_lch[chain_id].q_count) \
104 #define OMAP_DMA_CHAIN_QEMPTY(chain_id) \
105 (0 == dma_linked_lch[chain_id].q_count)
106 #define __OMAP_DMA_CHAIN_INCQ(end) \
107 ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
108 #define OMAP_DMA_CHAIN_INCQHEAD(chain_id) \
110 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
111 dma_linked_lch[chain_id].q_count--; \
114 #define OMAP_DMA_CHAIN_INCQTAIL(chain_id) \
116 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
117 dma_linked_lch[chain_id].q_count++; \
121 static int dma_lch_count;
122 static int dma_chan_count;
123 static int omap_dma_reserve_channels;
125 static spinlock_t dma_chan_lock;
126 static struct omap_dma_lch *dma_chan;
128 static inline void disable_lnk(int lch);
129 static void omap_disable_channel_irq(int lch);
130 static inline void omap_enable_channel_irq(int lch);
132 #define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \
135 #ifdef CONFIG_ARCH_OMAP15XX
136 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
137 static int omap_dma_in_1510_mode(void)
139 return enable_1510_mode;
142 #define omap_dma_in_1510_mode() 0
145 #ifdef CONFIG_ARCH_OMAP1
146 static inline int get_gdma_dev(int req)
148 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
149 int shift = ((req - 1) % 5) * 6;
151 return ((omap_readl(reg) >> shift) & 0x3f) + 1;
154 static inline void set_gdma_dev(int req, int dev)
156 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
157 int shift = ((req - 1) % 5) * 6;
161 l &= ~(0x3f << shift);
162 l |= (dev - 1) << shift;
166 #define set_gdma_dev(req, dev) do {} while (0)
169 void omap_set_dma_priority(int lch, int dst_port, int priority)
174 if (cpu_class_is_omap1()) {
176 case OMAP_DMA_PORT_OCP_T1: /* FFFECC00 */
177 reg = OMAP_TC_OCPT1_PRIOR;
179 case OMAP_DMA_PORT_OCP_T2: /* FFFECCD0 */
180 reg = OMAP_TC_OCPT2_PRIOR;
182 case OMAP_DMA_PORT_EMIFF: /* FFFECC08 */
183 reg = OMAP_TC_EMIFF_PRIOR;
185 case OMAP_DMA_PORT_EMIFS: /* FFFECC04 */
186 reg = OMAP_TC_EMIFS_PRIOR;
194 l |= (priority & 0xf) << 8;
198 if (cpu_class_is_omap2()) {
201 ccr = p->dma_read(CCR, lch);
206 p->dma_write(ccr, CCR, lch);
209 EXPORT_SYMBOL(omap_set_dma_priority);
211 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
212 int frame_count, int sync_mode,
213 int dma_trigger, int src_or_dst_synch)
217 l = p->dma_read(CSDP, lch);
220 p->dma_write(l, CSDP, lch);
222 if (cpu_class_is_omap1()) {
225 ccr = p->dma_read(CCR, lch);
227 if (sync_mode == OMAP_DMA_SYNC_FRAME)
229 p->dma_write(ccr, CCR, lch);
231 ccr = p->dma_read(CCR2, lch);
233 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
235 p->dma_write(ccr, CCR2, lch);
238 if (cpu_class_is_omap2() && dma_trigger) {
241 val = p->dma_read(CCR, lch);
243 /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
244 val &= ~((1 << 23) | (3 << 19) | 0x1f);
245 val |= (dma_trigger & ~0x1f) << 14;
246 val |= dma_trigger & 0x1f;
248 if (sync_mode & OMAP_DMA_SYNC_FRAME)
253 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
258 if (src_or_dst_synch == OMAP_DMA_DST_SYNC_PREFETCH) {
259 val &= ~(1 << 24); /* dest synch */
260 val |= (1 << 23); /* Prefetch */
261 } else if (src_or_dst_synch) {
262 val |= 1 << 24; /* source synch */
264 val &= ~(1 << 24); /* dest synch */
266 p->dma_write(val, CCR, lch);
269 p->dma_write(elem_count, CEN, lch);
270 p->dma_write(frame_count, CFN, lch);
272 EXPORT_SYMBOL(omap_set_dma_transfer_params);
274 void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
276 BUG_ON(omap_dma_in_1510_mode());
278 if (cpu_class_is_omap1()) {
281 w = p->dma_read(CCR2, lch);
285 case OMAP_DMA_CONSTANT_FILL:
288 case OMAP_DMA_TRANSPARENT_COPY:
291 case OMAP_DMA_COLOR_DIS:
296 p->dma_write(w, CCR2, lch);
298 w = p->dma_read(LCH_CTRL, lch);
300 /* Default is channel type 2D */
302 p->dma_write(color, COLOR, lch);
303 w |= 1; /* Channel type G */
305 p->dma_write(w, LCH_CTRL, lch);
308 if (cpu_class_is_omap2()) {
311 val = p->dma_read(CCR, lch);
312 val &= ~((1 << 17) | (1 << 16));
315 case OMAP_DMA_CONSTANT_FILL:
318 case OMAP_DMA_TRANSPARENT_COPY:
321 case OMAP_DMA_COLOR_DIS:
326 p->dma_write(val, CCR, lch);
329 p->dma_write(color, COLOR, lch);
332 EXPORT_SYMBOL(omap_set_dma_color_mode);
334 void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
336 if (cpu_class_is_omap2()) {
339 csdp = p->dma_read(CSDP, lch);
340 csdp &= ~(0x3 << 16);
341 csdp |= (mode << 16);
342 p->dma_write(csdp, CSDP, lch);
345 EXPORT_SYMBOL(omap_set_dma_write_mode);
347 void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
349 if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
352 l = p->dma_read(LCH_CTRL, lch);
355 p->dma_write(l, LCH_CTRL, lch);
358 EXPORT_SYMBOL(omap_set_dma_channel_mode);
360 /* Note that src_port is only for omap1 */
361 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
362 unsigned long src_start,
363 int src_ei, int src_fi)
367 if (cpu_class_is_omap1()) {
370 w = p->dma_read(CSDP, lch);
373 p->dma_write(w, CSDP, lch);
376 l = p->dma_read(CCR, lch);
378 l |= src_amode << 12;
379 p->dma_write(l, CCR, lch);
381 p->dma_write(src_start, CSSA, lch);
383 p->dma_write(src_ei, CSEI, lch);
384 p->dma_write(src_fi, CSFI, lch);
386 EXPORT_SYMBOL(omap_set_dma_src_params);
388 void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
390 omap_set_dma_transfer_params(lch, params->data_type,
391 params->elem_count, params->frame_count,
392 params->sync_mode, params->trigger,
393 params->src_or_dst_synch);
394 omap_set_dma_src_params(lch, params->src_port,
395 params->src_amode, params->src_start,
396 params->src_ei, params->src_fi);
398 omap_set_dma_dest_params(lch, params->dst_port,
399 params->dst_amode, params->dst_start,
400 params->dst_ei, params->dst_fi);
401 if (params->read_prio || params->write_prio)
402 omap_dma_set_prio_lch(lch, params->read_prio,
405 EXPORT_SYMBOL(omap_set_dma_params);
407 void omap_set_dma_src_index(int lch, int eidx, int fidx)
409 if (cpu_class_is_omap2())
412 p->dma_write(eidx, CSEI, lch);
413 p->dma_write(fidx, CSFI, lch);
415 EXPORT_SYMBOL(omap_set_dma_src_index);
417 void omap_set_dma_src_data_pack(int lch, int enable)
421 l = p->dma_read(CSDP, lch);
425 p->dma_write(l, CSDP, lch);
427 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
429 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
431 unsigned int burst = 0;
434 l = p->dma_read(CSDP, lch);
437 switch (burst_mode) {
438 case OMAP_DMA_DATA_BURST_DIS:
440 case OMAP_DMA_DATA_BURST_4:
441 if (cpu_class_is_omap2())
446 case OMAP_DMA_DATA_BURST_8:
447 if (cpu_class_is_omap2()) {
452 * not supported by current hardware on OMAP1
456 case OMAP_DMA_DATA_BURST_16:
457 if (cpu_class_is_omap2()) {
462 * OMAP1 don't support burst 16
470 p->dma_write(l, CSDP, lch);
472 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
474 /* Note that dest_port is only for OMAP1 */
475 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
476 unsigned long dest_start,
477 int dst_ei, int dst_fi)
481 if (cpu_class_is_omap1()) {
482 l = p->dma_read(CSDP, lch);
485 p->dma_write(l, CSDP, lch);
488 l = p->dma_read(CCR, lch);
490 l |= dest_amode << 14;
491 p->dma_write(l, CCR, lch);
493 p->dma_write(dest_start, CDSA, lch);
495 p->dma_write(dst_ei, CDEI, lch);
496 p->dma_write(dst_fi, CDFI, lch);
498 EXPORT_SYMBOL(omap_set_dma_dest_params);
500 void omap_set_dma_dest_index(int lch, int eidx, int fidx)
502 if (cpu_class_is_omap2())
505 p->dma_write(eidx, CDEI, lch);
506 p->dma_write(fidx, CDFI, lch);
508 EXPORT_SYMBOL(omap_set_dma_dest_index);
510 void omap_set_dma_dest_data_pack(int lch, int enable)
514 l = p->dma_read(CSDP, lch);
518 p->dma_write(l, CSDP, lch);
520 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
522 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
524 unsigned int burst = 0;
527 l = p->dma_read(CSDP, lch);
530 switch (burst_mode) {
531 case OMAP_DMA_DATA_BURST_DIS:
533 case OMAP_DMA_DATA_BURST_4:
534 if (cpu_class_is_omap2())
539 case OMAP_DMA_DATA_BURST_8:
540 if (cpu_class_is_omap2())
545 case OMAP_DMA_DATA_BURST_16:
546 if (cpu_class_is_omap2()) {
551 * OMAP1 don't support burst 16
555 printk(KERN_ERR "Invalid DMA burst mode\n");
560 p->dma_write(l, CSDP, lch);
562 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
564 static inline void omap_enable_channel_irq(int lch)
569 if (cpu_class_is_omap1())
570 status = p->dma_read(CSR, lch);
571 else if (cpu_class_is_omap2())
572 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
574 /* Enable some nice interrupts. */
575 p->dma_write(dma_chan[lch].enabled_irqs, CICR, lch);
578 static void omap_disable_channel_irq(int lch)
580 if (cpu_class_is_omap2())
581 p->dma_write(0, CICR, lch);
584 void omap_enable_dma_irq(int lch, u16 bits)
586 dma_chan[lch].enabled_irqs |= bits;
588 EXPORT_SYMBOL(omap_enable_dma_irq);
590 void omap_disable_dma_irq(int lch, u16 bits)
592 dma_chan[lch].enabled_irqs &= ~bits;
594 EXPORT_SYMBOL(omap_disable_dma_irq);
596 static inline void enable_lnk(int lch)
600 l = p->dma_read(CLNK_CTRL, lch);
602 if (cpu_class_is_omap1())
605 /* Set the ENABLE_LNK bits */
606 if (dma_chan[lch].next_lch != -1)
607 l = dma_chan[lch].next_lch | (1 << 15);
609 #ifndef CONFIG_ARCH_OMAP1
610 if (cpu_class_is_omap2())
611 if (dma_chan[lch].next_linked_ch != -1)
612 l = dma_chan[lch].next_linked_ch | (1 << 15);
615 p->dma_write(l, CLNK_CTRL, lch);
618 static inline void disable_lnk(int lch)
622 l = p->dma_read(CLNK_CTRL, lch);
624 /* Disable interrupts */
625 if (cpu_class_is_omap1()) {
626 p->dma_write(0, CICR, lch);
627 /* Set the STOP_LNK bit */
631 if (cpu_class_is_omap2()) {
632 omap_disable_channel_irq(lch);
633 /* Clear the ENABLE_LNK bit */
637 p->dma_write(l, CLNK_CTRL, lch);
638 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
641 static inline void omap2_enable_irq_lch(int lch)
646 if (!cpu_class_is_omap2())
649 spin_lock_irqsave(&dma_chan_lock, flags);
650 val = p->dma_read(IRQENABLE_L0, lch);
652 p->dma_write(val, IRQENABLE_L0, lch);
653 spin_unlock_irqrestore(&dma_chan_lock, flags);
656 static inline void omap2_disable_irq_lch(int lch)
661 if (!cpu_class_is_omap2())
664 spin_lock_irqsave(&dma_chan_lock, flags);
665 val = p->dma_read(IRQENABLE_L0, lch);
667 p->dma_write(val, IRQENABLE_L0, lch);
668 spin_unlock_irqrestore(&dma_chan_lock, flags);
671 int omap_request_dma(int dev_id, const char *dev_name,
672 void (*callback)(int lch, u16 ch_status, void *data),
673 void *data, int *dma_ch_out)
675 int ch, free_ch = -1;
677 struct omap_dma_lch *chan;
679 spin_lock_irqsave(&dma_chan_lock, flags);
680 for (ch = 0; ch < dma_chan_count; ch++) {
681 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
688 spin_unlock_irqrestore(&dma_chan_lock, flags);
691 chan = dma_chan + free_ch;
692 chan->dev_id = dev_id;
694 if (p->clear_lch_regs)
695 p->clear_lch_regs(free_ch);
697 if (cpu_class_is_omap2())
698 omap_clear_dma(free_ch);
700 spin_unlock_irqrestore(&dma_chan_lock, flags);
702 chan->dev_name = dev_name;
703 chan->callback = callback;
707 #ifndef CONFIG_ARCH_OMAP1
708 if (cpu_class_is_omap2()) {
710 chan->next_linked_ch = -1;
714 chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
716 if (cpu_class_is_omap1())
717 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
718 else if (cpu_class_is_omap2())
719 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
720 OMAP2_DMA_TRANS_ERR_IRQ;
722 if (cpu_is_omap16xx()) {
723 /* If the sync device is set, configure it dynamically. */
725 set_gdma_dev(free_ch + 1, dev_id);
726 dev_id = free_ch + 1;
729 * Disable the 1510 compatibility mode and set the sync device
732 p->dma_write(dev_id | (1 << 10), CCR, free_ch);
733 } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) {
734 p->dma_write(dev_id, CCR, free_ch);
737 if (cpu_class_is_omap2()) {
738 omap2_enable_irq_lch(free_ch);
739 omap_enable_channel_irq(free_ch);
740 /* Clear the CSR register and IRQ status register */
741 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, free_ch);
742 p->dma_write(1 << free_ch, IRQSTATUS_L0, 0);
745 *dma_ch_out = free_ch;
749 EXPORT_SYMBOL(omap_request_dma);
751 void omap_free_dma(int lch)
755 if (dma_chan[lch].dev_id == -1) {
756 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
761 if (cpu_class_is_omap1()) {
762 /* Disable all DMA interrupts for the channel. */
763 p->dma_write(0, CICR, lch);
764 /* Make sure the DMA transfer is stopped. */
765 p->dma_write(0, CCR, lch);
768 if (cpu_class_is_omap2()) {
769 omap2_disable_irq_lch(lch);
771 /* Clear the CSR register and IRQ status register */
772 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
773 p->dma_write(1 << lch, IRQSTATUS_L0, lch);
775 /* Disable all DMA interrupts for the channel. */
776 p->dma_write(0, CICR, lch);
778 /* Make sure the DMA transfer is stopped. */
779 p->dma_write(0, CCR, lch);
783 spin_lock_irqsave(&dma_chan_lock, flags);
784 dma_chan[lch].dev_id = -1;
785 dma_chan[lch].next_lch = -1;
786 dma_chan[lch].callback = NULL;
787 spin_unlock_irqrestore(&dma_chan_lock, flags);
789 EXPORT_SYMBOL(omap_free_dma);
792 * @brief omap_dma_set_global_params : Set global priority settings for dma
795 * @param max_fifo_depth
796 * @param tparams - Number of threads to reserve : DMA_THREAD_RESERVE_NORM
797 * DMA_THREAD_RESERVE_ONET
798 * DMA_THREAD_RESERVE_TWOT
799 * DMA_THREAD_RESERVE_THREET
802 omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
806 if (!cpu_class_is_omap2()) {
807 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
811 if (max_fifo_depth == 0)
816 reg = 0xff & max_fifo_depth;
817 reg |= (0x3 & tparams) << 12;
818 reg |= (arb_rate & 0xff) << 16;
820 p->dma_write(reg, GCR, 0);
822 EXPORT_SYMBOL(omap_dma_set_global_params);
825 * @brief omap_dma_set_prio_lch : Set channel wise priority settings
828 * @param read_prio - Read priority
829 * @param write_prio - Write priority
830 * Both of the above can be set with one of the following values :
831 * DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
834 omap_dma_set_prio_lch(int lch, unsigned char read_prio,
835 unsigned char write_prio)
839 if (unlikely((lch < 0 || lch >= dma_lch_count))) {
840 printk(KERN_ERR "Invalid channel id\n");
843 l = p->dma_read(CCR, lch);
844 l &= ~((1 << 6) | (1 << 26));
845 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx())
846 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
848 l |= ((read_prio & 0x1) << 6);
850 p->dma_write(l, CCR, lch);
854 EXPORT_SYMBOL(omap_dma_set_prio_lch);
857 * Clears any DMA state so the DMA engine is ready to restart with new buffers
858 * through omap_start_dma(). Any buffers in flight are discarded.
860 void omap_clear_dma(int lch)
864 local_irq_save(flags);
866 local_irq_restore(flags);
868 EXPORT_SYMBOL(omap_clear_dma);
870 void omap_start_dma(int lch)
875 * The CPC/CDAC register needs to be initialized to zero
876 * before starting dma transfer.
878 if (cpu_is_omap15xx())
879 p->dma_write(0, CPC, lch);
881 p->dma_write(0, CDAC, lch);
883 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
884 int next_lch, cur_lch;
885 char dma_chan_link_map[dma_lch_count];
887 dma_chan_link_map[lch] = 1;
888 /* Set the link register of the first channel */
891 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
892 cur_lch = dma_chan[lch].next_lch;
894 next_lch = dma_chan[cur_lch].next_lch;
896 /* The loop case: we've been here already */
897 if (dma_chan_link_map[cur_lch])
899 /* Mark the current channel */
900 dma_chan_link_map[cur_lch] = 1;
903 omap_enable_channel_irq(cur_lch);
906 } while (next_lch != -1);
907 } else if (IS_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS))
908 p->dma_write(lch, CLNK_CTRL, lch);
910 omap_enable_channel_irq(lch);
912 l = p->dma_read(CCR, lch);
914 if (IS_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING))
915 l |= OMAP_DMA_CCR_BUFFERING_DISABLE;
916 l |= OMAP_DMA_CCR_EN;
918 p->dma_write(l, CCR, lch);
920 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
922 EXPORT_SYMBOL(omap_start_dma);
924 void omap_stop_dma(int lch)
928 /* Disable all interrupts on the channel */
929 if (cpu_class_is_omap1())
930 p->dma_write(0, CICR, lch);
932 l = p->dma_read(CCR, lch);
933 if (IS_DMA_ERRATA(DMA_ERRATA_i541) &&
934 (l & OMAP_DMA_CCR_SEL_SRC_DST_SYNC)) {
938 /* Configure No-Standby */
939 l = p->dma_read(OCP_SYSCONFIG, lch);
941 l &= ~DMA_SYSCONFIG_MIDLEMODE_MASK;
942 l |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE);
943 p->dma_write(l , OCP_SYSCONFIG, 0);
945 l = p->dma_read(CCR, lch);
946 l &= ~OMAP_DMA_CCR_EN;
947 p->dma_write(l, CCR, lch);
949 /* Wait for sDMA FIFO drain */
950 l = p->dma_read(CCR, lch);
951 while (i < 100 && (l & (OMAP_DMA_CCR_RD_ACTIVE |
952 OMAP_DMA_CCR_WR_ACTIVE))) {
955 l = p->dma_read(CCR, lch);
958 printk(KERN_ERR "DMA drain did not complete on "
960 /* Restore OCP_SYSCONFIG */
961 p->dma_write(sys_cf, OCP_SYSCONFIG, lch);
963 l &= ~OMAP_DMA_CCR_EN;
964 p->dma_write(l, CCR, lch);
967 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
968 int next_lch, cur_lch = lch;
969 char dma_chan_link_map[dma_lch_count];
971 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
973 /* The loop case: we've been here already */
974 if (dma_chan_link_map[cur_lch])
976 /* Mark the current channel */
977 dma_chan_link_map[cur_lch] = 1;
979 disable_lnk(cur_lch);
981 next_lch = dma_chan[cur_lch].next_lch;
983 } while (next_lch != -1);
986 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
988 EXPORT_SYMBOL(omap_stop_dma);
991 * Allows changing the DMA callback function or data. This may be needed if
992 * the driver shares a single DMA channel for multiple dma triggers.
994 int omap_set_dma_callback(int lch,
995 void (*callback)(int lch, u16 ch_status, void *data),
1003 spin_lock_irqsave(&dma_chan_lock, flags);
1004 if (dma_chan[lch].dev_id == -1) {
1005 printk(KERN_ERR "DMA callback for not set for free channel\n");
1006 spin_unlock_irqrestore(&dma_chan_lock, flags);
1009 dma_chan[lch].callback = callback;
1010 dma_chan[lch].data = data;
1011 spin_unlock_irqrestore(&dma_chan_lock, flags);
1015 EXPORT_SYMBOL(omap_set_dma_callback);
1018 * Returns current physical source address for the given DMA channel.
1019 * If the channel is running the caller must disable interrupts prior calling
1020 * this function and process the returned value before re-enabling interrupt to
1021 * prevent races with the interrupt handler. Note that in continuous mode there
1022 * is a chance for CSSA_L register overflow between the two reads resulting
1023 * in incorrect return value.
1025 dma_addr_t omap_get_dma_src_pos(int lch)
1027 dma_addr_t offset = 0;
1029 if (cpu_is_omap15xx())
1030 offset = p->dma_read(CPC, lch);
1032 offset = p->dma_read(CSAC, lch);
1034 if (IS_DMA_ERRATA(DMA_ERRATA_3_3) && offset == 0)
1035 offset = p->dma_read(CSAC, lch);
1037 if (!cpu_is_omap15xx()) {
1039 * CDAC == 0 indicates that the DMA transfer on the channel has
1040 * not been started (no data has been transferred so far).
1041 * Return the programmed source start address in this case.
1043 if (likely(p->dma_read(CDAC, lch)))
1044 offset = p->dma_read(CSAC, lch);
1046 offset = p->dma_read(CSSA, lch);
1049 if (cpu_class_is_omap1())
1050 offset |= (p->dma_read(CSSA, lch) & 0xFFFF0000);
1054 EXPORT_SYMBOL(omap_get_dma_src_pos);
1057 * Returns current physical destination address for the given DMA channel.
1058 * If the channel is running the caller must disable interrupts prior calling
1059 * this function and process the returned value before re-enabling interrupt to
1060 * prevent races with the interrupt handler. Note that in continuous mode there
1061 * is a chance for CDSA_L register overflow between the two reads resulting
1062 * in incorrect return value.
1064 dma_addr_t omap_get_dma_dst_pos(int lch)
1066 dma_addr_t offset = 0;
1068 if (cpu_is_omap15xx())
1069 offset = p->dma_read(CPC, lch);
1071 offset = p->dma_read(CDAC, lch);
1074 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1075 * read before the DMA controller finished disabling the channel.
1077 if (!cpu_is_omap15xx() && offset == 0)
1078 offset = p->dma_read(CDAC, lch);
1080 if (cpu_class_is_omap1())
1081 offset |= (p->dma_read(CDSA, lch) & 0xFFFF0000);
1085 EXPORT_SYMBOL(omap_get_dma_dst_pos);
1087 int omap_get_dma_active_status(int lch)
1089 return (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN) != 0;
1091 EXPORT_SYMBOL(omap_get_dma_active_status);
1093 int omap_dma_running(void)
1097 if (cpu_class_is_omap1())
1098 if (omap_lcd_dma_running())
1101 for (lch = 0; lch < dma_chan_count; lch++)
1102 if (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN)
1109 * lch_queue DMA will start right after lch_head one is finished.
1110 * For this DMA link to start, you still need to start (see omap_start_dma)
1111 * the first one. That will fire up the entire queue.
1113 void omap_dma_link_lch(int lch_head, int lch_queue)
1115 if (omap_dma_in_1510_mode()) {
1116 if (lch_head == lch_queue) {
1117 p->dma_write(p->dma_read(CCR, lch_head) | (3 << 8),
1121 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1126 if ((dma_chan[lch_head].dev_id == -1) ||
1127 (dma_chan[lch_queue].dev_id == -1)) {
1128 printk(KERN_ERR "omap_dma: trying to link "
1129 "non requested channels\n");
1133 dma_chan[lch_head].next_lch = lch_queue;
1135 EXPORT_SYMBOL(omap_dma_link_lch);
1138 * Once the DMA queue is stopped, we can destroy it.
1140 void omap_dma_unlink_lch(int lch_head, int lch_queue)
1142 if (omap_dma_in_1510_mode()) {
1143 if (lch_head == lch_queue) {
1144 p->dma_write(p->dma_read(CCR, lch_head) & ~(3 << 8),
1148 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1153 if (dma_chan[lch_head].next_lch != lch_queue ||
1154 dma_chan[lch_head].next_lch == -1) {
1155 printk(KERN_ERR "omap_dma: trying to unlink "
1156 "non linked channels\n");
1160 if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
1161 (dma_chan[lch_queue].flags & OMAP_DMA_ACTIVE)) {
1162 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
1163 "before unlinking\n");
1167 dma_chan[lch_head].next_lch = -1;
1169 EXPORT_SYMBOL(omap_dma_unlink_lch);
1171 #ifndef CONFIG_ARCH_OMAP1
1172 /* Create chain of DMA channesls */
1173 static void create_dma_lch_chain(int lch_head, int lch_queue)
1177 /* Check if this is the first link in chain */
1178 if (dma_chan[lch_head].next_linked_ch == -1) {
1179 dma_chan[lch_head].next_linked_ch = lch_queue;
1180 dma_chan[lch_head].prev_linked_ch = lch_queue;
1181 dma_chan[lch_queue].next_linked_ch = lch_head;
1182 dma_chan[lch_queue].prev_linked_ch = lch_head;
1185 /* a link exists, link the new channel in circular chain */
1187 dma_chan[lch_queue].next_linked_ch =
1188 dma_chan[lch_head].next_linked_ch;
1189 dma_chan[lch_queue].prev_linked_ch = lch_head;
1190 dma_chan[lch_head].next_linked_ch = lch_queue;
1191 dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
1195 l = p->dma_read(CLNK_CTRL, lch_head);
1198 p->dma_write(l, CLNK_CTRL, lch_head);
1200 l = p->dma_read(CLNK_CTRL, lch_queue);
1202 l |= (dma_chan[lch_queue].next_linked_ch);
1203 p->dma_write(l, CLNK_CTRL, lch_queue);
1207 * @brief omap_request_dma_chain : Request a chain of DMA channels
1209 * @param dev_id - Device id using the dma channel
1210 * @param dev_name - Device name
1211 * @param callback - Call back function
1213 * @no_of_chans - Number of channels requested
1214 * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1215 * OMAP_DMA_DYNAMIC_CHAIN
1216 * @params - Channel parameters
1218 * @return - Success : 0
1219 * Failure: -EINVAL/-ENOMEM
1221 int omap_request_dma_chain(int dev_id, const char *dev_name,
1222 void (*callback) (int lch, u16 ch_status,
1224 int *chain_id, int no_of_chans, int chain_mode,
1225 struct omap_dma_channel_params params)
1230 /* Is the chain mode valid ? */
1231 if (chain_mode != OMAP_DMA_STATIC_CHAIN
1232 && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
1233 printk(KERN_ERR "Invalid chain mode requested\n");
1237 if (unlikely((no_of_chans < 1
1238 || no_of_chans > dma_lch_count))) {
1239 printk(KERN_ERR "Invalid Number of channels requested\n");
1244 * Allocate a queue to maintain the status of the channels
1247 channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
1248 if (channels == NULL) {
1249 printk(KERN_ERR "omap_dma: No memory for channel queue\n");
1253 /* request and reserve DMA channels for the chain */
1254 for (i = 0; i < no_of_chans; i++) {
1255 err = omap_request_dma(dev_id, dev_name,
1256 callback, NULL, &channels[i]);
1259 for (j = 0; j < i; j++)
1260 omap_free_dma(channels[j]);
1262 printk(KERN_ERR "omap_dma: Request failed %d\n", err);
1265 dma_chan[channels[i]].prev_linked_ch = -1;
1266 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1269 * Allowing client drivers to set common parameters now,
1270 * so that later only relevant (src_start, dest_start
1271 * and element count) can be set
1273 omap_set_dma_params(channels[i], ¶ms);
1276 *chain_id = channels[0];
1277 dma_linked_lch[*chain_id].linked_dmach_q = channels;
1278 dma_linked_lch[*chain_id].chain_mode = chain_mode;
1279 dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1280 dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;
1282 for (i = 0; i < no_of_chans; i++)
1283 dma_chan[channels[i]].chain_id = *chain_id;
1285 /* Reset the Queue pointers */
1286 OMAP_DMA_CHAIN_QINIT(*chain_id);
1288 /* Set up the chain */
1289 if (no_of_chans == 1)
1290 create_dma_lch_chain(channels[0], channels[0]);
1292 for (i = 0; i < (no_of_chans - 1); i++)
1293 create_dma_lch_chain(channels[i], channels[i + 1]);
1298 EXPORT_SYMBOL(omap_request_dma_chain);
1301 * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1302 * params after setting it. Dont do this while dma is running!!
1304 * @param chain_id - Chained logical channel id.
1307 * @return - Success : 0
1310 int omap_modify_dma_chain_params(int chain_id,
1311 struct omap_dma_channel_params params)
1316 /* Check for input params */
1317 if (unlikely((chain_id < 0
1318 || chain_id >= dma_lch_count))) {
1319 printk(KERN_ERR "Invalid chain id\n");
1323 /* Check if the chain exists */
1324 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1325 printk(KERN_ERR "Chain doesn't exists\n");
1328 channels = dma_linked_lch[chain_id].linked_dmach_q;
1330 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1332 * Allowing client drivers to set common parameters now,
1333 * so that later only relevant (src_start, dest_start
1334 * and element count) can be set
1336 omap_set_dma_params(channels[i], ¶ms);
1341 EXPORT_SYMBOL(omap_modify_dma_chain_params);
1344 * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1348 * @return - Success : 0
1351 int omap_free_dma_chain(int chain_id)
1356 /* Check for input params */
1357 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1358 printk(KERN_ERR "Invalid chain id\n");
1362 /* Check if the chain exists */
1363 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1364 printk(KERN_ERR "Chain doesn't exists\n");
1368 channels = dma_linked_lch[chain_id].linked_dmach_q;
1369 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1370 dma_chan[channels[i]].next_linked_ch = -1;
1371 dma_chan[channels[i]].prev_linked_ch = -1;
1372 dma_chan[channels[i]].chain_id = -1;
1373 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1374 omap_free_dma(channels[i]);
1379 dma_linked_lch[chain_id].linked_dmach_q = NULL;
1380 dma_linked_lch[chain_id].chain_mode = -1;
1381 dma_linked_lch[chain_id].chain_state = -1;
1385 EXPORT_SYMBOL(omap_free_dma_chain);
1388 * @brief omap_dma_chain_status - Check if the chain is in
1389 * active / inactive state.
1392 * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1395 int omap_dma_chain_status(int chain_id)
1397 /* Check for input params */
1398 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1399 printk(KERN_ERR "Invalid chain id\n");
1403 /* Check if the chain exists */
1404 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1405 printk(KERN_ERR "Chain doesn't exists\n");
1408 pr_debug("CHAINID=%d, qcnt=%d\n", chain_id,
1409 dma_linked_lch[chain_id].q_count);
1411 if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
1412 return OMAP_DMA_CHAIN_INACTIVE;
1414 return OMAP_DMA_CHAIN_ACTIVE;
1416 EXPORT_SYMBOL(omap_dma_chain_status);
1419 * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1420 * set the params and start the transfer.
1423 * @param src_start - buffer start address
1424 * @param dest_start - Dest address
1426 * @param frame_count
1427 * @param callbk_data - channel callback parameter data.
1429 * @return - Success : 0
1430 * Failure: -EINVAL/-EBUSY
1432 int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1433 int elem_count, int frame_count, void *callbk_data)
1440 * if buffer size is less than 1 then there is
1441 * no use of starting the chain
1443 if (elem_count < 1) {
1444 printk(KERN_ERR "Invalid buffer size\n");
1448 /* Check for input params */
1449 if (unlikely((chain_id < 0
1450 || chain_id >= dma_lch_count))) {
1451 printk(KERN_ERR "Invalid chain id\n");
1455 /* Check if the chain exists */
1456 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1457 printk(KERN_ERR "Chain doesn't exist\n");
1461 /* Check if all the channels in chain are in use */
1462 if (OMAP_DMA_CHAIN_QFULL(chain_id))
1465 /* Frame count may be negative in case of indexed transfers */
1466 channels = dma_linked_lch[chain_id].linked_dmach_q;
1468 /* Get a free channel */
1469 lch = channels[dma_linked_lch[chain_id].q_tail];
1471 /* Store the callback data */
1472 dma_chan[lch].data = callbk_data;
1474 /* Increment the q_tail */
1475 OMAP_DMA_CHAIN_INCQTAIL(chain_id);
1477 /* Set the params to the free channel */
1479 p->dma_write(src_start, CSSA, lch);
1480 if (dest_start != 0)
1481 p->dma_write(dest_start, CDSA, lch);
1483 /* Write the buffer size */
1484 p->dma_write(elem_count, CEN, lch);
1485 p->dma_write(frame_count, CFN, lch);
1488 * If the chain is dynamically linked,
1489 * then we may have to start the chain if its not active
1491 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
1494 * In Dynamic chain, if the chain is not started,
1497 if (dma_linked_lch[chain_id].chain_state ==
1498 DMA_CHAIN_NOTSTARTED) {
1499 /* Enable the link in previous channel */
1500 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1502 enable_lnk(dma_chan[lch].prev_linked_ch);
1503 dma_chan[lch].state = DMA_CH_QUEUED;
1507 * Chain is already started, make sure its active,
1508 * if not then start the chain
1513 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1515 enable_lnk(dma_chan[lch].prev_linked_ch);
1516 dma_chan[lch].state = DMA_CH_QUEUED;
1518 if (0 == ((1 << 7) & p->dma_read(
1519 CCR, dma_chan[lch].prev_linked_ch))) {
1520 disable_lnk(dma_chan[lch].
1522 pr_debug("\n prev ch is stopped\n");
1527 else if (dma_chan[dma_chan[lch].prev_linked_ch].state
1529 enable_lnk(dma_chan[lch].prev_linked_ch);
1530 dma_chan[lch].state = DMA_CH_QUEUED;
1533 omap_enable_channel_irq(lch);
1535 l = p->dma_read(CCR, lch);
1537 if ((0 == (l & (1 << 24))))
1541 if (start_dma == 1) {
1542 if (0 == (l & (1 << 7))) {
1544 dma_chan[lch].state = DMA_CH_STARTED;
1545 pr_debug("starting %d\n", lch);
1546 p->dma_write(l, CCR, lch);
1550 if (0 == (l & (1 << 7)))
1551 p->dma_write(l, CCR, lch);
1553 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1559 EXPORT_SYMBOL(omap_dma_chain_a_transfer);
1562 * @brief omap_start_dma_chain_transfers - Start the chain
1566 * @return - Success : 0
1567 * Failure : -EINVAL/-EBUSY
1569 int omap_start_dma_chain_transfers(int chain_id)
1574 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1575 printk(KERN_ERR "Invalid chain id\n");
1579 channels = dma_linked_lch[chain_id].linked_dmach_q;
1581 if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
1582 printk(KERN_ERR "Chain is already started\n");
1586 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
1587 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
1589 enable_lnk(channels[i]);
1590 omap_enable_channel_irq(channels[i]);
1593 omap_enable_channel_irq(channels[0]);
1596 l = p->dma_read(CCR, channels[0]);
1598 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
1599 dma_chan[channels[0]].state = DMA_CH_STARTED;
1601 if ((0 == (l & (1 << 24))))
1605 p->dma_write(l, CCR, channels[0]);
1607 dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
1611 EXPORT_SYMBOL(omap_start_dma_chain_transfers);
1614 * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1618 * @return - Success : 0
1621 int omap_stop_dma_chain_transfers(int chain_id)
1627 /* Check for input params */
1628 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1629 printk(KERN_ERR "Invalid chain id\n");
1633 /* Check if the chain exists */
1634 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1635 printk(KERN_ERR "Chain doesn't exists\n");
1638 channels = dma_linked_lch[chain_id].linked_dmach_q;
1640 if (IS_DMA_ERRATA(DMA_ERRATA_i88)) {
1641 sys_cf = p->dma_read(OCP_SYSCONFIG, 0);
1643 /* Middle mode reg set no Standby */
1644 l &= ~((1 << 12)|(1 << 13));
1645 p->dma_write(l, OCP_SYSCONFIG, 0);
1648 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1650 /* Stop the Channel transmission */
1651 l = p->dma_read(CCR, channels[i]);
1653 p->dma_write(l, CCR, channels[i]);
1655 /* Disable the link in all the channels */
1656 disable_lnk(channels[i]);
1657 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1660 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1662 /* Reset the Queue pointers */
1663 OMAP_DMA_CHAIN_QINIT(chain_id);
1665 if (IS_DMA_ERRATA(DMA_ERRATA_i88))
1666 p->dma_write(sys_cf, OCP_SYSCONFIG, 0);
1670 EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
1672 /* Get the index of the ongoing DMA in chain */
1674 * @brief omap_get_dma_chain_index - Get the element and frame index
1675 * of the ongoing DMA in chain
1678 * @param ei - Element index
1679 * @param fi - Frame index
1681 * @return - Success : 0
1684 int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1689 /* Check for input params */
1690 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1691 printk(KERN_ERR "Invalid chain id\n");
1695 /* Check if the chain exists */
1696 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1697 printk(KERN_ERR "Chain doesn't exists\n");
1703 channels = dma_linked_lch[chain_id].linked_dmach_q;
1705 /* Get the current channel */
1706 lch = channels[dma_linked_lch[chain_id].q_head];
1708 *ei = p->dma_read(CCEN, lch);
1709 *fi = p->dma_read(CCFN, lch);
1713 EXPORT_SYMBOL(omap_get_dma_chain_index);
1716 * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1717 * ongoing DMA in chain
1721 * @return - Success : Destination position
1724 int omap_get_dma_chain_dst_pos(int chain_id)
1729 /* Check for input params */
1730 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1731 printk(KERN_ERR "Invalid chain id\n");
1735 /* Check if the chain exists */
1736 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1737 printk(KERN_ERR "Chain doesn't exists\n");
1741 channels = dma_linked_lch[chain_id].linked_dmach_q;
1743 /* Get the current channel */
1744 lch = channels[dma_linked_lch[chain_id].q_head];
1746 return p->dma_read(CDAC, lch);
1748 EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
1751 * @brief omap_get_dma_chain_src_pos - Get the source position
1752 * of the ongoing DMA in chain
1755 * @return - Success : Destination position
1758 int omap_get_dma_chain_src_pos(int chain_id)
1763 /* Check for input params */
1764 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1765 printk(KERN_ERR "Invalid chain id\n");
1769 /* Check if the chain exists */
1770 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1771 printk(KERN_ERR "Chain doesn't exists\n");
1775 channels = dma_linked_lch[chain_id].linked_dmach_q;
1777 /* Get the current channel */
1778 lch = channels[dma_linked_lch[chain_id].q_head];
1780 return p->dma_read(CSAC, lch);
1782 EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
1783 #endif /* ifndef CONFIG_ARCH_OMAP1 */
1785 /*----------------------------------------------------------------------------*/
1787 #ifdef CONFIG_ARCH_OMAP1
1789 static int omap1_dma_handle_ch(int ch)
1793 if (enable_1510_mode && ch >= 6) {
1794 csr = dma_chan[ch].saved_csr;
1795 dma_chan[ch].saved_csr = 0;
1797 csr = p->dma_read(CSR, ch);
1798 if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1799 dma_chan[ch + 6].saved_csr = csr >> 7;
1802 if ((csr & 0x3f) == 0)
1804 if (unlikely(dma_chan[ch].dev_id == -1)) {
1805 printk(KERN_WARNING "Spurious interrupt from DMA channel "
1806 "%d (CSR %04x)\n", ch, csr);
1809 if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
1810 printk(KERN_WARNING "DMA timeout with device %d\n",
1811 dma_chan[ch].dev_id);
1812 if (unlikely(csr & OMAP_DMA_DROP_IRQ))
1813 printk(KERN_WARNING "DMA synchronization event drop occurred "
1814 "with device %d\n", dma_chan[ch].dev_id);
1815 if (likely(csr & OMAP_DMA_BLOCK_IRQ))
1816 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1817 if (likely(dma_chan[ch].callback != NULL))
1818 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
1823 static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1825 int ch = ((int) dev_id) - 1;
1829 int handled_now = 0;
1831 handled_now += omap1_dma_handle_ch(ch);
1832 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
1833 handled_now += omap1_dma_handle_ch(ch + 6);
1836 handled += handled_now;
1839 return handled ? IRQ_HANDLED : IRQ_NONE;
1843 #define omap1_dma_irq_handler NULL
1846 #ifdef CONFIG_ARCH_OMAP2PLUS
1848 static int omap2_dma_handle_ch(int ch)
1850 u32 status = p->dma_read(CSR, ch);
1853 if (printk_ratelimit())
1854 printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
1856 p->dma_write(1 << ch, IRQSTATUS_L0, ch);
1859 if (unlikely(dma_chan[ch].dev_id == -1)) {
1860 if (printk_ratelimit())
1861 printk(KERN_WARNING "IRQ %04x for non-allocated DMA"
1862 "channel %d\n", status, ch);
1865 if (unlikely(status & OMAP_DMA_DROP_IRQ))
1867 "DMA synchronization event drop occurred with device "
1868 "%d\n", dma_chan[ch].dev_id);
1869 if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
1870 printk(KERN_INFO "DMA transaction error with device %d\n",
1871 dma_chan[ch].dev_id);
1872 if (IS_DMA_ERRATA(DMA_ERRATA_i378)) {
1875 ccr = p->dma_read(CCR, ch);
1876 ccr &= ~OMAP_DMA_CCR_EN;
1877 p->dma_write(ccr, CCR, ch);
1878 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1881 if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
1882 printk(KERN_INFO "DMA secure error with device %d\n",
1883 dma_chan[ch].dev_id);
1884 if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
1885 printk(KERN_INFO "DMA misaligned error with device %d\n",
1886 dma_chan[ch].dev_id);
1888 p->dma_write(status, CSR, ch);
1889 p->dma_write(1 << ch, IRQSTATUS_L0, ch);
1890 /* read back the register to flush the write */
1891 p->dma_read(IRQSTATUS_L0, ch);
1893 /* If the ch is not chained then chain_id will be -1 */
1894 if (dma_chan[ch].chain_id != -1) {
1895 int chain_id = dma_chan[ch].chain_id;
1896 dma_chan[ch].state = DMA_CH_NOTSTARTED;
1897 if (p->dma_read(CLNK_CTRL, ch) & (1 << 15))
1898 dma_chan[dma_chan[ch].next_linked_ch].state =
1900 if (dma_linked_lch[chain_id].chain_mode ==
1901 OMAP_DMA_DYNAMIC_CHAIN)
1904 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1905 OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1907 status = p->dma_read(CSR, ch);
1908 p->dma_write(status, CSR, ch);
1911 if (likely(dma_chan[ch].callback != NULL))
1912 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1917 /* STATUS register count is from 1-32 while our is 0-31 */
1918 static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1920 u32 val, enable_reg;
1923 val = p->dma_read(IRQSTATUS_L0, 0);
1925 if (printk_ratelimit())
1926 printk(KERN_WARNING "Spurious DMA IRQ\n");
1929 enable_reg = p->dma_read(IRQENABLE_L0, 0);
1930 val &= enable_reg; /* Dispatch only relevant interrupts */
1931 for (i = 0; i < dma_lch_count && val != 0; i++) {
1933 omap2_dma_handle_ch(i);
1940 static struct irqaction omap24xx_dma_irq = {
1942 .handler = omap2_dma_irq_handler,
1943 .flags = IRQF_DISABLED
1947 static struct irqaction omap24xx_dma_irq;
1950 /*----------------------------------------------------------------------------*/
1952 void omap_dma_global_context_save(void)
1954 omap_dma_global_context.dma_irqenable_l0 =
1955 p->dma_read(IRQENABLE_L0, 0);
1956 omap_dma_global_context.dma_ocp_sysconfig =
1957 p->dma_read(OCP_SYSCONFIG, 0);
1958 omap_dma_global_context.dma_gcr = p->dma_read(GCR, 0);
1961 void omap_dma_global_context_restore(void)
1965 p->dma_write(omap_dma_global_context.dma_gcr, GCR, 0);
1966 p->dma_write(omap_dma_global_context.dma_ocp_sysconfig,
1968 p->dma_write(omap_dma_global_context.dma_irqenable_l0,
1971 if (IS_DMA_ERRATA(DMA_ROMCODE_BUG))
1972 p->dma_write(0x3 , IRQSTATUS_L0, 0);
1974 for (ch = 0; ch < dma_chan_count; ch++)
1975 if (dma_chan[ch].dev_id != -1)
1979 static int __devinit omap_system_dma_probe(struct platform_device *pdev)
1986 p = pdev->dev.platform_data;
1988 dev_err(&pdev->dev, "%s: System DMA initialized without"
1989 "platform data\n", __func__);
1996 if ((d->dev_caps & RESERVE_CHANNEL) && omap_dma_reserve_channels
1997 && (omap_dma_reserve_channels <= dma_lch_count))
1998 d->lch_count = omap_dma_reserve_channels;
2000 dma_lch_count = d->lch_count;
2001 dma_chan_count = dma_lch_count;
2003 enable_1510_mode = d->dev_caps & ENABLE_1510_MODE;
2005 if (cpu_class_is_omap2()) {
2006 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
2007 dma_lch_count, GFP_KERNEL);
2008 if (!dma_linked_lch) {
2010 goto exit_dma_lch_fail;
2014 spin_lock_init(&dma_chan_lock);
2015 for (ch = 0; ch < dma_chan_count; ch++) {
2017 if (cpu_class_is_omap2())
2018 omap2_disable_irq_lch(ch);
2020 dma_chan[ch].dev_id = -1;
2021 dma_chan[ch].next_lch = -1;
2023 if (ch >= 6 && enable_1510_mode)
2026 if (cpu_class_is_omap1()) {
2028 * request_irq() doesn't like dev_id (ie. ch) being
2029 * zero, so we have to kludge around this.
2031 sprintf(&irq_name[0], "%d", ch);
2032 dma_irq = platform_get_irq_byname(pdev, irq_name);
2036 goto exit_dma_irq_fail;
2039 /* INT_DMA_LCD is handled in lcd_dma.c */
2040 if (dma_irq == INT_DMA_LCD)
2043 ret = request_irq(dma_irq,
2044 omap1_dma_irq_handler, 0, "DMA",
2047 goto exit_dma_irq_fail;
2051 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx())
2052 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
2053 DMA_DEFAULT_FIFO_DEPTH, 0);
2055 if (cpu_class_is_omap2()) {
2056 strcpy(irq_name, "0");
2057 dma_irq = platform_get_irq_byname(pdev, irq_name);
2059 dev_err(&pdev->dev, "failed: request IRQ %d", dma_irq);
2060 goto exit_dma_lch_fail;
2062 ret = setup_irq(dma_irq, &omap24xx_dma_irq);
2064 dev_err(&pdev->dev, "set_up failed for IRQ %d"
2065 "for DMA (error %d)\n", dma_irq, ret);
2066 goto exit_dma_lch_fail;
2070 /* reserve dma channels 0 and 1 in high security devices */
2071 if (cpu_is_omap34xx() &&
2072 (omap_type() != OMAP2_DEVICE_TYPE_GP)) {
2073 printk(KERN_INFO "Reserving DMA channels 0 and 1 for "
2075 dma_chan[0].dev_id = 0;
2076 dma_chan[1].dev_id = 1;
2082 dev_err(&pdev->dev, "unable to request IRQ %d"
2083 "for DMA (error %d)\n", dma_irq, ret);
2084 for (irq_rel = 0; irq_rel < ch; irq_rel++) {
2085 dma_irq = platform_get_irq(pdev, irq_rel);
2086 free_irq(dma_irq, (void *)(irq_rel + 1));
2096 static int __devexit omap_system_dma_remove(struct platform_device *pdev)
2100 if (cpu_class_is_omap2()) {
2102 strcpy(irq_name, "0");
2103 dma_irq = platform_get_irq_byname(pdev, irq_name);
2104 remove_irq(dma_irq, &omap24xx_dma_irq);
2107 for ( ; irq_rel < dma_chan_count; irq_rel++) {
2108 dma_irq = platform_get_irq(pdev, irq_rel);
2109 free_irq(dma_irq, (void *)(irq_rel + 1));
2118 static struct platform_driver omap_system_dma_driver = {
2119 .probe = omap_system_dma_probe,
2120 .remove = omap_system_dma_remove,
2122 .name = "omap_dma_system"
2126 static int __init omap_system_dma_init(void)
2128 return platform_driver_register(&omap_system_dma_driver);
2130 arch_initcall(omap_system_dma_init);
2132 static void __exit omap_system_dma_exit(void)
2134 platform_driver_unregister(&omap_system_dma_driver);
2137 MODULE_DESCRIPTION("OMAP SYSTEM DMA DRIVER");
2138 MODULE_LICENSE("GPL");
2139 MODULE_ALIAS("platform:" DRIVER_NAME);
2140 MODULE_AUTHOR("Texas Instruments Inc");
2143 * Reserve the omap SDMA channels using cmdline bootarg
2144 * "omap_dma_reserve_ch=". The valid range is 1 to 32
2146 static int __init omap_dma_cmdline_reserve_ch(char *str)
2148 if (get_option(&str, &omap_dma_reserve_channels) != 1)
2149 omap_dma_reserve_channels = 0;
2153 __setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch);