ARM: OMAP2+: DMA: Workaround for invalid source position
[pandora-kernel.git] / arch / arm / plat-omap / dma.c
1 /*
2  * linux/arch/arm/plat-omap/dma.c
3  *
4  * Copyright (C) 2003 - 2008 Nokia Corporation
5  * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6  * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7  * Graphics DMA and LCD DMA graphics tranformations
8  * by Imre Deak <imre.deak@nokia.com>
9  * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
10  * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
11  * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
12  *
13  * Copyright (C) 2009 Texas Instruments
14  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
15  *
16  * Support functions for the OMAP internal DMA channels.
17  *
18  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
19  * Converted DMA library into DMA platform driver.
20  *      - G, Manjunath Kondaiah <manjugk@ti.com>
21  *
22  * This program is free software; you can redistribute it and/or modify
23  * it under the terms of the GNU General Public License version 2 as
24  * published by the Free Software Foundation.
25  *
26  */
27
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/sched.h>
31 #include <linux/spinlock.h>
32 #include <linux/errno.h>
33 #include <linux/interrupt.h>
34 #include <linux/irq.h>
35 #include <linux/io.h>
36 #include <linux/slab.h>
37 #include <linux/delay.h>
38
39 #include <asm/system.h>
40 #include <mach/hardware.h>
41 #include <plat/dma.h>
42
43 #include <plat/tc.h>
44
45 #undef DEBUG
46
47 #ifndef CONFIG_ARCH_OMAP1
48 enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
49         DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
50 };
51
52 enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
53 #endif
54
55 #define OMAP_DMA_ACTIVE                 0x01
56 #define OMAP2_DMA_CSR_CLEAR_MASK        0xffffffff
57
58 #define OMAP_FUNC_MUX_ARM_BASE          (0xfffe1000 + 0xec)
59
60 static struct omap_system_dma_plat_info *p;
61 static struct omap_dma_dev_attr *d;
62
63 static int enable_1510_mode;
64 static u32 errata;
65
66 static struct omap_dma_global_context_registers {
67         u32 dma_irqenable_l0;
68         u32 dma_ocp_sysconfig;
69         u32 dma_gcr;
70 } omap_dma_global_context;
71
72 struct dma_link_info {
73         int *linked_dmach_q;
74         int no_of_lchs_linked;
75
76         int q_count;
77         int q_tail;
78         int q_head;
79
80         int chain_state;
81         int chain_mode;
82
83 };
84
85 static struct dma_link_info *dma_linked_lch;
86
87 #ifndef CONFIG_ARCH_OMAP1
88
89 /* Chain handling macros */
90 #define OMAP_DMA_CHAIN_QINIT(chain_id)                                  \
91         do {                                                            \
92                 dma_linked_lch[chain_id].q_head =                       \
93                 dma_linked_lch[chain_id].q_tail =                       \
94                 dma_linked_lch[chain_id].q_count = 0;                   \
95         } while (0)
96 #define OMAP_DMA_CHAIN_QFULL(chain_id)                                  \
97                 (dma_linked_lch[chain_id].no_of_lchs_linked ==          \
98                 dma_linked_lch[chain_id].q_count)
99 #define OMAP_DMA_CHAIN_QLAST(chain_id)                                  \
100         do {                                                            \
101                 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) ==      \
102                 dma_linked_lch[chain_id].q_count)                       \
103         } while (0)
104 #define OMAP_DMA_CHAIN_QEMPTY(chain_id)                                 \
105                 (0 == dma_linked_lch[chain_id].q_count)
106 #define __OMAP_DMA_CHAIN_INCQ(end)                                      \
107         ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
108 #define OMAP_DMA_CHAIN_INCQHEAD(chain_id)                               \
109         do {                                                            \
110                 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
111                 dma_linked_lch[chain_id].q_count--;                     \
112         } while (0)
113
114 #define OMAP_DMA_CHAIN_INCQTAIL(chain_id)                               \
115         do {                                                            \
116                 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
117                 dma_linked_lch[chain_id].q_count++; \
118         } while (0)
119 #endif
120
121 static int dma_lch_count;
122 static int dma_chan_count;
123 static int omap_dma_reserve_channels;
124
125 static spinlock_t dma_chan_lock;
126 static struct omap_dma_lch *dma_chan;
127
128 static inline void disable_lnk(int lch);
129 static void omap_disable_channel_irq(int lch);
130 static inline void omap_enable_channel_irq(int lch);
131
132 #define REVISIT_24XX()          printk(KERN_ERR "FIXME: no %s on 24xx\n", \
133                                                 __func__);
134
135 #ifdef CONFIG_ARCH_OMAP15XX
136 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
137 static int omap_dma_in_1510_mode(void)
138 {
139         return enable_1510_mode;
140 }
141 #else
142 #define omap_dma_in_1510_mode()         0
143 #endif
144
145 #ifdef CONFIG_ARCH_OMAP1
146 static inline int get_gdma_dev(int req)
147 {
148         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
149         int shift = ((req - 1) % 5) * 6;
150
151         return ((omap_readl(reg) >> shift) & 0x3f) + 1;
152 }
153
154 static inline void set_gdma_dev(int req, int dev)
155 {
156         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
157         int shift = ((req - 1) % 5) * 6;
158         u32 l;
159
160         l = omap_readl(reg);
161         l &= ~(0x3f << shift);
162         l |= (dev - 1) << shift;
163         omap_writel(l, reg);
164 }
165 #else
166 #define set_gdma_dev(req, dev)  do {} while (0)
167 #endif
168
169 void omap_set_dma_priority(int lch, int dst_port, int priority)
170 {
171         unsigned long reg;
172         u32 l;
173
174         if (cpu_class_is_omap1()) {
175                 switch (dst_port) {
176                 case OMAP_DMA_PORT_OCP_T1:      /* FFFECC00 */
177                         reg = OMAP_TC_OCPT1_PRIOR;
178                         break;
179                 case OMAP_DMA_PORT_OCP_T2:      /* FFFECCD0 */
180                         reg = OMAP_TC_OCPT2_PRIOR;
181                         break;
182                 case OMAP_DMA_PORT_EMIFF:       /* FFFECC08 */
183                         reg = OMAP_TC_EMIFF_PRIOR;
184                         break;
185                 case OMAP_DMA_PORT_EMIFS:       /* FFFECC04 */
186                         reg = OMAP_TC_EMIFS_PRIOR;
187                         break;
188                 default:
189                         BUG();
190                         return;
191                 }
192                 l = omap_readl(reg);
193                 l &= ~(0xf << 8);
194                 l |= (priority & 0xf) << 8;
195                 omap_writel(l, reg);
196         }
197
198         if (cpu_class_is_omap2()) {
199                 u32 ccr;
200
201                 ccr = p->dma_read(CCR, lch);
202                 if (priority)
203                         ccr |= (1 << 6);
204                 else
205                         ccr &= ~(1 << 6);
206                 p->dma_write(ccr, CCR, lch);
207         }
208 }
209 EXPORT_SYMBOL(omap_set_dma_priority);
210
211 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
212                                   int frame_count, int sync_mode,
213                                   int dma_trigger, int src_or_dst_synch)
214 {
215         u32 l;
216
217         l = p->dma_read(CSDP, lch);
218         l &= ~0x03;
219         l |= data_type;
220         p->dma_write(l, CSDP, lch);
221
222         if (cpu_class_is_omap1()) {
223                 u16 ccr;
224
225                 ccr = p->dma_read(CCR, lch);
226                 ccr &= ~(1 << 5);
227                 if (sync_mode == OMAP_DMA_SYNC_FRAME)
228                         ccr |= 1 << 5;
229                 p->dma_write(ccr, CCR, lch);
230
231                 ccr = p->dma_read(CCR2, lch);
232                 ccr &= ~(1 << 2);
233                 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
234                         ccr |= 1 << 2;
235                 p->dma_write(ccr, CCR2, lch);
236         }
237
238         if (cpu_class_is_omap2() && dma_trigger) {
239                 u32 val;
240
241                 val = p->dma_read(CCR, lch);
242
243                 /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
244                 val &= ~((1 << 23) | (3 << 19) | 0x1f);
245                 val |= (dma_trigger & ~0x1f) << 14;
246                 val |= dma_trigger & 0x1f;
247
248                 if (sync_mode & OMAP_DMA_SYNC_FRAME)
249                         val |= 1 << 5;
250                 else
251                         val &= ~(1 << 5);
252
253                 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
254                         val |= 1 << 18;
255                 else
256                         val &= ~(1 << 18);
257
258                 if (src_or_dst_synch == OMAP_DMA_DST_SYNC_PREFETCH) {
259                         val &= ~(1 << 24);      /* dest synch */
260                         val |= (1 << 23);       /* Prefetch */
261                 } else if (src_or_dst_synch) {
262                         val |= 1 << 24;         /* source synch */
263                 } else {
264                         val &= ~(1 << 24);      /* dest synch */
265                 }
266                 p->dma_write(val, CCR, lch);
267         }
268
269         p->dma_write(elem_count, CEN, lch);
270         p->dma_write(frame_count, CFN, lch);
271 }
272 EXPORT_SYMBOL(omap_set_dma_transfer_params);
273
274 void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
275 {
276         BUG_ON(omap_dma_in_1510_mode());
277
278         if (cpu_class_is_omap1()) {
279                 u16 w;
280
281                 w = p->dma_read(CCR2, lch);
282                 w &= ~0x03;
283
284                 switch (mode) {
285                 case OMAP_DMA_CONSTANT_FILL:
286                         w |= 0x01;
287                         break;
288                 case OMAP_DMA_TRANSPARENT_COPY:
289                         w |= 0x02;
290                         break;
291                 case OMAP_DMA_COLOR_DIS:
292                         break;
293                 default:
294                         BUG();
295                 }
296                 p->dma_write(w, CCR2, lch);
297
298                 w = p->dma_read(LCH_CTRL, lch);
299                 w &= ~0x0f;
300                 /* Default is channel type 2D */
301                 if (mode) {
302                         p->dma_write(color, COLOR, lch);
303                         w |= 1;         /* Channel type G */
304                 }
305                 p->dma_write(w, LCH_CTRL, lch);
306         }
307
308         if (cpu_class_is_omap2()) {
309                 u32 val;
310
311                 val = p->dma_read(CCR, lch);
312                 val &= ~((1 << 17) | (1 << 16));
313
314                 switch (mode) {
315                 case OMAP_DMA_CONSTANT_FILL:
316                         val |= 1 << 16;
317                         break;
318                 case OMAP_DMA_TRANSPARENT_COPY:
319                         val |= 1 << 17;
320                         break;
321                 case OMAP_DMA_COLOR_DIS:
322                         break;
323                 default:
324                         BUG();
325                 }
326                 p->dma_write(val, CCR, lch);
327
328                 color &= 0xffffff;
329                 p->dma_write(color, COLOR, lch);
330         }
331 }
332 EXPORT_SYMBOL(omap_set_dma_color_mode);
333
334 void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
335 {
336         if (cpu_class_is_omap2()) {
337                 u32 csdp;
338
339                 csdp = p->dma_read(CSDP, lch);
340                 csdp &= ~(0x3 << 16);
341                 csdp |= (mode << 16);
342                 p->dma_write(csdp, CSDP, lch);
343         }
344 }
345 EXPORT_SYMBOL(omap_set_dma_write_mode);
346
347 void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
348 {
349         if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
350                 u32 l;
351
352                 l = p->dma_read(LCH_CTRL, lch);
353                 l &= ~0x7;
354                 l |= mode;
355                 p->dma_write(l, LCH_CTRL, lch);
356         }
357 }
358 EXPORT_SYMBOL(omap_set_dma_channel_mode);
359
360 /* Note that src_port is only for omap1 */
361 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
362                              unsigned long src_start,
363                              int src_ei, int src_fi)
364 {
365         u32 l;
366
367         if (cpu_class_is_omap1()) {
368                 u16 w;
369
370                 w = p->dma_read(CSDP, lch);
371                 w &= ~(0x1f << 2);
372                 w |= src_port << 2;
373                 p->dma_write(w, CSDP, lch);
374         }
375
376         l = p->dma_read(CCR, lch);
377         l &= ~(0x03 << 12);
378         l |= src_amode << 12;
379         p->dma_write(l, CCR, lch);
380
381         p->dma_write(src_start, CSSA, lch);
382
383         p->dma_write(src_ei, CSEI, lch);
384         p->dma_write(src_fi, CSFI, lch);
385 }
386 EXPORT_SYMBOL(omap_set_dma_src_params);
387
388 void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
389 {
390         omap_set_dma_transfer_params(lch, params->data_type,
391                                      params->elem_count, params->frame_count,
392                                      params->sync_mode, params->trigger,
393                                      params->src_or_dst_synch);
394         omap_set_dma_src_params(lch, params->src_port,
395                                 params->src_amode, params->src_start,
396                                 params->src_ei, params->src_fi);
397
398         omap_set_dma_dest_params(lch, params->dst_port,
399                                  params->dst_amode, params->dst_start,
400                                  params->dst_ei, params->dst_fi);
401         if (params->read_prio || params->write_prio)
402                 omap_dma_set_prio_lch(lch, params->read_prio,
403                                       params->write_prio);
404 }
405 EXPORT_SYMBOL(omap_set_dma_params);
406
407 void omap_set_dma_src_index(int lch, int eidx, int fidx)
408 {
409         if (cpu_class_is_omap2())
410                 return;
411
412         p->dma_write(eidx, CSEI, lch);
413         p->dma_write(fidx, CSFI, lch);
414 }
415 EXPORT_SYMBOL(omap_set_dma_src_index);
416
417 void omap_set_dma_src_data_pack(int lch, int enable)
418 {
419         u32 l;
420
421         l = p->dma_read(CSDP, lch);
422         l &= ~(1 << 6);
423         if (enable)
424                 l |= (1 << 6);
425         p->dma_write(l, CSDP, lch);
426 }
427 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
428
429 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
430 {
431         unsigned int burst = 0;
432         u32 l;
433
434         l = p->dma_read(CSDP, lch);
435         l &= ~(0x03 << 7);
436
437         switch (burst_mode) {
438         case OMAP_DMA_DATA_BURST_DIS:
439                 break;
440         case OMAP_DMA_DATA_BURST_4:
441                 if (cpu_class_is_omap2())
442                         burst = 0x1;
443                 else
444                         burst = 0x2;
445                 break;
446         case OMAP_DMA_DATA_BURST_8:
447                 if (cpu_class_is_omap2()) {
448                         burst = 0x2;
449                         break;
450                 }
451                 /*
452                  * not supported by current hardware on OMAP1
453                  * w |= (0x03 << 7);
454                  * fall through
455                  */
456         case OMAP_DMA_DATA_BURST_16:
457                 if (cpu_class_is_omap2()) {
458                         burst = 0x3;
459                         break;
460                 }
461                 /*
462                  * OMAP1 don't support burst 16
463                  * fall through
464                  */
465         default:
466                 BUG();
467         }
468
469         l |= (burst << 7);
470         p->dma_write(l, CSDP, lch);
471 }
472 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
473
474 /* Note that dest_port is only for OMAP1 */
475 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
476                               unsigned long dest_start,
477                               int dst_ei, int dst_fi)
478 {
479         u32 l;
480
481         if (cpu_class_is_omap1()) {
482                 l = p->dma_read(CSDP, lch);
483                 l &= ~(0x1f << 9);
484                 l |= dest_port << 9;
485                 p->dma_write(l, CSDP, lch);
486         }
487
488         l = p->dma_read(CCR, lch);
489         l &= ~(0x03 << 14);
490         l |= dest_amode << 14;
491         p->dma_write(l, CCR, lch);
492
493         p->dma_write(dest_start, CDSA, lch);
494
495         p->dma_write(dst_ei, CDEI, lch);
496         p->dma_write(dst_fi, CDFI, lch);
497 }
498 EXPORT_SYMBOL(omap_set_dma_dest_params);
499
500 void omap_set_dma_dest_index(int lch, int eidx, int fidx)
501 {
502         if (cpu_class_is_omap2())
503                 return;
504
505         p->dma_write(eidx, CDEI, lch);
506         p->dma_write(fidx, CDFI, lch);
507 }
508 EXPORT_SYMBOL(omap_set_dma_dest_index);
509
510 void omap_set_dma_dest_data_pack(int lch, int enable)
511 {
512         u32 l;
513
514         l = p->dma_read(CSDP, lch);
515         l &= ~(1 << 13);
516         if (enable)
517                 l |= 1 << 13;
518         p->dma_write(l, CSDP, lch);
519 }
520 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
521
522 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
523 {
524         unsigned int burst = 0;
525         u32 l;
526
527         l = p->dma_read(CSDP, lch);
528         l &= ~(0x03 << 14);
529
530         switch (burst_mode) {
531         case OMAP_DMA_DATA_BURST_DIS:
532                 break;
533         case OMAP_DMA_DATA_BURST_4:
534                 if (cpu_class_is_omap2())
535                         burst = 0x1;
536                 else
537                         burst = 0x2;
538                 break;
539         case OMAP_DMA_DATA_BURST_8:
540                 if (cpu_class_is_omap2())
541                         burst = 0x2;
542                 else
543                         burst = 0x3;
544                 break;
545         case OMAP_DMA_DATA_BURST_16:
546                 if (cpu_class_is_omap2()) {
547                         burst = 0x3;
548                         break;
549                 }
550                 /*
551                  * OMAP1 don't support burst 16
552                  * fall through
553                  */
554         default:
555                 printk(KERN_ERR "Invalid DMA burst mode\n");
556                 BUG();
557                 return;
558         }
559         l |= (burst << 14);
560         p->dma_write(l, CSDP, lch);
561 }
562 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
563
564 static inline void omap_enable_channel_irq(int lch)
565 {
566         u32 status;
567
568         /* Clear CSR */
569         if (cpu_class_is_omap1())
570                 status = p->dma_read(CSR, lch);
571         else if (cpu_class_is_omap2())
572                 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
573
574         /* Enable some nice interrupts. */
575         p->dma_write(dma_chan[lch].enabled_irqs, CICR, lch);
576 }
577
578 static void omap_disable_channel_irq(int lch)
579 {
580         if (cpu_class_is_omap2())
581                 p->dma_write(0, CICR, lch);
582 }
583
584 void omap_enable_dma_irq(int lch, u16 bits)
585 {
586         dma_chan[lch].enabled_irqs |= bits;
587 }
588 EXPORT_SYMBOL(omap_enable_dma_irq);
589
590 void omap_disable_dma_irq(int lch, u16 bits)
591 {
592         dma_chan[lch].enabled_irqs &= ~bits;
593 }
594 EXPORT_SYMBOL(omap_disable_dma_irq);
595
596 static inline void enable_lnk(int lch)
597 {
598         u32 l;
599
600         l = p->dma_read(CLNK_CTRL, lch);
601
602         if (cpu_class_is_omap1())
603                 l &= ~(1 << 14);
604
605         /* Set the ENABLE_LNK bits */
606         if (dma_chan[lch].next_lch != -1)
607                 l = dma_chan[lch].next_lch | (1 << 15);
608
609 #ifndef CONFIG_ARCH_OMAP1
610         if (cpu_class_is_omap2())
611                 if (dma_chan[lch].next_linked_ch != -1)
612                         l = dma_chan[lch].next_linked_ch | (1 << 15);
613 #endif
614
615         p->dma_write(l, CLNK_CTRL, lch);
616 }
617
618 static inline void disable_lnk(int lch)
619 {
620         u32 l;
621
622         l = p->dma_read(CLNK_CTRL, lch);
623
624         /* Disable interrupts */
625         if (cpu_class_is_omap1()) {
626                 p->dma_write(0, CICR, lch);
627                 /* Set the STOP_LNK bit */
628                 l |= 1 << 14;
629         }
630
631         if (cpu_class_is_omap2()) {
632                 omap_disable_channel_irq(lch);
633                 /* Clear the ENABLE_LNK bit */
634                 l &= ~(1 << 15);
635         }
636
637         p->dma_write(l, CLNK_CTRL, lch);
638         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
639 }
640
641 static inline void omap2_enable_irq_lch(int lch)
642 {
643         u32 val;
644         unsigned long flags;
645
646         if (!cpu_class_is_omap2())
647                 return;
648
649         spin_lock_irqsave(&dma_chan_lock, flags);
650         val = p->dma_read(IRQENABLE_L0, lch);
651         val |= 1 << lch;
652         p->dma_write(val, IRQENABLE_L0, lch);
653         spin_unlock_irqrestore(&dma_chan_lock, flags);
654 }
655
656 static inline void omap2_disable_irq_lch(int lch)
657 {
658         u32 val;
659         unsigned long flags;
660
661         if (!cpu_class_is_omap2())
662                 return;
663
664         spin_lock_irqsave(&dma_chan_lock, flags);
665         val = p->dma_read(IRQENABLE_L0, lch);
666         val &= ~(1 << lch);
667         p->dma_write(val, IRQENABLE_L0, lch);
668         spin_unlock_irqrestore(&dma_chan_lock, flags);
669 }
670
671 int omap_request_dma(int dev_id, const char *dev_name,
672                      void (*callback)(int lch, u16 ch_status, void *data),
673                      void *data, int *dma_ch_out)
674 {
675         int ch, free_ch = -1;
676         unsigned long flags;
677         struct omap_dma_lch *chan;
678
679         spin_lock_irqsave(&dma_chan_lock, flags);
680         for (ch = 0; ch < dma_chan_count; ch++) {
681                 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
682                         free_ch = ch;
683                         if (dev_id == 0)
684                                 break;
685                 }
686         }
687         if (free_ch == -1) {
688                 spin_unlock_irqrestore(&dma_chan_lock, flags);
689                 return -EBUSY;
690         }
691         chan = dma_chan + free_ch;
692         chan->dev_id = dev_id;
693
694         if (p->clear_lch_regs)
695                 p->clear_lch_regs(free_ch);
696
697         if (cpu_class_is_omap2())
698                 omap_clear_dma(free_ch);
699
700         spin_unlock_irqrestore(&dma_chan_lock, flags);
701
702         chan->dev_name = dev_name;
703         chan->callback = callback;
704         chan->data = data;
705         chan->flags = 0;
706
707 #ifndef CONFIG_ARCH_OMAP1
708         if (cpu_class_is_omap2()) {
709                 chan->chain_id = -1;
710                 chan->next_linked_ch = -1;
711         }
712 #endif
713
714         chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
715
716         if (cpu_class_is_omap1())
717                 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
718         else if (cpu_class_is_omap2())
719                 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
720                         OMAP2_DMA_TRANS_ERR_IRQ;
721
722         if (cpu_is_omap16xx()) {
723                 /* If the sync device is set, configure it dynamically. */
724                 if (dev_id != 0) {
725                         set_gdma_dev(free_ch + 1, dev_id);
726                         dev_id = free_ch + 1;
727                 }
728                 /*
729                  * Disable the 1510 compatibility mode and set the sync device
730                  * id.
731                  */
732                 p->dma_write(dev_id | (1 << 10), CCR, free_ch);
733         } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) {
734                 p->dma_write(dev_id, CCR, free_ch);
735         }
736
737         if (cpu_class_is_omap2()) {
738                 omap2_enable_irq_lch(free_ch);
739                 omap_enable_channel_irq(free_ch);
740                 /* Clear the CSR register and IRQ status register */
741                 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, free_ch);
742                 p->dma_write(1 << free_ch, IRQSTATUS_L0, 0);
743         }
744
745         *dma_ch_out = free_ch;
746
747         return 0;
748 }
749 EXPORT_SYMBOL(omap_request_dma);
750
751 void omap_free_dma(int lch)
752 {
753         unsigned long flags;
754
755         if (dma_chan[lch].dev_id == -1) {
756                 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
757                        lch);
758                 return;
759         }
760
761         if (cpu_class_is_omap1()) {
762                 /* Disable all DMA interrupts for the channel. */
763                 p->dma_write(0, CICR, lch);
764                 /* Make sure the DMA transfer is stopped. */
765                 p->dma_write(0, CCR, lch);
766         }
767
768         if (cpu_class_is_omap2()) {
769                 omap2_disable_irq_lch(lch);
770
771                 /* Clear the CSR register and IRQ status register */
772                 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
773                 p->dma_write(1 << lch, IRQSTATUS_L0, lch);
774
775                 /* Disable all DMA interrupts for the channel. */
776                 p->dma_write(0, CICR, lch);
777
778                 /* Make sure the DMA transfer is stopped. */
779                 p->dma_write(0, CCR, lch);
780                 omap_clear_dma(lch);
781         }
782
783         spin_lock_irqsave(&dma_chan_lock, flags);
784         dma_chan[lch].dev_id = -1;
785         dma_chan[lch].next_lch = -1;
786         dma_chan[lch].callback = NULL;
787         spin_unlock_irqrestore(&dma_chan_lock, flags);
788 }
789 EXPORT_SYMBOL(omap_free_dma);
790
791 /**
792  * @brief omap_dma_set_global_params : Set global priority settings for dma
793  *
794  * @param arb_rate
795  * @param max_fifo_depth
796  * @param tparams - Number of threads to reserve : DMA_THREAD_RESERVE_NORM
797  *                                                 DMA_THREAD_RESERVE_ONET
798  *                                                 DMA_THREAD_RESERVE_TWOT
799  *                                                 DMA_THREAD_RESERVE_THREET
800  */
801 void
802 omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
803 {
804         u32 reg;
805
806         if (!cpu_class_is_omap2()) {
807                 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
808                 return;
809         }
810
811         if (max_fifo_depth == 0)
812                 max_fifo_depth = 1;
813         if (arb_rate == 0)
814                 arb_rate = 1;
815
816         reg = 0xff & max_fifo_depth;
817         reg |= (0x3 & tparams) << 12;
818         reg |= (arb_rate & 0xff) << 16;
819
820         p->dma_write(reg, GCR, 0);
821 }
822 EXPORT_SYMBOL(omap_dma_set_global_params);
823
824 /**
825  * @brief omap_dma_set_prio_lch : Set channel wise priority settings
826  *
827  * @param lch
828  * @param read_prio - Read priority
829  * @param write_prio - Write priority
830  * Both of the above can be set with one of the following values :
831  *      DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
832  */
833 int
834 omap_dma_set_prio_lch(int lch, unsigned char read_prio,
835                       unsigned char write_prio)
836 {
837         u32 l;
838
839         if (unlikely((lch < 0 || lch >= dma_lch_count))) {
840                 printk(KERN_ERR "Invalid channel id\n");
841                 return -EINVAL;
842         }
843         l = p->dma_read(CCR, lch);
844         l &= ~((1 << 6) | (1 << 26));
845         if (cpu_is_omap2430() || cpu_is_omap34xx() ||  cpu_is_omap44xx())
846                 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
847         else
848                 l |= ((read_prio & 0x1) << 6);
849
850         p->dma_write(l, CCR, lch);
851
852         return 0;
853 }
854 EXPORT_SYMBOL(omap_dma_set_prio_lch);
855
856 /*
857  * Clears any DMA state so the DMA engine is ready to restart with new buffers
858  * through omap_start_dma(). Any buffers in flight are discarded.
859  */
860 void omap_clear_dma(int lch)
861 {
862         unsigned long flags;
863
864         local_irq_save(flags);
865         p->clear_dma(lch);
866         local_irq_restore(flags);
867 }
868 EXPORT_SYMBOL(omap_clear_dma);
869
870 void omap_start_dma(int lch)
871 {
872         u32 l;
873
874         /*
875          * The CPC/CDAC register needs to be initialized to zero
876          * before starting dma transfer.
877          */
878         if (cpu_is_omap15xx())
879                 p->dma_write(0, CPC, lch);
880         else
881                 p->dma_write(0, CDAC, lch);
882
883         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
884                 int next_lch, cur_lch;
885                 char dma_chan_link_map[dma_lch_count];
886
887                 dma_chan_link_map[lch] = 1;
888                 /* Set the link register of the first channel */
889                 enable_lnk(lch);
890
891                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
892                 cur_lch = dma_chan[lch].next_lch;
893                 do {
894                         next_lch = dma_chan[cur_lch].next_lch;
895
896                         /* The loop case: we've been here already */
897                         if (dma_chan_link_map[cur_lch])
898                                 break;
899                         /* Mark the current channel */
900                         dma_chan_link_map[cur_lch] = 1;
901
902                         enable_lnk(cur_lch);
903                         omap_enable_channel_irq(cur_lch);
904
905                         cur_lch = next_lch;
906                 } while (next_lch != -1);
907         } else if (IS_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS))
908                 p->dma_write(lch, CLNK_CTRL, lch);
909
910         omap_enable_channel_irq(lch);
911
912         l = p->dma_read(CCR, lch);
913
914         if (IS_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING))
915                         l |= OMAP_DMA_CCR_BUFFERING_DISABLE;
916         l |= OMAP_DMA_CCR_EN;
917
918         p->dma_write(l, CCR, lch);
919
920         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
921 }
922 EXPORT_SYMBOL(omap_start_dma);
923
924 void omap_stop_dma(int lch)
925 {
926         u32 l;
927
928         /* Disable all interrupts on the channel */
929         if (cpu_class_is_omap1())
930                 p->dma_write(0, CICR, lch);
931
932         l = p->dma_read(CCR, lch);
933         if (IS_DMA_ERRATA(DMA_ERRATA_i541) &&
934                         (l & OMAP_DMA_CCR_SEL_SRC_DST_SYNC)) {
935                 int i = 0;
936                 u32 sys_cf;
937
938                 /* Configure No-Standby */
939                 l = p->dma_read(OCP_SYSCONFIG, lch);
940                 sys_cf = l;
941                 l &= ~DMA_SYSCONFIG_MIDLEMODE_MASK;
942                 l |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE);
943                 p->dma_write(l , OCP_SYSCONFIG, 0);
944
945                 l = p->dma_read(CCR, lch);
946                 l &= ~OMAP_DMA_CCR_EN;
947                 p->dma_write(l, CCR, lch);
948
949                 /* Wait for sDMA FIFO drain */
950                 l = p->dma_read(CCR, lch);
951                 while (i < 100 && (l & (OMAP_DMA_CCR_RD_ACTIVE |
952                                         OMAP_DMA_CCR_WR_ACTIVE))) {
953                         udelay(5);
954                         i++;
955                         l = p->dma_read(CCR, lch);
956                 }
957                 if (i >= 100)
958                         printk(KERN_ERR "DMA drain did not complete on "
959                                         "lch %d\n", lch);
960                 /* Restore OCP_SYSCONFIG */
961                 p->dma_write(sys_cf, OCP_SYSCONFIG, lch);
962         } else {
963                 l &= ~OMAP_DMA_CCR_EN;
964                 p->dma_write(l, CCR, lch);
965         }
966
967         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
968                 int next_lch, cur_lch = lch;
969                 char dma_chan_link_map[dma_lch_count];
970
971                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
972                 do {
973                         /* The loop case: we've been here already */
974                         if (dma_chan_link_map[cur_lch])
975                                 break;
976                         /* Mark the current channel */
977                         dma_chan_link_map[cur_lch] = 1;
978
979                         disable_lnk(cur_lch);
980
981                         next_lch = dma_chan[cur_lch].next_lch;
982                         cur_lch = next_lch;
983                 } while (next_lch != -1);
984         }
985
986         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
987 }
988 EXPORT_SYMBOL(omap_stop_dma);
989
990 /*
991  * Allows changing the DMA callback function or data. This may be needed if
992  * the driver shares a single DMA channel for multiple dma triggers.
993  */
994 int omap_set_dma_callback(int lch,
995                           void (*callback)(int lch, u16 ch_status, void *data),
996                           void *data)
997 {
998         unsigned long flags;
999
1000         if (lch < 0)
1001                 return -ENODEV;
1002
1003         spin_lock_irqsave(&dma_chan_lock, flags);
1004         if (dma_chan[lch].dev_id == -1) {
1005                 printk(KERN_ERR "DMA callback for not set for free channel\n");
1006                 spin_unlock_irqrestore(&dma_chan_lock, flags);
1007                 return -EINVAL;
1008         }
1009         dma_chan[lch].callback = callback;
1010         dma_chan[lch].data = data;
1011         spin_unlock_irqrestore(&dma_chan_lock, flags);
1012
1013         return 0;
1014 }
1015 EXPORT_SYMBOL(omap_set_dma_callback);
1016
1017 /*
1018  * Returns current physical source address for the given DMA channel.
1019  * If the channel is running the caller must disable interrupts prior calling
1020  * this function and process the returned value before re-enabling interrupt to
1021  * prevent races with the interrupt handler. Note that in continuous mode there
1022  * is a chance for CSSA_L register overflow between the two reads resulting
1023  * in incorrect return value.
1024  */
1025 dma_addr_t omap_get_dma_src_pos(int lch)
1026 {
1027         dma_addr_t offset = 0;
1028
1029         if (cpu_is_omap15xx())
1030                 offset = p->dma_read(CPC, lch);
1031         else
1032                 offset = p->dma_read(CSAC, lch);
1033
1034         if (IS_DMA_ERRATA(DMA_ERRATA_3_3) && offset == 0)
1035                 offset = p->dma_read(CSAC, lch);
1036
1037         if (!cpu_is_omap15xx()) {
1038                 /*
1039                  * CDAC == 0 indicates that the DMA transfer on the channel has
1040                  * not been started (no data has been transferred so far).
1041                  * Return the programmed source start address in this case.
1042                  */
1043                 if (likely(p->dma_read(CDAC, lch)))
1044                         offset = p->dma_read(CSAC, lch);
1045                 else
1046                         offset = p->dma_read(CSSA, lch);
1047         }
1048
1049         if (cpu_class_is_omap1())
1050                 offset |= (p->dma_read(CSSA, lch) & 0xFFFF0000);
1051
1052         return offset;
1053 }
1054 EXPORT_SYMBOL(omap_get_dma_src_pos);
1055
1056 /*
1057  * Returns current physical destination address for the given DMA channel.
1058  * If the channel is running the caller must disable interrupts prior calling
1059  * this function and process the returned value before re-enabling interrupt to
1060  * prevent races with the interrupt handler. Note that in continuous mode there
1061  * is a chance for CDSA_L register overflow between the two reads resulting
1062  * in incorrect return value.
1063  */
1064 dma_addr_t omap_get_dma_dst_pos(int lch)
1065 {
1066         dma_addr_t offset = 0;
1067
1068         if (cpu_is_omap15xx())
1069                 offset = p->dma_read(CPC, lch);
1070         else
1071                 offset = p->dma_read(CDAC, lch);
1072
1073         /*
1074          * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1075          * read before the DMA controller finished disabling the channel.
1076          */
1077         if (!cpu_is_omap15xx() && offset == 0)
1078                 offset = p->dma_read(CDAC, lch);
1079
1080         if (cpu_class_is_omap1())
1081                 offset |= (p->dma_read(CDSA, lch) & 0xFFFF0000);
1082
1083         return offset;
1084 }
1085 EXPORT_SYMBOL(omap_get_dma_dst_pos);
1086
1087 int omap_get_dma_active_status(int lch)
1088 {
1089         return (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN) != 0;
1090 }
1091 EXPORT_SYMBOL(omap_get_dma_active_status);
1092
1093 int omap_dma_running(void)
1094 {
1095         int lch;
1096
1097         if (cpu_class_is_omap1())
1098                 if (omap_lcd_dma_running())
1099                         return 1;
1100
1101         for (lch = 0; lch < dma_chan_count; lch++)
1102                 if (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN)
1103                         return 1;
1104
1105         return 0;
1106 }
1107
1108 /*
1109  * lch_queue DMA will start right after lch_head one is finished.
1110  * For this DMA link to start, you still need to start (see omap_start_dma)
1111  * the first one. That will fire up the entire queue.
1112  */
1113 void omap_dma_link_lch(int lch_head, int lch_queue)
1114 {
1115         if (omap_dma_in_1510_mode()) {
1116                 if (lch_head == lch_queue) {
1117                         p->dma_write(p->dma_read(CCR, lch_head) | (3 << 8),
1118                                                                 CCR, lch_head);
1119                         return;
1120                 }
1121                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1122                 BUG();
1123                 return;
1124         }
1125
1126         if ((dma_chan[lch_head].dev_id == -1) ||
1127             (dma_chan[lch_queue].dev_id == -1)) {
1128                 printk(KERN_ERR "omap_dma: trying to link "
1129                        "non requested channels\n");
1130                 dump_stack();
1131         }
1132
1133         dma_chan[lch_head].next_lch = lch_queue;
1134 }
1135 EXPORT_SYMBOL(omap_dma_link_lch);
1136
1137 /*
1138  * Once the DMA queue is stopped, we can destroy it.
1139  */
1140 void omap_dma_unlink_lch(int lch_head, int lch_queue)
1141 {
1142         if (omap_dma_in_1510_mode()) {
1143                 if (lch_head == lch_queue) {
1144                         p->dma_write(p->dma_read(CCR, lch_head) & ~(3 << 8),
1145                                                                 CCR, lch_head);
1146                         return;
1147                 }
1148                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1149                 BUG();
1150                 return;
1151         }
1152
1153         if (dma_chan[lch_head].next_lch != lch_queue ||
1154             dma_chan[lch_head].next_lch == -1) {
1155                 printk(KERN_ERR "omap_dma: trying to unlink "
1156                        "non linked channels\n");
1157                 dump_stack();
1158         }
1159
1160         if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
1161             (dma_chan[lch_queue].flags & OMAP_DMA_ACTIVE)) {
1162                 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
1163                        "before unlinking\n");
1164                 dump_stack();
1165         }
1166
1167         dma_chan[lch_head].next_lch = -1;
1168 }
1169 EXPORT_SYMBOL(omap_dma_unlink_lch);
1170
1171 #ifndef CONFIG_ARCH_OMAP1
1172 /* Create chain of DMA channesls */
1173 static void create_dma_lch_chain(int lch_head, int lch_queue)
1174 {
1175         u32 l;
1176
1177         /* Check if this is the first link in chain */
1178         if (dma_chan[lch_head].next_linked_ch == -1) {
1179                 dma_chan[lch_head].next_linked_ch = lch_queue;
1180                 dma_chan[lch_head].prev_linked_ch = lch_queue;
1181                 dma_chan[lch_queue].next_linked_ch = lch_head;
1182                 dma_chan[lch_queue].prev_linked_ch = lch_head;
1183         }
1184
1185         /* a link exists, link the new channel in circular chain */
1186         else {
1187                 dma_chan[lch_queue].next_linked_ch =
1188                                         dma_chan[lch_head].next_linked_ch;
1189                 dma_chan[lch_queue].prev_linked_ch = lch_head;
1190                 dma_chan[lch_head].next_linked_ch = lch_queue;
1191                 dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
1192                                         lch_queue;
1193         }
1194
1195         l = p->dma_read(CLNK_CTRL, lch_head);
1196         l &= ~(0x1f);
1197         l |= lch_queue;
1198         p->dma_write(l, CLNK_CTRL, lch_head);
1199
1200         l = p->dma_read(CLNK_CTRL, lch_queue);
1201         l &= ~(0x1f);
1202         l |= (dma_chan[lch_queue].next_linked_ch);
1203         p->dma_write(l, CLNK_CTRL, lch_queue);
1204 }
1205
1206 /**
1207  * @brief omap_request_dma_chain : Request a chain of DMA channels
1208  *
1209  * @param dev_id - Device id using the dma channel
1210  * @param dev_name - Device name
1211  * @param callback - Call back function
1212  * @chain_id -
1213  * @no_of_chans - Number of channels requested
1214  * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1215  *                                            OMAP_DMA_DYNAMIC_CHAIN
1216  * @params - Channel parameters
1217  *
1218  * @return - Success : 0
1219  *           Failure: -EINVAL/-ENOMEM
1220  */
1221 int omap_request_dma_chain(int dev_id, const char *dev_name,
1222                            void (*callback) (int lch, u16 ch_status,
1223                                              void *data),
1224                            int *chain_id, int no_of_chans, int chain_mode,
1225                            struct omap_dma_channel_params params)
1226 {
1227         int *channels;
1228         int i, err;
1229
1230         /* Is the chain mode valid ? */
1231         if (chain_mode != OMAP_DMA_STATIC_CHAIN
1232                         && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
1233                 printk(KERN_ERR "Invalid chain mode requested\n");
1234                 return -EINVAL;
1235         }
1236
1237         if (unlikely((no_of_chans < 1
1238                         || no_of_chans > dma_lch_count))) {
1239                 printk(KERN_ERR "Invalid Number of channels requested\n");
1240                 return -EINVAL;
1241         }
1242
1243         /*
1244          * Allocate a queue to maintain the status of the channels
1245          * in the chain
1246          */
1247         channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
1248         if (channels == NULL) {
1249                 printk(KERN_ERR "omap_dma: No memory for channel queue\n");
1250                 return -ENOMEM;
1251         }
1252
1253         /* request and reserve DMA channels for the chain */
1254         for (i = 0; i < no_of_chans; i++) {
1255                 err = omap_request_dma(dev_id, dev_name,
1256                                         callback, NULL, &channels[i]);
1257                 if (err < 0) {
1258                         int j;
1259                         for (j = 0; j < i; j++)
1260                                 omap_free_dma(channels[j]);
1261                         kfree(channels);
1262                         printk(KERN_ERR "omap_dma: Request failed %d\n", err);
1263                         return err;
1264                 }
1265                 dma_chan[channels[i]].prev_linked_ch = -1;
1266                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1267
1268                 /*
1269                  * Allowing client drivers to set common parameters now,
1270                  * so that later only relevant (src_start, dest_start
1271                  * and element count) can be set
1272                  */
1273                 omap_set_dma_params(channels[i], &params);
1274         }
1275
1276         *chain_id = channels[0];
1277         dma_linked_lch[*chain_id].linked_dmach_q = channels;
1278         dma_linked_lch[*chain_id].chain_mode = chain_mode;
1279         dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1280         dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;
1281
1282         for (i = 0; i < no_of_chans; i++)
1283                 dma_chan[channels[i]].chain_id = *chain_id;
1284
1285         /* Reset the Queue pointers */
1286         OMAP_DMA_CHAIN_QINIT(*chain_id);
1287
1288         /* Set up the chain */
1289         if (no_of_chans == 1)
1290                 create_dma_lch_chain(channels[0], channels[0]);
1291         else {
1292                 for (i = 0; i < (no_of_chans - 1); i++)
1293                         create_dma_lch_chain(channels[i], channels[i + 1]);
1294         }
1295
1296         return 0;
1297 }
1298 EXPORT_SYMBOL(omap_request_dma_chain);
1299
1300 /**
1301  * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1302  * params after setting it. Dont do this while dma is running!!
1303  *
1304  * @param chain_id - Chained logical channel id.
1305  * @param params
1306  *
1307  * @return - Success : 0
1308  *           Failure : -EINVAL
1309  */
1310 int omap_modify_dma_chain_params(int chain_id,
1311                                 struct omap_dma_channel_params params)
1312 {
1313         int *channels;
1314         u32 i;
1315
1316         /* Check for input params */
1317         if (unlikely((chain_id < 0
1318                         || chain_id >= dma_lch_count))) {
1319                 printk(KERN_ERR "Invalid chain id\n");
1320                 return -EINVAL;
1321         }
1322
1323         /* Check if the chain exists */
1324         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1325                 printk(KERN_ERR "Chain doesn't exists\n");
1326                 return -EINVAL;
1327         }
1328         channels = dma_linked_lch[chain_id].linked_dmach_q;
1329
1330         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1331                 /*
1332                  * Allowing client drivers to set common parameters now,
1333                  * so that later only relevant (src_start, dest_start
1334                  * and element count) can be set
1335                  */
1336                 omap_set_dma_params(channels[i], &params);
1337         }
1338
1339         return 0;
1340 }
1341 EXPORT_SYMBOL(omap_modify_dma_chain_params);
1342
1343 /**
1344  * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1345  *
1346  * @param chain_id
1347  *
1348  * @return - Success : 0
1349  *           Failure : -EINVAL
1350  */
1351 int omap_free_dma_chain(int chain_id)
1352 {
1353         int *channels;
1354         u32 i;
1355
1356         /* Check for input params */
1357         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1358                 printk(KERN_ERR "Invalid chain id\n");
1359                 return -EINVAL;
1360         }
1361
1362         /* Check if the chain exists */
1363         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1364                 printk(KERN_ERR "Chain doesn't exists\n");
1365                 return -EINVAL;
1366         }
1367
1368         channels = dma_linked_lch[chain_id].linked_dmach_q;
1369         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1370                 dma_chan[channels[i]].next_linked_ch = -1;
1371                 dma_chan[channels[i]].prev_linked_ch = -1;
1372                 dma_chan[channels[i]].chain_id = -1;
1373                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1374                 omap_free_dma(channels[i]);
1375         }
1376
1377         kfree(channels);
1378
1379         dma_linked_lch[chain_id].linked_dmach_q = NULL;
1380         dma_linked_lch[chain_id].chain_mode = -1;
1381         dma_linked_lch[chain_id].chain_state = -1;
1382
1383         return (0);
1384 }
1385 EXPORT_SYMBOL(omap_free_dma_chain);
1386
1387 /**
1388  * @brief omap_dma_chain_status - Check if the chain is in
1389  * active / inactive state.
1390  * @param chain_id
1391  *
1392  * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1393  *           Failure : -EINVAL
1394  */
1395 int omap_dma_chain_status(int chain_id)
1396 {
1397         /* Check for input params */
1398         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1399                 printk(KERN_ERR "Invalid chain id\n");
1400                 return -EINVAL;
1401         }
1402
1403         /* Check if the chain exists */
1404         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1405                 printk(KERN_ERR "Chain doesn't exists\n");
1406                 return -EINVAL;
1407         }
1408         pr_debug("CHAINID=%d, qcnt=%d\n", chain_id,
1409                         dma_linked_lch[chain_id].q_count);
1410
1411         if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
1412                 return OMAP_DMA_CHAIN_INACTIVE;
1413
1414         return OMAP_DMA_CHAIN_ACTIVE;
1415 }
1416 EXPORT_SYMBOL(omap_dma_chain_status);
1417
1418 /**
1419  * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1420  * set the params and start the transfer.
1421  *
1422  * @param chain_id
1423  * @param src_start - buffer start address
1424  * @param dest_start - Dest address
1425  * @param elem_count
1426  * @param frame_count
1427  * @param callbk_data - channel callback parameter data.
1428  *
1429  * @return  - Success : 0
1430  *            Failure: -EINVAL/-EBUSY
1431  */
1432 int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1433                         int elem_count, int frame_count, void *callbk_data)
1434 {
1435         int *channels;
1436         u32 l, lch;
1437         int start_dma = 0;
1438
1439         /*
1440          * if buffer size is less than 1 then there is
1441          * no use of starting the chain
1442          */
1443         if (elem_count < 1) {
1444                 printk(KERN_ERR "Invalid buffer size\n");
1445                 return -EINVAL;
1446         }
1447
1448         /* Check for input params */
1449         if (unlikely((chain_id < 0
1450                         || chain_id >= dma_lch_count))) {
1451                 printk(KERN_ERR "Invalid chain id\n");
1452                 return -EINVAL;
1453         }
1454
1455         /* Check if the chain exists */
1456         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1457                 printk(KERN_ERR "Chain doesn't exist\n");
1458                 return -EINVAL;
1459         }
1460
1461         /* Check if all the channels in chain are in use */
1462         if (OMAP_DMA_CHAIN_QFULL(chain_id))
1463                 return -EBUSY;
1464
1465         /* Frame count may be negative in case of indexed transfers */
1466         channels = dma_linked_lch[chain_id].linked_dmach_q;
1467
1468         /* Get a free channel */
1469         lch = channels[dma_linked_lch[chain_id].q_tail];
1470
1471         /* Store the callback data */
1472         dma_chan[lch].data = callbk_data;
1473
1474         /* Increment the q_tail */
1475         OMAP_DMA_CHAIN_INCQTAIL(chain_id);
1476
1477         /* Set the params to the free channel */
1478         if (src_start != 0)
1479                 p->dma_write(src_start, CSSA, lch);
1480         if (dest_start != 0)
1481                 p->dma_write(dest_start, CDSA, lch);
1482
1483         /* Write the buffer size */
1484         p->dma_write(elem_count, CEN, lch);
1485         p->dma_write(frame_count, CFN, lch);
1486
1487         /*
1488          * If the chain is dynamically linked,
1489          * then we may have to start the chain if its not active
1490          */
1491         if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
1492
1493                 /*
1494                  * In Dynamic chain, if the chain is not started,
1495                  * queue the channel
1496                  */
1497                 if (dma_linked_lch[chain_id].chain_state ==
1498                                                 DMA_CHAIN_NOTSTARTED) {
1499                         /* Enable the link in previous channel */
1500                         if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1501                                                                 DMA_CH_QUEUED)
1502                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1503                         dma_chan[lch].state = DMA_CH_QUEUED;
1504                 }
1505
1506                 /*
1507                  * Chain is already started, make sure its active,
1508                  * if not then start the chain
1509                  */
1510                 else {
1511                         start_dma = 1;
1512
1513                         if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1514                                                         DMA_CH_STARTED) {
1515                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1516                                 dma_chan[lch].state = DMA_CH_QUEUED;
1517                                 start_dma = 0;
1518                                 if (0 == ((1 << 7) & p->dma_read(
1519                                         CCR, dma_chan[lch].prev_linked_ch))) {
1520                                         disable_lnk(dma_chan[lch].
1521                                                     prev_linked_ch);
1522                                         pr_debug("\n prev ch is stopped\n");
1523                                         start_dma = 1;
1524                                 }
1525                         }
1526
1527                         else if (dma_chan[dma_chan[lch].prev_linked_ch].state
1528                                                         == DMA_CH_QUEUED) {
1529                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1530                                 dma_chan[lch].state = DMA_CH_QUEUED;
1531                                 start_dma = 0;
1532                         }
1533                         omap_enable_channel_irq(lch);
1534
1535                         l = p->dma_read(CCR, lch);
1536
1537                         if ((0 == (l & (1 << 24))))
1538                                 l &= ~(1 << 25);
1539                         else
1540                                 l |= (1 << 25);
1541                         if (start_dma == 1) {
1542                                 if (0 == (l & (1 << 7))) {
1543                                         l |= (1 << 7);
1544                                         dma_chan[lch].state = DMA_CH_STARTED;
1545                                         pr_debug("starting %d\n", lch);
1546                                         p->dma_write(l, CCR, lch);
1547                                 } else
1548                                         start_dma = 0;
1549                         } else {
1550                                 if (0 == (l & (1 << 7)))
1551                                         p->dma_write(l, CCR, lch);
1552                         }
1553                         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1554                 }
1555         }
1556
1557         return 0;
1558 }
1559 EXPORT_SYMBOL(omap_dma_chain_a_transfer);
1560
1561 /**
1562  * @brief omap_start_dma_chain_transfers - Start the chain
1563  *
1564  * @param chain_id
1565  *
1566  * @return - Success : 0
1567  *           Failure : -EINVAL/-EBUSY
1568  */
1569 int omap_start_dma_chain_transfers(int chain_id)
1570 {
1571         int *channels;
1572         u32 l, i;
1573
1574         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1575                 printk(KERN_ERR "Invalid chain id\n");
1576                 return -EINVAL;
1577         }
1578
1579         channels = dma_linked_lch[chain_id].linked_dmach_q;
1580
1581         if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
1582                 printk(KERN_ERR "Chain is already started\n");
1583                 return -EBUSY;
1584         }
1585
1586         if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
1587                 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
1588                                                                         i++) {
1589                         enable_lnk(channels[i]);
1590                         omap_enable_channel_irq(channels[i]);
1591                 }
1592         } else {
1593                 omap_enable_channel_irq(channels[0]);
1594         }
1595
1596         l = p->dma_read(CCR, channels[0]);
1597         l |= (1 << 7);
1598         dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
1599         dma_chan[channels[0]].state = DMA_CH_STARTED;
1600
1601         if ((0 == (l & (1 << 24))))
1602                 l &= ~(1 << 25);
1603         else
1604                 l |= (1 << 25);
1605         p->dma_write(l, CCR, channels[0]);
1606
1607         dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
1608
1609         return 0;
1610 }
1611 EXPORT_SYMBOL(omap_start_dma_chain_transfers);
1612
1613 /**
1614  * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1615  *
1616  * @param chain_id
1617  *
1618  * @return - Success : 0
1619  *           Failure : EINVAL
1620  */
1621 int omap_stop_dma_chain_transfers(int chain_id)
1622 {
1623         int *channels;
1624         u32 l, i;
1625         u32 sys_cf = 0;
1626
1627         /* Check for input params */
1628         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1629                 printk(KERN_ERR "Invalid chain id\n");
1630                 return -EINVAL;
1631         }
1632
1633         /* Check if the chain exists */
1634         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1635                 printk(KERN_ERR "Chain doesn't exists\n");
1636                 return -EINVAL;
1637         }
1638         channels = dma_linked_lch[chain_id].linked_dmach_q;
1639
1640         if (IS_DMA_ERRATA(DMA_ERRATA_i88)) {
1641                 sys_cf = p->dma_read(OCP_SYSCONFIG, 0);
1642                 l = sys_cf;
1643                 /* Middle mode reg set no Standby */
1644                 l &= ~((1 << 12)|(1 << 13));
1645                 p->dma_write(l, OCP_SYSCONFIG, 0);
1646         }
1647
1648         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1649
1650                 /* Stop the Channel transmission */
1651                 l = p->dma_read(CCR, channels[i]);
1652                 l &= ~(1 << 7);
1653                 p->dma_write(l, CCR, channels[i]);
1654
1655                 /* Disable the link in all the channels */
1656                 disable_lnk(channels[i]);
1657                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1658
1659         }
1660         dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1661
1662         /* Reset the Queue pointers */
1663         OMAP_DMA_CHAIN_QINIT(chain_id);
1664
1665         if (IS_DMA_ERRATA(DMA_ERRATA_i88))
1666                 p->dma_write(sys_cf, OCP_SYSCONFIG, 0);
1667
1668         return 0;
1669 }
1670 EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
1671
1672 /* Get the index of the ongoing DMA in chain */
1673 /**
1674  * @brief omap_get_dma_chain_index - Get the element and frame index
1675  * of the ongoing DMA in chain
1676  *
1677  * @param chain_id
1678  * @param ei - Element index
1679  * @param fi - Frame index
1680  *
1681  * @return - Success : 0
1682  *           Failure : -EINVAL
1683  */
1684 int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1685 {
1686         int lch;
1687         int *channels;
1688
1689         /* Check for input params */
1690         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1691                 printk(KERN_ERR "Invalid chain id\n");
1692                 return -EINVAL;
1693         }
1694
1695         /* Check if the chain exists */
1696         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1697                 printk(KERN_ERR "Chain doesn't exists\n");
1698                 return -EINVAL;
1699         }
1700         if ((!ei) || (!fi))
1701                 return -EINVAL;
1702
1703         channels = dma_linked_lch[chain_id].linked_dmach_q;
1704
1705         /* Get the current channel */
1706         lch = channels[dma_linked_lch[chain_id].q_head];
1707
1708         *ei = p->dma_read(CCEN, lch);
1709         *fi = p->dma_read(CCFN, lch);
1710
1711         return 0;
1712 }
1713 EXPORT_SYMBOL(omap_get_dma_chain_index);
1714
1715 /**
1716  * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1717  * ongoing DMA in chain
1718  *
1719  * @param chain_id
1720  *
1721  * @return - Success : Destination position
1722  *           Failure : -EINVAL
1723  */
1724 int omap_get_dma_chain_dst_pos(int chain_id)
1725 {
1726         int lch;
1727         int *channels;
1728
1729         /* Check for input params */
1730         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1731                 printk(KERN_ERR "Invalid chain id\n");
1732                 return -EINVAL;
1733         }
1734
1735         /* Check if the chain exists */
1736         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1737                 printk(KERN_ERR "Chain doesn't exists\n");
1738                 return -EINVAL;
1739         }
1740
1741         channels = dma_linked_lch[chain_id].linked_dmach_q;
1742
1743         /* Get the current channel */
1744         lch = channels[dma_linked_lch[chain_id].q_head];
1745
1746         return p->dma_read(CDAC, lch);
1747 }
1748 EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
1749
1750 /**
1751  * @brief omap_get_dma_chain_src_pos - Get the source position
1752  * of the ongoing DMA in chain
1753  * @param chain_id
1754  *
1755  * @return - Success : Destination position
1756  *           Failure : -EINVAL
1757  */
1758 int omap_get_dma_chain_src_pos(int chain_id)
1759 {
1760         int lch;
1761         int *channels;
1762
1763         /* Check for input params */
1764         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1765                 printk(KERN_ERR "Invalid chain id\n");
1766                 return -EINVAL;
1767         }
1768
1769         /* Check if the chain exists */
1770         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1771                 printk(KERN_ERR "Chain doesn't exists\n");
1772                 return -EINVAL;
1773         }
1774
1775         channels = dma_linked_lch[chain_id].linked_dmach_q;
1776
1777         /* Get the current channel */
1778         lch = channels[dma_linked_lch[chain_id].q_head];
1779
1780         return p->dma_read(CSAC, lch);
1781 }
1782 EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
1783 #endif  /* ifndef CONFIG_ARCH_OMAP1 */
1784
1785 /*----------------------------------------------------------------------------*/
1786
1787 #ifdef CONFIG_ARCH_OMAP1
1788
1789 static int omap1_dma_handle_ch(int ch)
1790 {
1791         u32 csr;
1792
1793         if (enable_1510_mode && ch >= 6) {
1794                 csr = dma_chan[ch].saved_csr;
1795                 dma_chan[ch].saved_csr = 0;
1796         } else
1797                 csr = p->dma_read(CSR, ch);
1798         if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1799                 dma_chan[ch + 6].saved_csr = csr >> 7;
1800                 csr &= 0x7f;
1801         }
1802         if ((csr & 0x3f) == 0)
1803                 return 0;
1804         if (unlikely(dma_chan[ch].dev_id == -1)) {
1805                 printk(KERN_WARNING "Spurious interrupt from DMA channel "
1806                        "%d (CSR %04x)\n", ch, csr);
1807                 return 0;
1808         }
1809         if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
1810                 printk(KERN_WARNING "DMA timeout with device %d\n",
1811                        dma_chan[ch].dev_id);
1812         if (unlikely(csr & OMAP_DMA_DROP_IRQ))
1813                 printk(KERN_WARNING "DMA synchronization event drop occurred "
1814                        "with device %d\n", dma_chan[ch].dev_id);
1815         if (likely(csr & OMAP_DMA_BLOCK_IRQ))
1816                 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1817         if (likely(dma_chan[ch].callback != NULL))
1818                 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
1819
1820         return 1;
1821 }
1822
1823 static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1824 {
1825         int ch = ((int) dev_id) - 1;
1826         int handled = 0;
1827
1828         for (;;) {
1829                 int handled_now = 0;
1830
1831                 handled_now += omap1_dma_handle_ch(ch);
1832                 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
1833                         handled_now += omap1_dma_handle_ch(ch + 6);
1834                 if (!handled_now)
1835                         break;
1836                 handled += handled_now;
1837         }
1838
1839         return handled ? IRQ_HANDLED : IRQ_NONE;
1840 }
1841
1842 #else
1843 #define omap1_dma_irq_handler   NULL
1844 #endif
1845
1846 #ifdef CONFIG_ARCH_OMAP2PLUS
1847
1848 static int omap2_dma_handle_ch(int ch)
1849 {
1850         u32 status = p->dma_read(CSR, ch);
1851
1852         if (!status) {
1853                 if (printk_ratelimit())
1854                         printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
1855                                 ch);
1856                 p->dma_write(1 << ch, IRQSTATUS_L0, ch);
1857                 return 0;
1858         }
1859         if (unlikely(dma_chan[ch].dev_id == -1)) {
1860                 if (printk_ratelimit())
1861                         printk(KERN_WARNING "IRQ %04x for non-allocated DMA"
1862                                         "channel %d\n", status, ch);
1863                 return 0;
1864         }
1865         if (unlikely(status & OMAP_DMA_DROP_IRQ))
1866                 printk(KERN_INFO
1867                        "DMA synchronization event drop occurred with device "
1868                        "%d\n", dma_chan[ch].dev_id);
1869         if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
1870                 printk(KERN_INFO "DMA transaction error with device %d\n",
1871                        dma_chan[ch].dev_id);
1872                 if (IS_DMA_ERRATA(DMA_ERRATA_i378)) {
1873                         u32 ccr;
1874
1875                         ccr = p->dma_read(CCR, ch);
1876                         ccr &= ~OMAP_DMA_CCR_EN;
1877                         p->dma_write(ccr, CCR, ch);
1878                         dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1879                 }
1880         }
1881         if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
1882                 printk(KERN_INFO "DMA secure error with device %d\n",
1883                        dma_chan[ch].dev_id);
1884         if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
1885                 printk(KERN_INFO "DMA misaligned error with device %d\n",
1886                        dma_chan[ch].dev_id);
1887
1888         p->dma_write(status, CSR, ch);
1889         p->dma_write(1 << ch, IRQSTATUS_L0, ch);
1890         /* read back the register to flush the write */
1891         p->dma_read(IRQSTATUS_L0, ch);
1892
1893         /* If the ch is not chained then chain_id will be -1 */
1894         if (dma_chan[ch].chain_id != -1) {
1895                 int chain_id = dma_chan[ch].chain_id;
1896                 dma_chan[ch].state = DMA_CH_NOTSTARTED;
1897                 if (p->dma_read(CLNK_CTRL, ch) & (1 << 15))
1898                         dma_chan[dma_chan[ch].next_linked_ch].state =
1899                                                         DMA_CH_STARTED;
1900                 if (dma_linked_lch[chain_id].chain_mode ==
1901                                                 OMAP_DMA_DYNAMIC_CHAIN)
1902                         disable_lnk(ch);
1903
1904                 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1905                         OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1906
1907                 status = p->dma_read(CSR, ch);
1908                 p->dma_write(status, CSR, ch);
1909         }
1910
1911         if (likely(dma_chan[ch].callback != NULL))
1912                 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1913
1914         return 0;
1915 }
1916
1917 /* STATUS register count is from 1-32 while our is 0-31 */
1918 static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1919 {
1920         u32 val, enable_reg;
1921         int i;
1922
1923         val = p->dma_read(IRQSTATUS_L0, 0);
1924         if (val == 0) {
1925                 if (printk_ratelimit())
1926                         printk(KERN_WARNING "Spurious DMA IRQ\n");
1927                 return IRQ_HANDLED;
1928         }
1929         enable_reg = p->dma_read(IRQENABLE_L0, 0);
1930         val &= enable_reg; /* Dispatch only relevant interrupts */
1931         for (i = 0; i < dma_lch_count && val != 0; i++) {
1932                 if (val & 1)
1933                         omap2_dma_handle_ch(i);
1934                 val >>= 1;
1935         }
1936
1937         return IRQ_HANDLED;
1938 }
1939
1940 static struct irqaction omap24xx_dma_irq = {
1941         .name = "DMA",
1942         .handler = omap2_dma_irq_handler,
1943         .flags = IRQF_DISABLED
1944 };
1945
1946 #else
1947 static struct irqaction omap24xx_dma_irq;
1948 #endif
1949
1950 /*----------------------------------------------------------------------------*/
1951
1952 void omap_dma_global_context_save(void)
1953 {
1954         omap_dma_global_context.dma_irqenable_l0 =
1955                 p->dma_read(IRQENABLE_L0, 0);
1956         omap_dma_global_context.dma_ocp_sysconfig =
1957                 p->dma_read(OCP_SYSCONFIG, 0);
1958         omap_dma_global_context.dma_gcr = p->dma_read(GCR, 0);
1959 }
1960
1961 void omap_dma_global_context_restore(void)
1962 {
1963         int ch;
1964
1965         p->dma_write(omap_dma_global_context.dma_gcr, GCR, 0);
1966         p->dma_write(omap_dma_global_context.dma_ocp_sysconfig,
1967                 OCP_SYSCONFIG, 0);
1968         p->dma_write(omap_dma_global_context.dma_irqenable_l0,
1969                 IRQENABLE_L0, 0);
1970
1971         if (IS_DMA_ERRATA(DMA_ROMCODE_BUG))
1972                 p->dma_write(0x3 , IRQSTATUS_L0, 0);
1973
1974         for (ch = 0; ch < dma_chan_count; ch++)
1975                 if (dma_chan[ch].dev_id != -1)
1976                         omap_clear_dma(ch);
1977 }
1978
1979 static int __devinit omap_system_dma_probe(struct platform_device *pdev)
1980 {
1981         int ch, ret = 0;
1982         int dma_irq;
1983         char irq_name[4];
1984         int irq_rel;
1985
1986         p = pdev->dev.platform_data;
1987         if (!p) {
1988                 dev_err(&pdev->dev, "%s: System DMA initialized without"
1989                         "platform data\n", __func__);
1990                 return -EINVAL;
1991         }
1992
1993         d                       = p->dma_attr;
1994         errata                  = p->errata;
1995
1996         if ((d->dev_caps & RESERVE_CHANNEL) && omap_dma_reserve_channels
1997                         && (omap_dma_reserve_channels <= dma_lch_count))
1998                 d->lch_count    = omap_dma_reserve_channels;
1999
2000         dma_lch_count           = d->lch_count;
2001         dma_chan_count          = dma_lch_count;
2002         dma_chan                = d->chan;
2003         enable_1510_mode        = d->dev_caps & ENABLE_1510_MODE;
2004
2005         if (cpu_class_is_omap2()) {
2006                 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
2007                                                 dma_lch_count, GFP_KERNEL);
2008                 if (!dma_linked_lch) {
2009                         ret = -ENOMEM;
2010                         goto exit_dma_lch_fail;
2011                 }
2012         }
2013
2014         spin_lock_init(&dma_chan_lock);
2015         for (ch = 0; ch < dma_chan_count; ch++) {
2016                 omap_clear_dma(ch);
2017                 if (cpu_class_is_omap2())
2018                         omap2_disable_irq_lch(ch);
2019
2020                 dma_chan[ch].dev_id = -1;
2021                 dma_chan[ch].next_lch = -1;
2022
2023                 if (ch >= 6 && enable_1510_mode)
2024                         continue;
2025
2026                 if (cpu_class_is_omap1()) {
2027                         /*
2028                          * request_irq() doesn't like dev_id (ie. ch) being
2029                          * zero, so we have to kludge around this.
2030                          */
2031                         sprintf(&irq_name[0], "%d", ch);
2032                         dma_irq = platform_get_irq_byname(pdev, irq_name);
2033
2034                         if (dma_irq < 0) {
2035                                 ret = dma_irq;
2036                                 goto exit_dma_irq_fail;
2037                         }
2038
2039                         /* INT_DMA_LCD is handled in lcd_dma.c */
2040                         if (dma_irq == INT_DMA_LCD)
2041                                 continue;
2042
2043                         ret = request_irq(dma_irq,
2044                                         omap1_dma_irq_handler, 0, "DMA",
2045                                         (void *) (ch + 1));
2046                         if (ret != 0)
2047                                 goto exit_dma_irq_fail;
2048                 }
2049         }
2050
2051         if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx())
2052                 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
2053                                 DMA_DEFAULT_FIFO_DEPTH, 0);
2054
2055         if (cpu_class_is_omap2()) {
2056                 strcpy(irq_name, "0");
2057                 dma_irq = platform_get_irq_byname(pdev, irq_name);
2058                 if (dma_irq < 0) {
2059                         dev_err(&pdev->dev, "failed: request IRQ %d", dma_irq);
2060                         goto exit_dma_lch_fail;
2061                 }
2062                 ret = setup_irq(dma_irq, &omap24xx_dma_irq);
2063                 if (ret) {
2064                         dev_err(&pdev->dev, "set_up failed for IRQ %d"
2065                                 "for DMA (error %d)\n", dma_irq, ret);
2066                         goto exit_dma_lch_fail;
2067                 }
2068         }
2069
2070         /* reserve dma channels 0 and 1 in high security devices */
2071         if (cpu_is_omap34xx() &&
2072                 (omap_type() != OMAP2_DEVICE_TYPE_GP)) {
2073                 printk(KERN_INFO "Reserving DMA channels 0 and 1 for "
2074                                 "HS ROM code\n");
2075                 dma_chan[0].dev_id = 0;
2076                 dma_chan[1].dev_id = 1;
2077         }
2078         p->show_dma_caps();
2079         return 0;
2080
2081 exit_dma_irq_fail:
2082         dev_err(&pdev->dev, "unable to request IRQ %d"
2083                         "for DMA (error %d)\n", dma_irq, ret);
2084         for (irq_rel = 0; irq_rel < ch; irq_rel++) {
2085                 dma_irq = platform_get_irq(pdev, irq_rel);
2086                 free_irq(dma_irq, (void *)(irq_rel + 1));
2087         }
2088
2089 exit_dma_lch_fail:
2090         kfree(p);
2091         kfree(d);
2092         kfree(dma_chan);
2093         return ret;
2094 }
2095
2096 static int __devexit omap_system_dma_remove(struct platform_device *pdev)
2097 {
2098         int dma_irq;
2099
2100         if (cpu_class_is_omap2()) {
2101                 char irq_name[4];
2102                 strcpy(irq_name, "0");
2103                 dma_irq = platform_get_irq_byname(pdev, irq_name);
2104                 remove_irq(dma_irq, &omap24xx_dma_irq);
2105         } else {
2106                 int irq_rel = 0;
2107                 for ( ; irq_rel < dma_chan_count; irq_rel++) {
2108                         dma_irq = platform_get_irq(pdev, irq_rel);
2109                         free_irq(dma_irq, (void *)(irq_rel + 1));
2110                 }
2111         }
2112         kfree(p);
2113         kfree(d);
2114         kfree(dma_chan);
2115         return 0;
2116 }
2117
2118 static struct platform_driver omap_system_dma_driver = {
2119         .probe          = omap_system_dma_probe,
2120         .remove         = omap_system_dma_remove,
2121         .driver         = {
2122                 .name   = "omap_dma_system"
2123         },
2124 };
2125
2126 static int __init omap_system_dma_init(void)
2127 {
2128         return platform_driver_register(&omap_system_dma_driver);
2129 }
2130 arch_initcall(omap_system_dma_init);
2131
2132 static void __exit omap_system_dma_exit(void)
2133 {
2134         platform_driver_unregister(&omap_system_dma_driver);
2135 }
2136
2137 MODULE_DESCRIPTION("OMAP SYSTEM DMA DRIVER");
2138 MODULE_LICENSE("GPL");
2139 MODULE_ALIAS("platform:" DRIVER_NAME);
2140 MODULE_AUTHOR("Texas Instruments Inc");
2141
2142 /*
2143  * Reserve the omap SDMA channels using cmdline bootarg
2144  * "omap_dma_reserve_ch=". The valid range is 1 to 32
2145  */
2146 static int __init omap_dma_cmdline_reserve_ch(char *str)
2147 {
2148         if (get_option(&str, &omap_dma_reserve_channels) != 1)
2149                 omap_dma_reserve_channels = 0;
2150         return 1;
2151 }
2152
2153 __setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch);
2154
2155