arch/arm/plat-omap/dma.c

   1 /*
   2  * linux/arch/arm/plat-omap/dma.c
   3  *
   4  * Copyright (C) 2003 - 2008 Nokia Corporation
   5  * Author: Juha Yrjölä <juha.yrjola@nokia.com>
   6  * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
   7  * Graphics DMA and LCD DMA graphics tranformations
   8  * by Imre Deak <imre.deak@nokia.com>
   9  * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
  10  * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
  11  * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
  12  *
  13  * Copyright (C) 2009 Texas Instruments
  14  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  15  *
  16  * Support functions for the OMAP internal DMA channels.
  17  *
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License version 2 as
  20  * published by the Free Software Foundation.
  21  *
  22  */
  23
  24 #include <linux/module.h>
  25 #include <linux/init.h>
  26 #include <linux/sched.h>
  27 #include <linux/spinlock.h>
  28 #include <linux/errno.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/irq.h>
  31 #include <linux/io.h>
  32
  33 #include <asm/system.h>
  34 #include <mach/hardware.h>
  35 #include <mach/dma.h>
  36
  37 #include <mach/tc.h>
  38
  39 #undef DEBUG
  40
  41 #ifndef CONFIG_ARCH_OMAP1
  42 enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
  43         DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
  44 };
  45
  46 enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
  47 #endif
  48
  49 #define OMAP_DMA_ACTIVE                 0x01
  50 #define OMAP_DMA_CCR_EN                 (1 << 7)
  51 #define OMAP2_DMA_CSR_CLEAR_MASK        0xffe
  52
  53 #define OMAP_FUNC_MUX_ARM_BASE          (0xfffe1000 + 0xec)
  54
  55 static int enable_1510_mode;
  56
  57 struct omap_dma_lch {
  58         int next_lch;
  59         int dev_id;
  60         u16 saved_csr;
  61         u16 enabled_irqs;
  62         const char *dev_name;
  63         void (*callback)(int lch, u16 ch_status, void *data);
  64         void *data;
  65
  66 #ifndef CONFIG_ARCH_OMAP1
  67         /* required for Dynamic chaining */
  68         int prev_linked_ch;
  69         int next_linked_ch;
  70         int state;
  71         int chain_id;
  72
  73         int status;
  74 #endif
  75         long flags;
  76 };
  77
  78 struct dma_link_info {
  79         int *linked_dmach_q;
  80         int no_of_lchs_linked;
  81
  82         int q_count;
  83         int q_tail;
  84         int q_head;
  85
  86         int chain_state;
  87         int chain_mode;
  88
  89 };
  90
  91 static struct dma_link_info *dma_linked_lch;
  92
  93 #ifndef CONFIG_ARCH_OMAP1
  94
  95 /* Chain handling macros */
  96 #define OMAP_DMA_CHAIN_QINIT(chain_id)                                  \
  97         do {                                                            \
  98                 dma_linked_lch[chain_id].q_head =                       \
  99                 dma_linked_lch[chain_id].q_tail =                       \
 100                 dma_linked_lch[chain_id].q_count = 0;                   \
 101         } while (0)
 102 #define OMAP_DMA_CHAIN_QFULL(chain_id)                                  \
 103                 (dma_linked_lch[chain_id].no_of_lchs_linked ==          \
 104                 dma_linked_lch[chain_id].q_count)
 105 #define OMAP_DMA_CHAIN_QLAST(chain_id)                                  \
 106         do {                                                            \
 107                 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) ==      \
 108                 dma_linked_lch[chain_id].q_count)                       \
 109         } while (0)
 110 #define OMAP_DMA_CHAIN_QEMPTY(chain_id)                                 \
 111                 (0 == dma_linked_lch[chain_id].q_count)
 112 #define __OMAP_DMA_CHAIN_INCQ(end)                                      \
 113         ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
 114 #define OMAP_DMA_CHAIN_INCQHEAD(chain_id)                               \
 115         do {                                                            \
 116                 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
 117                 dma_linked_lch[chain_id].q_count--;                     \
 118         } while (0)
 119
 120 #define OMAP_DMA_CHAIN_INCQTAIL(chain_id)                               \
 121         do {                                                            \
 122                 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
 123                 dma_linked_lch[chain_id].q_count++; \
 124         } while (0)
 125 #endif
 126
 127 static int dma_lch_count;
 128 static int dma_chan_count;
 129 static int omap_dma_reserve_channels;
 130
 131 static spinlock_t dma_chan_lock;
 132 static struct omap_dma_lch *dma_chan;
 133 static void __iomem *omap_dma_base;
 134
 135 static const u8 omap1_dma_irq[OMAP1_LOGICAL_DMA_CH_COUNT] = {
 136         INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3,
 137         INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7,
 138         INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10,
 139         INT_1610_DMA_CH11, INT_1610_DMA_CH12, INT_1610_DMA_CH13,
 140         INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD
 141 };
 142
 143 static inline void disable_lnk(int lch);
 144 static void omap_disable_channel_irq(int lch);
 145 static inline void omap_enable_channel_irq(int lch);
 146
 147 #define REVISIT_24XX()          printk(KERN_ERR "FIXME: no %s on 24xx\n", \
 148                                                 __func__);
 149
 150 #define dma_read(reg)                                                   \
 151 ({                                                                      \
 152         u32 __val;                                                      \
 153         if (cpu_class_is_omap1())                                       \
 154                 __val = __raw_readw(omap_dma_base + OMAP1_DMA_##reg);   \
 155         else                                                            \
 156                 __val = __raw_readl(omap_dma_base + OMAP_DMA4_##reg);   \
 157         __val;                                                          \
 158 })
 159
 160 #define dma_write(val, reg)                                             \
 161 ({                                                                      \
 162         if (cpu_class_is_omap1())                                       \
 163                 __raw_writew((u16)(val), omap_dma_base + OMAP1_DMA_##reg); \
 164         else                                                            \
 165                 __raw_writel((val), omap_dma_base + OMAP_DMA4_##reg);   \
 166 })
 167
 168 #ifdef CONFIG_ARCH_OMAP15XX
 169 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
 170 int omap_dma_in_1510_mode(void)
 171 {
 172         return enable_1510_mode;
 173 }
 174 #else
 175 #define omap_dma_in_1510_mode()         0
 176 #endif
 177
 178 #ifdef CONFIG_ARCH_OMAP1
 179 static inline int get_gdma_dev(int req)
 180 {
 181         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
 182         int shift = ((req - 1) % 5) * 6;
 183
 184         return ((omap_readl(reg) >> shift) & 0x3f) + 1;
 185 }
 186
 187 static inline void set_gdma_dev(int req, int dev)
 188 {
 189         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
 190         int shift = ((req - 1) % 5) * 6;
 191         u32 l;
 192
 193         l = omap_readl(reg);
 194         l &= ~(0x3f << shift);
 195         l |= (dev - 1) << shift;
 196         omap_writel(l, reg);
 197 }
 198 #else
 199 #define set_gdma_dev(req, dev)  do {} while (0)
 200 #endif
 201
 202 /* Omap1 only */
 203 static void clear_lch_regs(int lch)
 204 {
 205         int i;
 206         void __iomem *lch_base = omap_dma_base + OMAP1_DMA_CH_BASE(lch);
 207
 208         for (i = 0; i < 0x2c; i += 2)
 209                 __raw_writew(0, lch_base + i);
 210 }
 211
 212 void omap_set_dma_priority(int lch, int dst_port, int priority)
 213 {
 214         unsigned long reg;
 215         u32 l;
 216
 217         if (cpu_class_is_omap1()) {
 218                 switch (dst_port) {
 219                 case OMAP_DMA_PORT_OCP_T1:      /* FFFECC00 */
 220                         reg = OMAP_TC_OCPT1_PRIOR;
 221                         break;
 222                 case OMAP_DMA_PORT_OCP_T2:      /* FFFECCD0 */
 223                         reg = OMAP_TC_OCPT2_PRIOR;
 224                         break;
 225                 case OMAP_DMA_PORT_EMIFF:       /* FFFECC08 */
 226                         reg = OMAP_TC_EMIFF_PRIOR;
 227                         break;
 228                 case OMAP_DMA_PORT_EMIFS:       /* FFFECC04 */
 229                         reg = OMAP_TC_EMIFS_PRIOR;
 230                         break;
 231                 default:
 232                         BUG();
 233                         return;
 234                 }
 235                 l = omap_readl(reg);
 236                 l &= ~(0xf << 8);
 237                 l |= (priority & 0xf) << 8;
 238                 omap_writel(l, reg);
 239         }
 240
 241         if (cpu_class_is_omap2()) {
 242                 u32 ccr;
 243
 244                 ccr = dma_read(CCR(lch));
 245                 if (priority)
 246                         ccr |= (1 << 6);
 247                 else
 248                         ccr &= ~(1 << 6);
 249                 dma_write(ccr, CCR(lch));
 250         }
 251 }
 252 EXPORT_SYMBOL(omap_set_dma_priority);
 253
 254 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
 255                                   int frame_count, int sync_mode,
 256                                   int dma_trigger, int src_or_dst_synch)
 257 {
 258         u32 l;
 259
 260         l = dma_read(CSDP(lch));
 261         l &= ~0x03;
 262         l |= data_type;
 263         dma_write(l, CSDP(lch));
 264
 265         if (cpu_class_is_omap1()) {
 266                 u16 ccr;
 267
 268                 ccr = dma_read(CCR(lch));
 269                 ccr &= ~(1 << 5);
 270                 if (sync_mode == OMAP_DMA_SYNC_FRAME)
 271                         ccr |= 1 << 5;
 272                 dma_write(ccr, CCR(lch));
 273
 274                 ccr = dma_read(CCR2(lch));
 275                 ccr &= ~(1 << 2);
 276                 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
 277                         ccr |= 1 << 2;
 278                 dma_write(ccr, CCR2(lch));
 279         }
 280
 281         if (cpu_class_is_omap2() && dma_trigger) {
 282                 u32 val;
 283
 284                 val = dma_read(CCR(lch));
 285
 286                 /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
 287                 val &= ~((3 << 19) | 0x1f);
 288                 val |= (dma_trigger & ~0x1f) << 14;
 289                 val |= dma_trigger & 0x1f;
 290
 291                 if (sync_mode & OMAP_DMA_SYNC_FRAME)
 292                         val |= 1 << 5;
 293                 else
 294                         val &= ~(1 << 5);
 295
 296                 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
 297                         val |= 1 << 18;
 298                 else
 299                         val &= ~(1 << 18);
 300
 301                 if (src_or_dst_synch)
 302                         val |= 1 << 24;         /* source synch */
 303                 else
 304                         val &= ~(1 << 24);      /* dest synch */
 305
 306                 dma_write(val, CCR(lch));
 307         }
 308
 309         dma_write(elem_count, CEN(lch));
 310         dma_write(frame_count, CFN(lch));
 311 }
 312 EXPORT_SYMBOL(omap_set_dma_transfer_params);
 313
 314 void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
 315 {
 316         BUG_ON(omap_dma_in_1510_mode());
 317
 318         if (cpu_class_is_omap1()) {
 319                 u16 w;
 320
 321                 w = dma_read(CCR2(lch));
 322                 w &= ~0x03;
 323
 324                 switch (mode) {
 325                 case OMAP_DMA_CONSTANT_FILL:
 326                         w |= 0x01;
 327                         break;
 328                 case OMAP_DMA_TRANSPARENT_COPY:
 329                         w |= 0x02;
 330                         break;
 331                 case OMAP_DMA_COLOR_DIS:
 332                         break;
 333                 default:
 334                         BUG();
 335                 }
 336                 dma_write(w, CCR2(lch));
 337
 338                 w = dma_read(LCH_CTRL(lch));
 339                 w &= ~0x0f;
 340                 /* Default is channel type 2D */
 341                 if (mode) {
 342                         dma_write((u16)color, COLOR_L(lch));
 343                         dma_write((u16)(color >> 16), COLOR_U(lch));
 344                         w |= 1;         /* Channel type G */
 345                 }
 346                 dma_write(w, LCH_CTRL(lch));
 347         }
 348
 349         if (cpu_class_is_omap2()) {
 350                 u32 val;
 351
 352                 val = dma_read(CCR(lch));
 353                 val &= ~((1 << 17) | (1 << 16));
 354
 355                 switch (mode) {
 356                 case OMAP_DMA_CONSTANT_FILL:
 357                         val |= 1 << 16;
 358                         break;
 359                 case OMAP_DMA_TRANSPARENT_COPY:
 360                         val |= 1 << 17;
 361                         break;
 362                 case OMAP_DMA_COLOR_DIS:
 363                         break;
 364                 default:
 365                         BUG();
 366                 }
 367                 dma_write(val, CCR(lch));
 368
 369                 color &= 0xffffff;
 370                 dma_write(color, COLOR(lch));
 371         }
 372 }
 373 EXPORT_SYMBOL(omap_set_dma_color_mode);
 374
 375 void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
 376 {
 377         if (cpu_class_is_omap2()) {
 378                 u32 csdp;
 379
 380                 csdp = dma_read(CSDP(lch));
 381                 csdp &= ~(0x3 << 16);
 382                 csdp |= (mode << 16);
 383                 dma_write(csdp, CSDP(lch));
 384         }
 385 }
 386 EXPORT_SYMBOL(omap_set_dma_write_mode);
 387
 388 void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
 389 {
 390         if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
 391                 u32 l;
 392
 393                 l = dma_read(LCH_CTRL(lch));
 394                 l &= ~0x7;
 395                 l |= mode;
 396                 dma_write(l, LCH_CTRL(lch));
 397         }
 398 }
 399 EXPORT_SYMBOL(omap_set_dma_channel_mode);
 400
 401 /* Note that src_port is only for omap1 */
 402 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
 403                              unsigned long src_start,
 404                              int src_ei, int src_fi)
 405 {
 406         u32 l;
 407
 408         if (cpu_class_is_omap1()) {
 409                 u16 w;
 410
 411                 w = dma_read(CSDP(lch));
 412                 w &= ~(0x1f << 2);
 413                 w |= src_port << 2;
 414                 dma_write(w, CSDP(lch));
 415         }
 416
 417         l = dma_read(CCR(lch));
 418         l &= ~(0x03 << 12);
 419         l |= src_amode << 12;
 420         dma_write(l, CCR(lch));
 421
 422         if (cpu_class_is_omap1()) {
 423                 dma_write(src_start >> 16, CSSA_U(lch));
 424                 dma_write((u16)src_start, CSSA_L(lch));
 425         }
 426
 427         if (cpu_class_is_omap2())
 428                 dma_write(src_start, CSSA(lch));
 429
 430         dma_write(src_ei, CSEI(lch));
 431         dma_write(src_fi, CSFI(lch));
 432 }
 433 EXPORT_SYMBOL(omap_set_dma_src_params);
 434
 435 void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
 436 {
 437         omap_set_dma_transfer_params(lch, params->data_type,
 438                                      params->elem_count, params->frame_count,
 439                                      params->sync_mode, params->trigger,
 440                                      params->src_or_dst_synch);
 441         omap_set_dma_src_params(lch, params->src_port,
 442                                 params->src_amode, params->src_start,
 443                                 params->src_ei, params->src_fi);
 444
 445         omap_set_dma_dest_params(lch, params->dst_port,
 446                                  params->dst_amode, params->dst_start,
 447                                  params->dst_ei, params->dst_fi);
 448         if (params->read_prio || params->write_prio)
 449                 omap_dma_set_prio_lch(lch, params->read_prio,
 450                                       params->write_prio);
 451 }
 452 EXPORT_SYMBOL(omap_set_dma_params);
 453
 454 void omap_set_dma_src_index(int lch, int eidx, int fidx)
 455 {
 456         if (cpu_class_is_omap2())
 457                 return;
 458
 459         dma_write(eidx, CSEI(lch));
 460         dma_write(fidx, CSFI(lch));
 461 }
 462 EXPORT_SYMBOL(omap_set_dma_src_index);
 463
 464 void omap_set_dma_src_data_pack(int lch, int enable)
 465 {
 466         u32 l;
 467
 468         l = dma_read(CSDP(lch));
 469         l &= ~(1 << 6);
 470         if (enable)
 471                 l |= (1 << 6);
 472         dma_write(l, CSDP(lch));
 473 }
 474 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
 475
 476 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
 477 {
 478         unsigned int burst = 0;
 479         u32 l;
 480
 481         l = dma_read(CSDP(lch));
 482         l &= ~(0x03 << 7);
 483
 484         switch (burst_mode) {
 485         case OMAP_DMA_DATA_BURST_DIS:
 486                 break;
 487         case OMAP_DMA_DATA_BURST_4:
 488                 if (cpu_class_is_omap2())
 489                         burst = 0x1;
 490                 else
 491                         burst = 0x2;
 492                 break;
 493         case OMAP_DMA_DATA_BURST_8:
 494                 if (cpu_class_is_omap2()) {
 495                         burst = 0x2;
 496                         break;
 497                 }
 498                 /* not supported by current hardware on OMAP1
 499                  * w |= (0x03 << 7);
 500                  * fall through
 501                  */
 502         case OMAP_DMA_DATA_BURST_16:
 503                 if (cpu_class_is_omap2()) {
 504                         burst = 0x3;
 505                         break;
 506                 }
 507                 /* OMAP1 don't support burst 16
 508                  * fall through
 509                  */
 510         default:
 511                 BUG();
 512         }
 513
 514         l |= (burst << 7);
 515         dma_write(l, CSDP(lch));
 516 }
 517 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
 518
 519 /* Note that dest_port is only for OMAP1 */
 520 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
 521                               unsigned long dest_start,
 522                               int dst_ei, int dst_fi)
 523 {
 524         u32 l;
 525
 526         if (cpu_class_is_omap1()) {
 527                 l = dma_read(CSDP(lch));
 528                 l &= ~(0x1f << 9);
 529                 l |= dest_port << 9;
 530                 dma_write(l, CSDP(lch));
 531         }
 532
 533         l = dma_read(CCR(lch));
 534         l &= ~(0x03 << 14);
 535         l |= dest_amode << 14;
 536         dma_write(l, CCR(lch));
 537
 538         if (cpu_class_is_omap1()) {
 539                 dma_write(dest_start >> 16, CDSA_U(lch));
 540                 dma_write(dest_start, CDSA_L(lch));
 541         }
 542
 543         if (cpu_class_is_omap2())
 544                 dma_write(dest_start, CDSA(lch));
 545
 546         dma_write(dst_ei, CDEI(lch));
 547         dma_write(dst_fi, CDFI(lch));
 548 }
 549 EXPORT_SYMBOL(omap_set_dma_dest_params);
 550
 551 void omap_set_dma_dest_index(int lch, int eidx, int fidx)
 552 {
 553         if (cpu_class_is_omap2())
 554                 return;
 555
 556         dma_write(eidx, CDEI(lch));
 557         dma_write(fidx, CDFI(lch));
 558 }
 559 EXPORT_SYMBOL(omap_set_dma_dest_index);
 560
 561 void omap_set_dma_dest_data_pack(int lch, int enable)
 562 {
 563         u32 l;
 564
 565         l = dma_read(CSDP(lch));
 566         l &= ~(1 << 13);
 567         if (enable)
 568                 l |= 1 << 13;
 569         dma_write(l, CSDP(lch));
 570 }
 571 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
 572
 573 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
 574 {
 575         unsigned int burst = 0;
 576         u32 l;
 577
 578         l = dma_read(CSDP(lch));
 579         l &= ~(0x03 << 14);
 580
 581         switch (burst_mode) {
 582         case OMAP_DMA_DATA_BURST_DIS:
 583                 break;
 584         case OMAP_DMA_DATA_BURST_4:
 585                 if (cpu_class_is_omap2())
 586                         burst = 0x1;
 587                 else
 588                         burst = 0x2;
 589                 break;
 590         case OMAP_DMA_DATA_BURST_8:
 591                 if (cpu_class_is_omap2())
 592                         burst = 0x2;
 593                 else
 594                         burst = 0x3;
 595                 break;
 596         case OMAP_DMA_DATA_BURST_16:
 597                 if (cpu_class_is_omap2()) {
 598                         burst = 0x3;
 599                         break;
 600                 }
 601                 /* OMAP1 don't support burst 16
 602                  * fall through
 603                  */
 604         default:
 605                 printk(KERN_ERR "Invalid DMA burst mode\n");
 606                 BUG();
 607                 return;
 608         }
 609         l |= (burst << 14);
 610         dma_write(l, CSDP(lch));
 611 }
 612 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
 613
 614 static inline void omap_enable_channel_irq(int lch)
 615 {
 616         u32 status;
 617
 618         /* Clear CSR */
 619         if (cpu_class_is_omap1())
 620                 status = dma_read(CSR(lch));
 621         else if (cpu_class_is_omap2())
 622                 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
 623
 624         /* Enable some nice interrupts. */
 625         dma_write(dma_chan[lch].enabled_irqs, CICR(lch));
 626 }
 627
 628 static void omap_disable_channel_irq(int lch)
 629 {
 630         if (cpu_class_is_omap2())
 631                 dma_write(0, CICR(lch));
 632 }
 633
 634 void omap_enable_dma_irq(int lch, u16 bits)
 635 {
 636         dma_chan[lch].enabled_irqs |= bits;
 637 }
 638 EXPORT_SYMBOL(omap_enable_dma_irq);
 639
 640 void omap_disable_dma_irq(int lch, u16 bits)
 641 {
 642         dma_chan[lch].enabled_irqs &= ~bits;
 643 }
 644 EXPORT_SYMBOL(omap_disable_dma_irq);
 645
 646 static inline void enable_lnk(int lch)
 647 {
 648         u32 l;
 649
 650         l = dma_read(CLNK_CTRL(lch));
 651
 652         if (cpu_class_is_omap1())
 653                 l &= ~(1 << 14);
 654
 655         /* Set the ENABLE_LNK bits */
 656         if (dma_chan[lch].next_lch != -1)
 657                 l = dma_chan[lch].next_lch | (1 << 15);
 658
 659 #ifndef CONFIG_ARCH_OMAP1
 660         if (cpu_class_is_omap2())
 661                 if (dma_chan[lch].next_linked_ch != -1)
 662                         l = dma_chan[lch].next_linked_ch | (1 << 15);
 663 #endif
 664
 665         dma_write(l, CLNK_CTRL(lch));
 666 }
 667
 668 static inline void disable_lnk(int lch)
 669 {
 670         u32 l;
 671
 672         l = dma_read(CLNK_CTRL(lch));
 673
 674         /* Disable interrupts */
 675         if (cpu_class_is_omap1()) {
 676                 dma_write(0, CICR(lch));
 677                 /* Set the STOP_LNK bit */
 678                 l |= 1 << 14;
 679         }
 680
 681         if (cpu_class_is_omap2()) {
 682                 omap_disable_channel_irq(lch);
 683                 /* Clear the ENABLE_LNK bit */
 684                 l &= ~(1 << 15);
 685         }
 686
 687         dma_write(l, CLNK_CTRL(lch));
 688         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
 689 }
 690
 691 static inline void omap2_enable_irq_lch(int lch)
 692 {
 693         u32 val;
 694
 695         if (!cpu_class_is_omap2())
 696                 return;
 697
 698         val = dma_read(IRQENABLE_L0);
 699         val |= 1 << lch;
 700         dma_write(val, IRQENABLE_L0);
 701 }
 702
 703 int omap_request_dma(int dev_id, const char *dev_name,
 704                      void (*callback)(int lch, u16 ch_status, void *data),
 705                      void *data, int *dma_ch_out)
 706 {
 707         int ch, free_ch = -1;
 708         unsigned long flags;
 709         struct omap_dma_lch *chan;
 710
 711         spin_lock_irqsave(&dma_chan_lock, flags);
 712         for (ch = 0; ch < dma_chan_count; ch++) {
 713                 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
 714                         free_ch = ch;
 715                         if (dev_id == 0)
 716                                 break;
 717                 }
 718         }
 719         if (free_ch == -1) {
 720                 spin_unlock_irqrestore(&dma_chan_lock, flags);
 721                 return -EBUSY;
 722         }
 723         chan = dma_chan + free_ch;
 724         chan->dev_id = dev_id;
 725
 726         if (cpu_class_is_omap1())
 727                 clear_lch_regs(free_ch);
 728
 729         if (cpu_class_is_omap2())
 730                 omap_clear_dma(free_ch);
 731
 732         spin_unlock_irqrestore(&dma_chan_lock, flags);
 733
 734         chan->dev_name = dev_name;
 735         chan->callback = callback;
 736         chan->data = data;
 737         chan->flags = 0;
 738
 739 #ifndef CONFIG_ARCH_OMAP1
 740         if (cpu_class_is_omap2()) {
 741                 chan->chain_id = -1;
 742                 chan->next_linked_ch = -1;
 743         }
 744 #endif
 745
 746         chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
 747
 748         if (cpu_class_is_omap1())
 749                 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
 750         else if (cpu_class_is_omap2())
 751                 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
 752                         OMAP2_DMA_TRANS_ERR_IRQ;
 753
 754         if (cpu_is_omap16xx()) {
 755                 /* If the sync device is set, configure it dynamically. */
 756                 if (dev_id != 0) {
 757                         set_gdma_dev(free_ch + 1, dev_id);
 758                         dev_id = free_ch + 1;
 759                 }
 760                 /*
 761                  * Disable the 1510 compatibility mode and set the sync device
 762                  * id.
 763                  */
 764                 dma_write(dev_id | (1 << 10), CCR(free_ch));
 765         } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) {
 766                 dma_write(dev_id, CCR(free_ch));
 767         }
 768
 769         if (cpu_class_is_omap2()) {
 770                 omap2_enable_irq_lch(free_ch);
 771                 omap_enable_channel_irq(free_ch);
 772                 /* Clear the CSR register and IRQ status register */
 773                 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(free_ch));
 774                 dma_write(1 << free_ch, IRQSTATUS_L0);
 775         }
 776
 777         *dma_ch_out = free_ch;
 778
 779         return 0;
 780 }
 781 EXPORT_SYMBOL(omap_request_dma);
 782
 783 void omap_free_dma(int lch)
 784 {
 785         unsigned long flags;
 786
 787         if (dma_chan[lch].dev_id == -1) {
 788                 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
 789                        lch);
 790                 return;
 791         }
 792
 793         if (cpu_class_is_omap1()) {
 794                 /* Disable all DMA interrupts for the channel. */
 795                 dma_write(0, CICR(lch));
 796                 /* Make sure the DMA transfer is stopped. */
 797                 dma_write(0, CCR(lch));
 798         }
 799
 800         if (cpu_class_is_omap2()) {
 801                 u32 val;
 802                 /* Disable interrupts */
 803                 val = dma_read(IRQENABLE_L0);
 804                 val &= ~(1 << lch);
 805                 dma_write(val, IRQENABLE_L0);
 806
 807                 /* Clear the CSR register and IRQ status register */
 808                 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
 809                 dma_write(1 << lch, IRQSTATUS_L0);
 810
 811                 /* Disable all DMA interrupts for the channel. */
 812                 dma_write(0, CICR(lch));
 813
 814                 /* Make sure the DMA transfer is stopped. */
 815                 dma_write(0, CCR(lch));
 816                 omap_clear_dma(lch);
 817         }
 818
 819         spin_lock_irqsave(&dma_chan_lock, flags);
 820         dma_chan[lch].dev_id = -1;
 821         dma_chan[lch].next_lch = -1;
 822         dma_chan[lch].callback = NULL;
 823         spin_unlock_irqrestore(&dma_chan_lock, flags);
 824 }
 825 EXPORT_SYMBOL(omap_free_dma);
 826
 827 /**
 828  * @brief omap_dma_set_global_params : Set global priority settings for dma
 829  *
 830  * @param arb_rate
 831  * @param max_fifo_depth
 832  * @param tparams - Number of thereads to reserve : DMA_THREAD_RESERVE_NORM
 833  *                                                  DMA_THREAD_RESERVE_ONET
 834  *                                                  DMA_THREAD_RESERVE_TWOT
 835  *                                                  DMA_THREAD_RESERVE_THREET
 836  */
 837 void
 838 omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
 839 {
 840         u32 reg;
 841
 842         if (!cpu_class_is_omap2()) {
 843                 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
 844                 return;
 845         }
 846
 847         if (arb_rate == 0)
 848                 arb_rate = 1;
 849
 850         reg = (arb_rate & 0xff) << 16;
 851         reg |= (0xff & max_fifo_depth);
 852
 853         dma_write(reg, GCR);
 854 }
 855 EXPORT_SYMBOL(omap_dma_set_global_params);
 856
 857 /**
 858  * @brief omap_dma_set_prio_lch : Set channel wise priority settings
 859  *
 860  * @param lch
 861  * @param read_prio - Read priority
 862  * @param write_prio - Write priority
 863  * Both of the above can be set with one of the following values :
 864  *      DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
 865  */
 866 int
 867 omap_dma_set_prio_lch(int lch, unsigned char read_prio,
 868                       unsigned char write_prio)
 869 {
 870         u32 l;
 871
 872         if (unlikely((lch < 0 || lch >= dma_lch_count))) {
 873                 printk(KERN_ERR "Invalid channel id\n");
 874                 return -EINVAL;
 875         }
 876         l = dma_read(CCR(lch));
 877         l &= ~((1 << 6) | (1 << 26));
 878         if (cpu_is_omap2430() || cpu_is_omap34xx() ||  cpu_is_omap44xx())
 879                 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
 880         else
 881                 l |= ((read_prio & 0x1) << 6);
 882
 883         dma_write(l, CCR(lch));
 884
 885         return 0;
 886 }
 887 EXPORT_SYMBOL(omap_dma_set_prio_lch);
 888
 889 /*
 890  * Clears any DMA state so the DMA engine is ready to restart with new buffers
 891  * through omap_start_dma(). Any buffers in flight are discarded.
 892  */
 893 void omap_clear_dma(int lch)
 894 {
 895         unsigned long flags;
 896
 897         local_irq_save(flags);
 898
 899         if (cpu_class_is_omap1()) {
 900                 u32 l;
 901
 902                 l = dma_read(CCR(lch));
 903                 l &= ~OMAP_DMA_CCR_EN;
 904                 dma_write(l, CCR(lch));
 905
 906                 /* Clear pending interrupts */
 907                 l = dma_read(CSR(lch));
 908         }
 909
 910         if (cpu_class_is_omap2()) {
 911                 int i;
 912                 void __iomem *lch_base = omap_dma_base + OMAP_DMA4_CH_BASE(lch);
 913                 for (i = 0; i < 0x44; i += 4)
 914                         __raw_writel(0, lch_base + i);
 915         }
 916
 917         local_irq_restore(flags);
 918 }
 919 EXPORT_SYMBOL(omap_clear_dma);
 920
 921 void omap_start_dma(int lch)
 922 {
 923         u32 l;
 924
 925         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
 926                 int next_lch, cur_lch;
 927                 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
 928
 929                 dma_chan_link_map[lch] = 1;
 930                 /* Set the link register of the first channel */
 931                 enable_lnk(lch);
 932
 933                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
 934                 cur_lch = dma_chan[lch].next_lch;
 935                 do {
 936                         next_lch = dma_chan[cur_lch].next_lch;
 937
 938                         /* The loop case: we've been here already */
 939                         if (dma_chan_link_map[cur_lch])
 940                                 break;
 941                         /* Mark the current channel */
 942                         dma_chan_link_map[cur_lch] = 1;
 943
 944                         enable_lnk(cur_lch);
 945                         omap_enable_channel_irq(cur_lch);
 946
 947                         cur_lch = next_lch;
 948                 } while (next_lch != -1);
 949         } else if (cpu_class_is_omap2()) {
 950                 /* Errata: Need to write lch even if not using chaining */
 951                 dma_write(lch, CLNK_CTRL(lch));
 952         }
 953
 954         omap_enable_channel_irq(lch);
 955
 956         l = dma_read(CCR(lch));
 957
 958         /*
 959          * Errata: On ES2.0 BUFFERING disable must be set.
 960          * This will always fail on ES1.0
 961          */
 962         if (cpu_is_omap24xx())
 963                 l |= OMAP_DMA_CCR_EN;
 964
 965         l |= OMAP_DMA_CCR_EN;
 966         dma_write(l, CCR(lch));
 967
 968         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
 969 }
 970 EXPORT_SYMBOL(omap_start_dma);
 971
 972 void omap_stop_dma(int lch)
 973 {
 974         u32 l;
 975
 976         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
 977                 int next_lch, cur_lch = lch;
 978                 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
 979
 980                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
 981                 do {
 982                         /* The loop case: we've been here already */
 983                         if (dma_chan_link_map[cur_lch])
 984                                 break;
 985                         /* Mark the current channel */
 986                         dma_chan_link_map[cur_lch] = 1;
 987
 988                         disable_lnk(cur_lch);
 989
 990                         next_lch = dma_chan[cur_lch].next_lch;
 991                         cur_lch = next_lch;
 992                 } while (next_lch != -1);
 993
 994                 return;
 995         }
 996
 997         /* Disable all interrupts on the channel */
 998         if (cpu_class_is_omap1())
 999                 dma_write(0, CICR(lch));
1000
1001         l = dma_read(CCR(lch));
1002         l &= ~OMAP_DMA_CCR_EN;
1003         dma_write(l, CCR(lch));
1004
1005         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
1006 }
1007 EXPORT_SYMBOL(omap_stop_dma);
1008
1009 /*
1010  * Allows changing the DMA callback function or data. This may be needed if
1011  * the driver shares a single DMA channel for multiple dma triggers.
1012  */
1013 int omap_set_dma_callback(int lch,
1014                           void (*callback)(int lch, u16 ch_status, void *data),
1015                           void *data)
1016 {
1017         unsigned long flags;
1018
1019         if (lch < 0)
1020                 return -ENODEV;
1021
1022         spin_lock_irqsave(&dma_chan_lock, flags);
1023         if (dma_chan[lch].dev_id == -1) {
1024                 printk(KERN_ERR "DMA callback for not set for free channel\n");
1025                 spin_unlock_irqrestore(&dma_chan_lock, flags);
1026                 return -EINVAL;
1027         }
1028         dma_chan[lch].callback = callback;
1029         dma_chan[lch].data = data;
1030         spin_unlock_irqrestore(&dma_chan_lock, flags);
1031
1032         return 0;
1033 }
1034 EXPORT_SYMBOL(omap_set_dma_callback);
1035
1036 /*
1037  * Returns current physical source address for the given DMA channel.
1038  * If the channel is running the caller must disable interrupts prior calling
1039  * this function and process the returned value before re-enabling interrupt to
1040  * prevent races with the interrupt handler. Note that in continuous mode there
1041  * is a chance for CSSA_L register overflow inbetween the two reads resulting
1042  * in incorrect return value.
1043  */
1044 dma_addr_t omap_get_dma_src_pos(int lch)
1045 {
1046         dma_addr_t offset = 0;
1047
1048         if (cpu_is_omap15xx())
1049                 offset = dma_read(CPC(lch));
1050         else
1051                 offset = dma_read(CSAC(lch));
1052
1053         /*
1054          * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1055          * read before the DMA controller finished disabling the channel.
1056          */
1057         if (!cpu_is_omap15xx() && offset == 0)
1058                 offset = dma_read(CSAC(lch));
1059
1060         if (cpu_class_is_omap1())
1061                 offset |= (dma_read(CSSA_U(lch)) << 16);
1062
1063         return offset;
1064 }
1065 EXPORT_SYMBOL(omap_get_dma_src_pos);
1066
1067 /*
1068  * Returns current physical destination address for the given DMA channel.
1069  * If the channel is running the caller must disable interrupts prior calling
1070  * this function and process the returned value before re-enabling interrupt to
1071  * prevent races with the interrupt handler. Note that in continuous mode there
1072  * is a chance for CDSA_L register overflow inbetween the two reads resulting
1073  * in incorrect return value.
1074  */
1075 dma_addr_t omap_get_dma_dst_pos(int lch)
1076 {
1077         dma_addr_t offset = 0;
1078
1079         if (cpu_is_omap15xx())
1080                 offset = dma_read(CPC(lch));
1081         else
1082                 offset = dma_read(CDAC(lch));
1083
1084         /*
1085          * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1086          * read before the DMA controller finished disabling the channel.
1087          */
1088         if (!cpu_is_omap15xx() && offset == 0)
1089                 offset = dma_read(CDAC(lch));
1090
1091         if (cpu_class_is_omap1())
1092                 offset |= (dma_read(CDSA_U(lch)) << 16);
1093
1094         return offset;
1095 }
1096 EXPORT_SYMBOL(omap_get_dma_dst_pos);
1097
1098 int omap_get_dma_active_status(int lch)
1099 {
1100         return (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN) != 0;
1101 }
1102 EXPORT_SYMBOL(omap_get_dma_active_status);
1103
1104 int omap_dma_running(void)
1105 {
1106         int lch;
1107
1108         /* Check if LCD DMA is running */
1109         if (cpu_is_omap16xx())
1110                 if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN)
1111                         return 1;
1112
1113         for (lch = 0; lch < dma_chan_count; lch++)
1114                 if (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN)
1115                         return 1;
1116
1117         return 0;
1118 }
1119
1120 /*
1121  * lch_queue DMA will start right after lch_head one is finished.
1122  * For this DMA link to start, you still need to start (see omap_start_dma)
1123  * the first one. That will fire up the entire queue.
1124  */
1125 void omap_dma_link_lch(int lch_head, int lch_queue)
1126 {
1127         if (omap_dma_in_1510_mode()) {
1128                 if (lch_head == lch_queue) {
1129                         dma_write(dma_read(CCR(lch_head)) | (3 << 8),
1130                                                                 CCR(lch_head));
1131                         return;
1132                 }
1133                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1134                 BUG();
1135                 return;
1136         }
1137
1138         if ((dma_chan[lch_head].dev_id == -1) ||
1139             (dma_chan[lch_queue].dev_id == -1)) {
1140                 printk(KERN_ERR "omap_dma: trying to link "
1141                        "non requested channels\n");
1142                 dump_stack();
1143         }
1144
1145         dma_chan[lch_head].next_lch = lch_queue;
1146 }
1147 EXPORT_SYMBOL(omap_dma_link_lch);
1148
1149 /*
1150  * Once the DMA queue is stopped, we can destroy it.
1151  */
1152 void omap_dma_unlink_lch(int lch_head, int lch_queue)
1153 {
1154         if (omap_dma_in_1510_mode()) {
1155                 if (lch_head == lch_queue) {
1156                         dma_write(dma_read(CCR(lch_head)) & ~(3 << 8),
1157                                                                 CCR(lch_head));
1158                         return;
1159                 }
1160                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1161                 BUG();
1162                 return;
1163         }
1164
1165         if (dma_chan[lch_head].next_lch != lch_queue ||
1166             dma_chan[lch_head].next_lch == -1) {
1167                 printk(KERN_ERR "omap_dma: trying to unlink "
1168                        "non linked channels\n");
1169                 dump_stack();
1170         }
1171
1172         if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
1173             (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) {
1174                 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
1175                        "before unlinking\n");
1176                 dump_stack();
1177         }
1178
1179         dma_chan[lch_head].next_lch = -1;
1180 }
1181 EXPORT_SYMBOL(omap_dma_unlink_lch);
1182
1183 /*----------------------------------------------------------------------------*/
1184
1185 #ifndef CONFIG_ARCH_OMAP1
1186 /* Create chain of DMA channesls */
1187 static void create_dma_lch_chain(int lch_head, int lch_queue)
1188 {
1189         u32 l;
1190
1191         /* Check if this is the first link in chain */
1192         if (dma_chan[lch_head].next_linked_ch == -1) {
1193                 dma_chan[lch_head].next_linked_ch = lch_queue;
1194                 dma_chan[lch_head].prev_linked_ch = lch_queue;
1195                 dma_chan[lch_queue].next_linked_ch = lch_head;
1196                 dma_chan[lch_queue].prev_linked_ch = lch_head;
1197         }
1198
1199         /* a link exists, link the new channel in circular chain */
1200         else {
1201                 dma_chan[lch_queue].next_linked_ch =
1202                                         dma_chan[lch_head].next_linked_ch;
1203                 dma_chan[lch_queue].prev_linked_ch = lch_head;
1204                 dma_chan[lch_head].next_linked_ch = lch_queue;
1205                 dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
1206                                         lch_queue;
1207         }
1208
1209         l = dma_read(CLNK_CTRL(lch_head));
1210         l &= ~(0x1f);
1211         l |= lch_queue;
1212         dma_write(l, CLNK_CTRL(lch_head));
1213
1214         l = dma_read(CLNK_CTRL(lch_queue));
1215         l &= ~(0x1f);
1216         l |= (dma_chan[lch_queue].next_linked_ch);
1217         dma_write(l, CLNK_CTRL(lch_queue));
1218 }
1219
1220 /**
1221  * @brief omap_request_dma_chain : Request a chain of DMA channels
1222  *
1223  * @param dev_id - Device id using the dma channel
1224  * @param dev_name - Device name
1225  * @param callback - Call back function
1226  * @chain_id -
1227  * @no_of_chans - Number of channels requested
1228  * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1229  *                                            OMAP_DMA_DYNAMIC_CHAIN
1230  * @params - Channel parameters
1231  *
1232  * @return - Succes : 0
1233  *           Failure: -EINVAL/-ENOMEM
1234  */
1235 int omap_request_dma_chain(int dev_id, const char *dev_name,
1236                            void (*callback) (int lch, u16 ch_status,
1237                                              void *data),
1238                            int *chain_id, int no_of_chans, int chain_mode,
1239                            struct omap_dma_channel_params params)
1240 {
1241         int *channels;
1242         int i, err;
1243
1244         /* Is the chain mode valid ? */
1245         if (chain_mode != OMAP_DMA_STATIC_CHAIN
1246                         && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
1247                 printk(KERN_ERR "Invalid chain mode requested\n");
1248                 return -EINVAL;
1249         }
1250
1251         if (unlikely((no_of_chans < 1
1252                         || no_of_chans > dma_lch_count))) {
1253                 printk(KERN_ERR "Invalid Number of channels requested\n");
1254                 return -EINVAL;
1255         }
1256
1257         /* Allocate a queue to maintain the status of the channels
1258          * in the chain */
1259         channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
1260         if (channels == NULL) {
1261                 printk(KERN_ERR "omap_dma: No memory for channel queue\n");
1262                 return -ENOMEM;
1263         }
1264
1265         /* request and reserve DMA channels for the chain */
1266         for (i = 0; i < no_of_chans; i++) {
1267                 err = omap_request_dma(dev_id, dev_name,
1268                                         callback, NULL, &channels[i]);
1269                 if (err < 0) {
1270                         int j;
1271                         for (j = 0; j < i; j++)
1272                                 omap_free_dma(channels[j]);
1273                         kfree(channels);
1274                         printk(KERN_ERR "omap_dma: Request failed %d\n", err);
1275                         return err;
1276                 }
1277                 dma_chan[channels[i]].prev_linked_ch = -1;
1278                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1279
1280                 /*
1281                  * Allowing client drivers to set common parameters now,
1282                  * so that later only relevant (src_start, dest_start
1283                  * and element count) can be set
1284                  */
1285                 omap_set_dma_params(channels[i], &params);
1286         }
1287
1288         *chain_id = channels[0];
1289         dma_linked_lch[*chain_id].linked_dmach_q = channels;
1290         dma_linked_lch[*chain_id].chain_mode = chain_mode;
1291         dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1292         dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;
1293
1294         for (i = 0; i < no_of_chans; i++)
1295                 dma_chan[channels[i]].chain_id = *chain_id;
1296
1297         /* Reset the Queue pointers */
1298         OMAP_DMA_CHAIN_QINIT(*chain_id);
1299
1300         /* Set up the chain */
1301         if (no_of_chans == 1)
1302                 create_dma_lch_chain(channels[0], channels[0]);
1303         else {
1304                 for (i = 0; i < (no_of_chans - 1); i++)
1305                         create_dma_lch_chain(channels[i], channels[i + 1]);
1306         }
1307
1308         return 0;
1309 }
1310 EXPORT_SYMBOL(omap_request_dma_chain);
1311
1312 /**
1313  * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1314  * params after setting it. Dont do this while dma is running!!
1315  *
1316  * @param chain_id - Chained logical channel id.
1317  * @param params
1318  *
1319  * @return - Success : 0
1320  *           Failure : -EINVAL
1321  */
1322 int omap_modify_dma_chain_params(int chain_id,
1323                                 struct omap_dma_channel_params params)
1324 {
1325         int *channels;
1326         u32 i;
1327
1328         /* Check for input params */
1329         if (unlikely((chain_id < 0
1330                         || chain_id >= dma_lch_count))) {
1331                 printk(KERN_ERR "Invalid chain id\n");
1332                 return -EINVAL;
1333         }
1334
1335         /* Check if the chain exists */
1336         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1337                 printk(KERN_ERR "Chain doesn't exists\n");
1338                 return -EINVAL;
1339         }
1340         channels = dma_linked_lch[chain_id].linked_dmach_q;
1341
1342         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1343                 /*
1344                  * Allowing client drivers to set common parameters now,
1345                  * so that later only relevant (src_start, dest_start
1346                  * and element count) can be set
1347                  */
1348                 omap_set_dma_params(channels[i], &params);
1349         }
1350
1351         return 0;
1352 }
1353 EXPORT_SYMBOL(omap_modify_dma_chain_params);
1354
1355 /**
1356  * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1357  *
1358  * @param chain_id
1359  *
1360  * @return - Success : 0
1361  *           Failure : -EINVAL
1362  */
1363 int omap_free_dma_chain(int chain_id)
1364 {
1365         int *channels;
1366         u32 i;
1367
1368         /* Check for input params */
1369         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1370                 printk(KERN_ERR "Invalid chain id\n");
1371                 return -EINVAL;
1372         }
1373
1374         /* Check if the chain exists */
1375         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1376                 printk(KERN_ERR "Chain doesn't exists\n");
1377                 return -EINVAL;
1378         }
1379
1380         channels = dma_linked_lch[chain_id].linked_dmach_q;
1381         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1382                 dma_chan[channels[i]].next_linked_ch = -1;
1383                 dma_chan[channels[i]].prev_linked_ch = -1;
1384                 dma_chan[channels[i]].chain_id = -1;
1385                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1386                 omap_free_dma(channels[i]);
1387         }
1388
1389         kfree(channels);
1390
1391         dma_linked_lch[chain_id].linked_dmach_q = NULL;
1392         dma_linked_lch[chain_id].chain_mode = -1;
1393         dma_linked_lch[chain_id].chain_state = -1;
1394
1395         return (0);
1396 }
1397 EXPORT_SYMBOL(omap_free_dma_chain);
1398
1399 /**
1400  * @brief omap_dma_chain_status - Check if the chain is in
1401  * active / inactive state.
1402  * @param chain_id
1403  *
1404  * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1405  *           Failure : -EINVAL
1406  */
1407 int omap_dma_chain_status(int chain_id)
1408 {
1409         /* Check for input params */
1410         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1411                 printk(KERN_ERR "Invalid chain id\n");
1412                 return -EINVAL;
1413         }
1414
1415         /* Check if the chain exists */
1416         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1417                 printk(KERN_ERR "Chain doesn't exists\n");
1418                 return -EINVAL;
1419         }
1420         pr_debug("CHAINID=%d, qcnt=%d\n", chain_id,
1421                         dma_linked_lch[chain_id].q_count);
1422
1423         if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
1424                 return OMAP_DMA_CHAIN_INACTIVE;
1425
1426         return OMAP_DMA_CHAIN_ACTIVE;
1427 }
1428 EXPORT_SYMBOL(omap_dma_chain_status);
1429
1430 /**
1431  * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1432  * set the params and start the transfer.
1433  *
1434  * @param chain_id
1435  * @param src_start - buffer start address
1436  * @param dest_start - Dest address
1437  * @param elem_count
1438  * @param frame_count
1439  * @param callbk_data - channel callback parameter data.
1440  *
1441  * @return  - Success : 0
1442  *            Failure: -EINVAL/-EBUSY
1443  */
1444 int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1445                         int elem_count, int frame_count, void *callbk_data)
1446 {
1447         int *channels;
1448         u32 l, lch;
1449         int start_dma = 0;
1450
1451         /*
1452          * if buffer size is less than 1 then there is
1453          * no use of starting the chain
1454          */
1455         if (elem_count < 1) {
1456                 printk(KERN_ERR "Invalid buffer size\n");
1457                 return -EINVAL;
1458         }
1459
1460         /* Check for input params */
1461         if (unlikely((chain_id < 0
1462                         || chain_id >= dma_lch_count))) {
1463                 printk(KERN_ERR "Invalid chain id\n");
1464                 return -EINVAL;
1465         }
1466
1467         /* Check if the chain exists */
1468         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1469                 printk(KERN_ERR "Chain doesn't exist\n");
1470                 return -EINVAL;
1471         }
1472
1473         /* Check if all the channels in chain are in use */
1474         if (OMAP_DMA_CHAIN_QFULL(chain_id))
1475                 return -EBUSY;
1476
1477         /* Frame count may be negative in case of indexed transfers */
1478         channels = dma_linked_lch[chain_id].linked_dmach_q;
1479
1480         /* Get a free channel */
1481         lch = channels[dma_linked_lch[chain_id].q_tail];
1482
1483         /* Store the callback data */
1484         dma_chan[lch].data = callbk_data;
1485
1486         /* Increment the q_tail */
1487         OMAP_DMA_CHAIN_INCQTAIL(chain_id);
1488
1489         /* Set the params to the free channel */
1490         if (src_start != 0)
1491                 dma_write(src_start, CSSA(lch));
1492         if (dest_start != 0)
1493                 dma_write(dest_start, CDSA(lch));
1494
1495         /* Write the buffer size */
1496         dma_write(elem_count, CEN(lch));
1497         dma_write(frame_count, CFN(lch));
1498
1499         /*
1500          * If the chain is dynamically linked,
1501          * then we may have to start the chain if its not active
1502          */
1503         if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
1504
1505                 /*
1506                  * In Dynamic chain, if the chain is not started,
1507                  * queue the channel
1508                  */
1509                 if (dma_linked_lch[chain_id].chain_state ==
1510                                                 DMA_CHAIN_NOTSTARTED) {
1511                         /* Enable the link in previous channel */
1512                         if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1513                                                                 DMA_CH_QUEUED)
1514                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1515                         dma_chan[lch].state = DMA_CH_QUEUED;
1516                 }
1517
1518                 /*
1519                  * Chain is already started, make sure its active,
1520                  * if not then start the chain
1521                  */
1522                 else {
1523                         start_dma = 1;
1524
1525                         if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1526                                                         DMA_CH_STARTED) {
1527                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1528                                 dma_chan[lch].state = DMA_CH_QUEUED;
1529                                 start_dma = 0;
1530                                 if (0 == ((1 << 7) & dma_read(
1531                                         CCR(dma_chan[lch].prev_linked_ch)))) {
1532                                         disable_lnk(dma_chan[lch].
1533                                                     prev_linked_ch);
1534                                         pr_debug("\n prev ch is stopped\n");
1535                                         start_dma = 1;
1536                                 }
1537                         }
1538
1539                         else if (dma_chan[dma_chan[lch].prev_linked_ch].state
1540                                                         == DMA_CH_QUEUED) {
1541                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1542                                 dma_chan[lch].state = DMA_CH_QUEUED;
1543                                 start_dma = 0;
1544                         }
1545                         omap_enable_channel_irq(lch);
1546
1547                         l = dma_read(CCR(lch));
1548
1549                         if ((0 == (l & (1 << 24))))
1550                                 l &= ~(1 << 25);
1551                         else
1552                                 l |= (1 << 25);
1553                         if (start_dma == 1) {
1554                                 if (0 == (l & (1 << 7))) {
1555                                         l |= (1 << 7);
1556                                         dma_chan[lch].state = DMA_CH_STARTED;
1557                                         pr_debug("starting %d\n", lch);
1558                                         dma_write(l, CCR(lch));
1559                                 } else
1560                                         start_dma = 0;
1561                         } else {
1562                                 if (0 == (l & (1 << 7)))
1563                                         dma_write(l, CCR(lch));
1564                         }
1565                         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1566                 }
1567         }
1568
1569         return 0;
1570 }
1571 EXPORT_SYMBOL(omap_dma_chain_a_transfer);
1572
1573 /**
1574  * @brief omap_start_dma_chain_transfers - Start the chain
1575  *
1576  * @param chain_id
1577  *
1578  * @return - Success : 0
1579  *           Failure : -EINVAL/-EBUSY
1580  */
1581 int omap_start_dma_chain_transfers(int chain_id)
1582 {
1583         int *channels;
1584         u32 l, i;
1585
1586         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1587                 printk(KERN_ERR "Invalid chain id\n");
1588                 return -EINVAL;
1589         }
1590
1591         channels = dma_linked_lch[chain_id].linked_dmach_q;
1592
1593         if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
1594                 printk(KERN_ERR "Chain is already started\n");
1595                 return -EBUSY;
1596         }
1597
1598         if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
1599                 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
1600                                                                         i++) {
1601                         enable_lnk(channels[i]);
1602                         omap_enable_channel_irq(channels[i]);
1603                 }
1604         } else {
1605                 omap_enable_channel_irq(channels[0]);
1606         }
1607
1608         l = dma_read(CCR(channels[0]));
1609         l |= (1 << 7);
1610         dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
1611         dma_chan[channels[0]].state = DMA_CH_STARTED;
1612
1613         if ((0 == (l & (1 << 24))))
1614                 l &= ~(1 << 25);
1615         else
1616                 l |= (1 << 25);
1617         dma_write(l, CCR(channels[0]));
1618
1619         dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
1620
1621         return 0;
1622 }
1623 EXPORT_SYMBOL(omap_start_dma_chain_transfers);
1624
1625 /**
1626  * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1627  *
1628  * @param chain_id
1629  *
1630  * @return - Success : 0
1631  *           Failure : EINVAL
1632  */
1633 int omap_stop_dma_chain_transfers(int chain_id)
1634 {
1635         int *channels;
1636         u32 l, i;
1637         u32 sys_cf;
1638
1639         /* Check for input params */
1640         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1641                 printk(KERN_ERR "Invalid chain id\n");
1642                 return -EINVAL;
1643         }
1644
1645         /* Check if the chain exists */
1646         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1647                 printk(KERN_ERR "Chain doesn't exists\n");
1648                 return -EINVAL;
1649         }
1650         channels = dma_linked_lch[chain_id].linked_dmach_q;
1651
1652         /*
1653          * DMA Errata:
1654          * Special programming model needed to disable DMA before end of block
1655          */
1656         sys_cf = dma_read(OCP_SYSCONFIG);
1657         l = sys_cf;
1658         /* Middle mode reg set no Standby */
1659         l &= ~((1 << 12)|(1 << 13));
1660         dma_write(l, OCP_SYSCONFIG);
1661
1662         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1663
1664                 /* Stop the Channel transmission */
1665                 l = dma_read(CCR(channels[i]));
1666                 l &= ~(1 << 7);
1667                 dma_write(l, CCR(channels[i]));
1668
1669                 /* Disable the link in all the channels */
1670                 disable_lnk(channels[i]);
1671                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1672
1673         }
1674         dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1675
1676         /* Reset the Queue pointers */
1677         OMAP_DMA_CHAIN_QINIT(chain_id);
1678
1679         /* Errata - put in the old value */
1680         dma_write(sys_cf, OCP_SYSCONFIG);
1681
1682         return 0;
1683 }
1684 EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
1685
1686 /* Get the index of the ongoing DMA in chain */
1687 /**
1688  * @brief omap_get_dma_chain_index - Get the element and frame index
1689  * of the ongoing DMA in chain
1690  *
1691  * @param chain_id
1692  * @param ei - Element index
1693  * @param fi - Frame index
1694  *
1695  * @return - Success : 0
1696  *           Failure : -EINVAL
1697  */
1698 int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1699 {
1700         int lch;
1701         int *channels;
1702
1703         /* Check for input params */
1704         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1705                 printk(KERN_ERR "Invalid chain id\n");
1706                 return -EINVAL;
1707         }
1708
1709         /* Check if the chain exists */
1710         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1711                 printk(KERN_ERR "Chain doesn't exists\n");
1712                 return -EINVAL;
1713         }
1714         if ((!ei) || (!fi))
1715                 return -EINVAL;
1716
1717         channels = dma_linked_lch[chain_id].linked_dmach_q;
1718
1719         /* Get the current channel */
1720         lch = channels[dma_linked_lch[chain_id].q_head];
1721
1722         *ei = dma_read(CCEN(lch));
1723         *fi = dma_read(CCFN(lch));
1724
1725         return 0;
1726 }
1727 EXPORT_SYMBOL(omap_get_dma_chain_index);
1728
1729 /**
1730  * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1731  * ongoing DMA in chain
1732  *
1733  * @param chain_id
1734  *
1735  * @return - Success : Destination position
1736  *           Failure : -EINVAL
1737  */
1738 int omap_get_dma_chain_dst_pos(int chain_id)
1739 {
1740         int lch;
1741         int *channels;
1742
1743         /* Check for input params */
1744         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1745                 printk(KERN_ERR "Invalid chain id\n");
1746                 return -EINVAL;
1747         }
1748
1749         /* Check if the chain exists */
1750         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1751                 printk(KERN_ERR "Chain doesn't exists\n");
1752                 return -EINVAL;
1753         }
1754
1755         channels = dma_linked_lch[chain_id].linked_dmach_q;
1756
1757         /* Get the current channel */
1758         lch = channels[dma_linked_lch[chain_id].q_head];
1759
1760         return dma_read(CDAC(lch));
1761 }
1762 EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
1763
1764 /**
1765  * @brief omap_get_dma_chain_src_pos - Get the source position
1766  * of the ongoing DMA in chain
1767  * @param chain_id
1768  *
1769  * @return - Success : Destination position
1770  *           Failure : -EINVAL
1771  */
1772 int omap_get_dma_chain_src_pos(int chain_id)
1773 {
1774         int lch;
1775         int *channels;
1776
1777         /* Check for input params */
1778         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1779                 printk(KERN_ERR "Invalid chain id\n");
1780                 return -EINVAL;
1781         }
1782
1783         /* Check if the chain exists */
1784         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1785                 printk(KERN_ERR "Chain doesn't exists\n");
1786                 return -EINVAL;
1787         }
1788
1789         channels = dma_linked_lch[chain_id].linked_dmach_q;
1790
1791         /* Get the current channel */
1792         lch = channels[dma_linked_lch[chain_id].q_head];
1793
1794         return dma_read(CSAC(lch));
1795 }
1796 EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
1797 #endif  /* ifndef CONFIG_ARCH_OMAP1 */
1798
1799 /*----------------------------------------------------------------------------*/
1800
1801 #ifdef CONFIG_ARCH_OMAP1
1802
1803 static int omap1_dma_handle_ch(int ch)
1804 {
1805         u32 csr;
1806
1807         if (enable_1510_mode && ch >= 6) {
1808                 csr = dma_chan[ch].saved_csr;
1809                 dma_chan[ch].saved_csr = 0;
1810         } else
1811                 csr = dma_read(CSR(ch));
1812         if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1813                 dma_chan[ch + 6].saved_csr = csr >> 7;
1814                 csr &= 0x7f;
1815         }
1816         if ((csr & 0x3f) == 0)
1817                 return 0;
1818         if (unlikely(dma_chan[ch].dev_id == -1)) {
1819                 printk(KERN_WARNING "Spurious interrupt from DMA channel "
1820                        "%d (CSR %04x)\n", ch, csr);
1821                 return 0;
1822         }
1823         if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
1824                 printk(KERN_WARNING "DMA timeout with device %d\n",
1825                        dma_chan[ch].dev_id);
1826         if (unlikely(csr & OMAP_DMA_DROP_IRQ))
1827                 printk(KERN_WARNING "DMA synchronization event drop occurred "
1828                        "with device %d\n", dma_chan[ch].dev_id);
1829         if (likely(csr & OMAP_DMA_BLOCK_IRQ))
1830                 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1831         if (likely(dma_chan[ch].callback != NULL))
1832                 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
1833
1834         return 1;
1835 }
1836
1837 static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1838 {
1839         int ch = ((int) dev_id) - 1;
1840         int handled = 0;
1841
1842         for (;;) {
1843                 int handled_now = 0;
1844
1845                 handled_now += omap1_dma_handle_ch(ch);
1846                 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
1847                         handled_now += omap1_dma_handle_ch(ch + 6);
1848                 if (!handled_now)
1849                         break;
1850                 handled += handled_now;
1851         }
1852
1853         return handled ? IRQ_HANDLED : IRQ_NONE;
1854 }
1855
1856 #else
1857 #define omap1_dma_irq_handler   NULL
1858 #endif
1859
1860 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
1861                         defined(CONFIG_ARCH_OMAP4)
1862
1863 static int omap2_dma_handle_ch(int ch)
1864 {
1865         u32 status = dma_read(CSR(ch));
1866
1867         if (!status) {
1868                 if (printk_ratelimit())
1869                         printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
1870                                 ch);
1871                 dma_write(1 << ch, IRQSTATUS_L0);
1872                 return 0;
1873         }
1874         if (unlikely(dma_chan[ch].dev_id == -1)) {
1875                 if (printk_ratelimit())
1876                         printk(KERN_WARNING "IRQ %04x for non-allocated DMA"
1877                                         "channel %d\n", status, ch);
1878                 return 0;
1879         }
1880         if (unlikely(status & OMAP_DMA_DROP_IRQ))
1881                 printk(KERN_INFO
1882                        "DMA synchronization event drop occurred with device "
1883                        "%d\n", dma_chan[ch].dev_id);
1884         if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
1885                 printk(KERN_INFO "DMA transaction error with device %d\n",
1886                        dma_chan[ch].dev_id);
1887                 if (cpu_class_is_omap2()) {
1888                         /* Errata: sDMA Channel is not disabled
1889                          * after a transaction error. So we explicitely
1890                          * disable the channel
1891                          */
1892                         u32 ccr;
1893
1894                         ccr = dma_read(CCR(ch));
1895                         ccr &= ~OMAP_DMA_CCR_EN;
1896                         dma_write(ccr, CCR(ch));
1897                         dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1898                 }
1899         }
1900         if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
1901                 printk(KERN_INFO "DMA secure error with device %d\n",
1902                        dma_chan[ch].dev_id);
1903         if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
1904                 printk(KERN_INFO "DMA misaligned error with device %d\n",
1905                        dma_chan[ch].dev_id);
1906
1907         dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(ch));
1908         dma_write(1 << ch, IRQSTATUS_L0);
1909
1910         /* If the ch is not chained then chain_id will be -1 */
1911         if (dma_chan[ch].chain_id != -1) {
1912                 int chain_id = dma_chan[ch].chain_id;
1913                 dma_chan[ch].state = DMA_CH_NOTSTARTED;
1914                 if (dma_read(CLNK_CTRL(ch)) & (1 << 15))
1915                         dma_chan[dma_chan[ch].next_linked_ch].state =
1916                                                         DMA_CH_STARTED;
1917                 if (dma_linked_lch[chain_id].chain_mode ==
1918                                                 OMAP_DMA_DYNAMIC_CHAIN)
1919                         disable_lnk(ch);
1920
1921                 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1922                         OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1923
1924                 status = dma_read(CSR(ch));
1925         }
1926
1927         dma_write(status, CSR(ch));
1928
1929         if (likely(dma_chan[ch].callback != NULL))
1930                 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1931
1932         return 0;
1933 }
1934
1935 /* STATUS register count is from 1-32 while our is 0-31 */
1936 static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1937 {
1938         u32 val, enable_reg;
1939         int i;
1940
1941         val = dma_read(IRQSTATUS_L0);
1942         if (val == 0) {
1943                 if (printk_ratelimit())
1944                         printk(KERN_WARNING "Spurious DMA IRQ\n");
1945                 return IRQ_HANDLED;
1946         }
1947         enable_reg = dma_read(IRQENABLE_L0);
1948         val &= enable_reg; /* Dispatch only relevant interrupts */
1949         for (i = 0; i < dma_lch_count && val != 0; i++) {
1950                 if (val & 1)
1951                         omap2_dma_handle_ch(i);
1952                 val >>= 1;
1953         }
1954
1955         return IRQ_HANDLED;
1956 }
1957
1958 static struct irqaction omap24xx_dma_irq = {
1959         .name = "DMA",
1960         .handler = omap2_dma_irq_handler,
1961         .flags = IRQF_DISABLED
1962 };
1963
1964 #else
1965 static struct irqaction omap24xx_dma_irq;
1966 #endif
1967
1968 /*----------------------------------------------------------------------------*/
1969
1970 static struct lcd_dma_info {
1971         spinlock_t lock;
1972         int reserved;
1973         void (*callback)(u16 status, void *data);
1974         void *cb_data;
1975
1976         int active;
1977         unsigned long addr, size;
1978         int rotate, data_type, xres, yres;
1979         int vxres;
1980         int mirror;
1981         int xscale, yscale;
1982         int ext_ctrl;
1983         int src_port;
1984         int single_transfer;
1985 } lcd_dma;
1986
1987 void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
1988                          int data_type)
1989 {
1990         lcd_dma.addr = addr;
1991         lcd_dma.data_type = data_type;
1992         lcd_dma.xres = fb_xres;
1993         lcd_dma.yres = fb_yres;
1994 }
1995 EXPORT_SYMBOL(omap_set_lcd_dma_b1);
1996
1997 void omap_set_lcd_dma_src_port(int port)
1998 {
1999         lcd_dma.src_port = port;
2000 }
2001
2002 void omap_set_lcd_dma_ext_controller(int external)
2003 {
2004         lcd_dma.ext_ctrl = external;
2005 }
2006 EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
2007
2008 void omap_set_lcd_dma_single_transfer(int single)
2009 {
2010         lcd_dma.single_transfer = single;
2011 }
2012 EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
2013
2014 void omap_set_lcd_dma_b1_rotation(int rotate)
2015 {
2016         if (omap_dma_in_1510_mode()) {
2017                 printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n");
2018                 BUG();
2019                 return;
2020         }
2021         lcd_dma.rotate = rotate;
2022 }
2023 EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
2024
2025 void omap_set_lcd_dma_b1_mirror(int mirror)
2026 {
2027         if (omap_dma_in_1510_mode()) {
2028                 printk(KERN_ERR "DMA mirror is not supported in 1510 mode\n");
2029                 BUG();
2030         }
2031         lcd_dma.mirror = mirror;
2032 }
2033 EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
2034
2035 void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
2036 {
2037         if (omap_dma_in_1510_mode()) {
2038                 printk(KERN_ERR "DMA virtual resulotion is not supported "
2039                                 "in 1510 mode\n");
2040                 BUG();
2041         }
2042         lcd_dma.vxres = vxres;
2043 }
2044 EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
2045
2046 void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
2047 {
2048         if (omap_dma_in_1510_mode()) {
2049                 printk(KERN_ERR "DMA scale is not supported in 1510 mode\n");
2050                 BUG();
2051         }
2052         lcd_dma.xscale = xscale;
2053         lcd_dma.yscale = yscale;
2054 }
2055 EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
2056
2057 static void set_b1_regs(void)
2058 {
2059         unsigned long top, bottom;
2060         int es;
2061         u16 w;
2062         unsigned long en, fn;
2063         long ei, fi;
2064         unsigned long vxres;
2065         unsigned int xscale, yscale;
2066
2067         switch (lcd_dma.data_type) {
2068         case OMAP_DMA_DATA_TYPE_S8:
2069                 es = 1;
2070                 break;
2071         case OMAP_DMA_DATA_TYPE_S16:
2072                 es = 2;
2073                 break;
2074         case OMAP_DMA_DATA_TYPE_S32:
2075                 es = 4;
2076                 break;
2077         default:
2078                 BUG();
2079                 return;
2080         }
2081
2082         vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres;
2083         xscale = lcd_dma.xscale ? lcd_dma.xscale : 1;
2084         yscale = lcd_dma.yscale ? lcd_dma.yscale : 1;
2085         BUG_ON(vxres < lcd_dma.xres);
2086
2087 #define PIXADDR(x, y) (lcd_dma.addr +                                   \
2088                 ((y) * vxres * yscale + (x) * xscale) * es)
2089 #define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
2090
2091         switch (lcd_dma.rotate) {
2092         case 0:
2093                 if (!lcd_dma.mirror) {
2094                         top = PIXADDR(0, 0);
2095                         bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2096                         /* 1510 DMA requires the bottom address to be 2 more
2097                          * than the actual last memory access location. */
2098                         if (omap_dma_in_1510_mode() &&
2099                                 lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
2100                                         bottom += 2;
2101                         ei = PIXSTEP(0, 0, 1, 0);
2102                         fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1);
2103                 } else {
2104                         top = PIXADDR(lcd_dma.xres - 1, 0);
2105                         bottom = PIXADDR(0, lcd_dma.yres - 1);
2106                         ei = PIXSTEP(1, 0, 0, 0);
2107                         fi = PIXSTEP(0, 0, lcd_dma.xres - 1, 1);
2108                 }
2109                 en = lcd_dma.xres;
2110                 fn = lcd_dma.yres;
2111                 break;
2112         case 90:
2113                 if (!lcd_dma.mirror) {
2114                         top = PIXADDR(0, lcd_dma.yres - 1);
2115                         bottom = PIXADDR(lcd_dma.xres - 1, 0);
2116                         ei = PIXSTEP(0, 1, 0, 0);
2117                         fi = PIXSTEP(0, 0, 1, lcd_dma.yres - 1);
2118                 } else {
2119                         top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2120                         bottom = PIXADDR(0, 0);
2121                         ei = PIXSTEP(0, 1, 0, 0);
2122                         fi = PIXSTEP(1, 0, 0, lcd_dma.yres - 1);
2123                 }
2124                 en = lcd_dma.yres;
2125                 fn = lcd_dma.xres;
2126                 break;
2127         case 180:
2128                 if (!lcd_dma.mirror) {
2129                         top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2130                         bottom = PIXADDR(0, 0);
2131                         ei = PIXSTEP(1, 0, 0, 0);
2132                         fi = PIXSTEP(0, 1, lcd_dma.xres - 1, 0);
2133                 } else {
2134                         top = PIXADDR(0, lcd_dma.yres - 1);
2135                         bottom = PIXADDR(lcd_dma.xres - 1, 0);
2136                         ei = PIXSTEP(0, 0, 1, 0);
2137                         fi = PIXSTEP(lcd_dma.xres - 1, 1, 0, 0);
2138                 }
2139                 en = lcd_dma.xres;
2140                 fn = lcd_dma.yres;
2141                 break;
2142         case 270:
2143                 if (!lcd_dma.mirror) {
2144                         top = PIXADDR(lcd_dma.xres - 1, 0);
2145                         bottom = PIXADDR(0, lcd_dma.yres - 1);
2146                         ei = PIXSTEP(0, 0, 0, 1);
2147                         fi = PIXSTEP(1, lcd_dma.yres - 1, 0, 0);
2148                 } else {
2149                         top = PIXADDR(0, 0);
2150                         bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2151                         ei = PIXSTEP(0, 0, 0, 1);
2152                         fi = PIXSTEP(0, lcd_dma.yres - 1, 1, 0);
2153                 }
2154                 en = lcd_dma.yres;
2155                 fn = lcd_dma.xres;
2156                 break;
2157         default:
2158                 BUG();
2159                 return; /* Suppress warning about uninitialized vars */
2160         }
2161
2162         if (omap_dma_in_1510_mode()) {
2163                 omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U);
2164                 omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L);
2165                 omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U);
2166                 omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L);
2167
2168                 return;
2169         }
2170
2171         /* 1610 regs */
2172         omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U);
2173         omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L);
2174         omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U);
2175         omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L);
2176
2177         omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1);
2178         omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1);
2179
2180         w = omap_readw(OMAP1610_DMA_LCD_CSDP);
2181         w &= ~0x03;
2182         w |= lcd_dma.data_type;
2183         omap_writew(w, OMAP1610_DMA_LCD_CSDP);
2184
2185         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2186         /* Always set the source port as SDRAM for now*/
2187         w &= ~(0x03 << 6);
2188         if (lcd_dma.callback != NULL)
2189                 w |= 1 << 1;            /* Block interrupt enable */
2190         else
2191                 w &= ~(1 << 1);
2192         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2193
2194         if (!(lcd_dma.rotate || lcd_dma.mirror ||
2195               lcd_dma.vxres || lcd_dma.xscale || lcd_dma.yscale))
2196                 return;
2197
2198         w = omap_readw(OMAP1610_DMA_LCD_CCR);
2199         /* Set the double-indexed addressing mode */
2200         w |= (0x03 << 12);
2201         omap_writew(w, OMAP1610_DMA_LCD_CCR);
2202
2203         omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1);
2204         omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U);
2205         omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
2206 }
2207
2208 static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id)
2209 {
2210         u16 w;
2211
2212         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2213         if (unlikely(!(w & (1 << 3)))) {
2214                 printk(KERN_WARNING "Spurious LCD DMA IRQ\n");
2215                 return IRQ_NONE;
2216         }
2217         /* Ack the IRQ */
2218         w |= (1 << 3);
2219         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2220         lcd_dma.active = 0;
2221         if (lcd_dma.callback != NULL)
2222                 lcd_dma.callback(w, lcd_dma.cb_data);
2223
2224         return IRQ_HANDLED;
2225 }
2226
2227 int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
2228                          void *data)
2229 {
2230         spin_lock_irq(&lcd_dma.lock);
2231         if (lcd_dma.reserved) {
2232                 spin_unlock_irq(&lcd_dma.lock);
2233                 printk(KERN_ERR "LCD DMA channel already reserved\n");
2234                 BUG();
2235                 return -EBUSY;
2236         }
2237         lcd_dma.reserved = 1;
2238         spin_unlock_irq(&lcd_dma.lock);
2239         lcd_dma.callback = callback;
2240         lcd_dma.cb_data = data;
2241         lcd_dma.active = 0;
2242         lcd_dma.single_transfer = 0;
2243         lcd_dma.rotate = 0;
2244         lcd_dma.vxres = 0;
2245         lcd_dma.mirror = 0;
2246         lcd_dma.xscale = 0;
2247         lcd_dma.yscale = 0;
2248         lcd_dma.ext_ctrl = 0;
2249         lcd_dma.src_port = 0;
2250
2251         return 0;
2252 }
2253 EXPORT_SYMBOL(omap_request_lcd_dma);
2254
2255 void omap_free_lcd_dma(void)
2256 {
2257         spin_lock(&lcd_dma.lock);
2258         if (!lcd_dma.reserved) {
2259                 spin_unlock(&lcd_dma.lock);
2260                 printk(KERN_ERR "LCD DMA is not reserved\n");
2261                 BUG();
2262                 return;
2263         }
2264         if (!enable_1510_mode)
2265                 omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1,
2266                             OMAP1610_DMA_LCD_CCR);
2267         lcd_dma.reserved = 0;
2268         spin_unlock(&lcd_dma.lock);
2269 }
2270 EXPORT_SYMBOL(omap_free_lcd_dma);
2271
2272 void omap_enable_lcd_dma(void)
2273 {
2274         u16 w;
2275
2276         /*
2277          * Set the Enable bit only if an external controller is
2278          * connected. Otherwise the OMAP internal controller will
2279          * start the transfer when it gets enabled.
2280          */
2281         if (enable_1510_mode || !lcd_dma.ext_ctrl)
2282                 return;
2283
2284         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2285         w |= 1 << 8;
2286         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2287
2288         lcd_dma.active = 1;
2289
2290         w = omap_readw(OMAP1610_DMA_LCD_CCR);
2291         w |= 1 << 7;
2292         omap_writew(w, OMAP1610_DMA_LCD_CCR);
2293 }
2294 EXPORT_SYMBOL(omap_enable_lcd_dma);
2295
2296 void omap_setup_lcd_dma(void)
2297 {
2298         BUG_ON(lcd_dma.active);
2299         if (!enable_1510_mode) {
2300                 /* Set some reasonable defaults */
2301                 omap_writew(0x5440, OMAP1610_DMA_LCD_CCR);
2302                 omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP);
2303                 omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL);
2304         }
2305         set_b1_regs();
2306         if (!enable_1510_mode) {
2307                 u16 w;
2308
2309                 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2310                 /*
2311                  * If DMA was already active set the end_prog bit to have
2312                  * the programmed register set loaded into the active
2313                  * register set.
2314                  */
2315                 w |= 1 << 11;           /* End_prog */
2316                 if (!lcd_dma.single_transfer)
2317                         w |= (3 << 8);  /* Auto_init, repeat */
2318                 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2319         }
2320 }
2321 EXPORT_SYMBOL(omap_setup_lcd_dma);
2322
2323 void omap_stop_lcd_dma(void)
2324 {
2325         u16 w;
2326
2327         lcd_dma.active = 0;
2328         if (enable_1510_mode || !lcd_dma.ext_ctrl)
2329                 return;
2330
2331         w = omap_readw(OMAP1610_DMA_LCD_CCR);
2332         w &= ~(1 << 7);
2333         omap_writew(w, OMAP1610_DMA_LCD_CCR);
2334
2335         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2336         w &= ~(1 << 8);
2337         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2338 }
2339 EXPORT_SYMBOL(omap_stop_lcd_dma);
2340
2341 /*----------------------------------------------------------------------------*/
2342
2343 static int __init omap_init_dma(void)
2344 {
2345         int ch, r;
2346
2347         if (cpu_class_is_omap1()) {
2348                 omap_dma_base = IO_ADDRESS(OMAP1_DMA_BASE);
2349                 dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
2350         } else if (cpu_is_omap24xx()) {
2351                 omap_dma_base = IO_ADDRESS(OMAP24XX_DMA4_BASE);
2352                 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2353         } else if (cpu_is_omap34xx()) {
2354                 omap_dma_base = IO_ADDRESS(OMAP34XX_DMA4_BASE);
2355                 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2356         } else if (cpu_is_omap44xx()) {
2357                 omap_dma_base = IO_ADDRESS(OMAP44XX_DMA4_BASE);
2358                 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2359         } else {
2360                 pr_err("DMA init failed for unsupported omap\n");
2361                 return -ENODEV;
2362         }
2363
2364         if (cpu_class_is_omap2() && omap_dma_reserve_channels
2365                         && (omap_dma_reserve_channels <= dma_lch_count))
2366                 dma_lch_count = omap_dma_reserve_channels;
2367
2368         dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count,
2369                                 GFP_KERNEL);
2370         if (!dma_chan)
2371                 return -ENOMEM;
2372
2373         if (cpu_class_is_omap2()) {
2374                 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
2375                                                 dma_lch_count, GFP_KERNEL);
2376                 if (!dma_linked_lch) {
2377                         kfree(dma_chan);
2378                         return -ENOMEM;
2379                 }
2380         }
2381
2382         if (cpu_is_omap15xx()) {
2383                 printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
2384                 dma_chan_count = 9;
2385                 enable_1510_mode = 1;
2386         } else if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
2387                 printk(KERN_INFO "OMAP DMA hardware version %d\n",
2388                        dma_read(HW_ID));
2389                 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
2390                        (dma_read(CAPS_0_U) << 16) |
2391                        dma_read(CAPS_0_L),
2392                        (dma_read(CAPS_1_U) << 16) |
2393                        dma_read(CAPS_1_L),
2394                        dma_read(CAPS_2), dma_read(CAPS_3),
2395                        dma_read(CAPS_4));
2396                 if (!enable_1510_mode) {
2397                         u16 w;
2398
2399                         /* Disable OMAP 3.0/3.1 compatibility mode. */
2400                         w = dma_read(GSCR);
2401                         w |= 1 << 3;
2402                         dma_write(w, GSCR);
2403                         dma_chan_count = 16;
2404                 } else
2405                         dma_chan_count = 9;
2406                 if (cpu_is_omap16xx()) {
2407                         u16 w;
2408
2409                         /* this would prevent OMAP sleep */
2410                         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2411                         w &= ~(1 << 8);
2412                         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2413                 }
2414         } else if (cpu_class_is_omap2()) {
2415                 u8 revision = dma_read(REVISION) & 0xff;
2416                 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
2417                        revision >> 4, revision & 0xf);
2418                 dma_chan_count = dma_lch_count;
2419         } else {
2420                 dma_chan_count = 0;
2421                 return 0;
2422         }
2423
2424         spin_lock_init(&lcd_dma.lock);
2425         spin_lock_init(&dma_chan_lock);
2426
2427         for (ch = 0; ch < dma_chan_count; ch++) {
2428                 omap_clear_dma(ch);
2429                 dma_chan[ch].dev_id = -1;
2430                 dma_chan[ch].next_lch = -1;
2431
2432                 if (ch >= 6 && enable_1510_mode)
2433                         continue;
2434
2435                 if (cpu_class_is_omap1()) {
2436                         /*
2437                          * request_irq() doesn't like dev_id (ie. ch) being
2438                          * zero, so we have to kludge around this.
2439                          */
2440                         r = request_irq(omap1_dma_irq[ch],
2441                                         omap1_dma_irq_handler, 0, "DMA",
2442                                         (void *) (ch + 1));
2443                         if (r != 0) {
2444                                 int i;
2445
2446                                 printk(KERN_ERR "unable to request IRQ %d "
2447                                        "for DMA (error %d)\n",
2448                                        omap1_dma_irq[ch], r);
2449                                 for (i = 0; i < ch; i++)
2450                                         free_irq(omap1_dma_irq[i],
2451                                                  (void *) (i + 1));
2452                                 return r;
2453                         }
2454                 }
2455         }
2456
2457         if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx())
2458                 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
2459                                 DMA_DEFAULT_FIFO_DEPTH, 0);
2460
2461         if (cpu_class_is_omap2()) {
2462                 int irq;
2463                 if (cpu_is_omap44xx())
2464                         irq = INT_44XX_SDMA_IRQ0;
2465                 else
2466                         irq = INT_24XX_SDMA_IRQ0;
2467                 setup_irq(irq, &omap24xx_dma_irq);
2468         }
2469
2470         /* FIXME: Update LCD DMA to work on 24xx */
2471         if (cpu_class_is_omap1()) {
2472                 r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
2473                                 "LCD DMA", NULL);
2474                 if (r != 0) {
2475                         int i;
2476
2477                         printk(KERN_ERR "unable to request IRQ for LCD DMA "
2478                                "(error %d)\n", r);
2479                         for (i = 0; i < dma_chan_count; i++)
2480                                 free_irq(omap1_dma_irq[i], (void *) (i + 1));
2481                         return r;
2482                 }
2483         }
2484
2485         return 0;
2486 }
2487
2488 arch_initcall(omap_init_dma);
2489
2490 /*
2491  * Reserve the omap SDMA channels using cmdline bootarg
2492  * "omap_dma_reserve_ch=". The valid range is 1 to 32
2493  */
2494 static int __init omap_dma_cmdline_reserve_ch(char *str)
2495 {
2496         if (get_option(&str, &omap_dma_reserve_channels) != 1)
2497                 omap_dma_reserve_channels = 0;
2498         return 1;
2499 }
2500
2501 __setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch);
2502
2503