ARM: OMAP: Fix the use of uninitialized dma_lch_count
[pandora-kernel.git] / arch / arm / plat-omap / dma.c
1 /*
2  * linux/arch/arm/plat-omap/dma.c
3  *
4  * Copyright (C) 2003 - 2008 Nokia Corporation
5  * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6  * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7  * Graphics DMA and LCD DMA graphics tranformations
8  * by Imre Deak <imre.deak@nokia.com>
9  * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
10  * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
11  * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
12  *
13  * Copyright (C) 2009 Texas Instruments
14  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
15  *
16  * Support functions for the OMAP internal DMA channels.
17  *
18  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
19  * Converted DMA library into DMA platform driver.
20  *      - G, Manjunath Kondaiah <manjugk@ti.com>
21  *
22  * This program is free software; you can redistribute it and/or modify
23  * it under the terms of the GNU General Public License version 2 as
24  * published by the Free Software Foundation.
25  *
26  */
27
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/sched.h>
31 #include <linux/spinlock.h>
32 #include <linux/errno.h>
33 #include <linux/interrupt.h>
34 #include <linux/irq.h>
35 #include <linux/io.h>
36 #include <linux/slab.h>
37 #include <linux/delay.h>
38
39 #include <asm/system.h>
40 #include <mach/hardware.h>
41 #include <plat/dma.h>
42
43 #include <plat/tc.h>
44
45 #undef DEBUG
46
47 #ifndef CONFIG_ARCH_OMAP1
48 enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
49         DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
50 };
51
52 enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
53 #endif
54
55 #define OMAP_DMA_ACTIVE                 0x01
56 #define OMAP2_DMA_CSR_CLEAR_MASK        0xffffffff
57
58 #define OMAP_FUNC_MUX_ARM_BASE          (0xfffe1000 + 0xec)
59
60 static struct omap_system_dma_plat_info *p;
61 static struct omap_dma_dev_attr *d;
62
63 static int enable_1510_mode;
64 static u32 errata;
65
66 static struct omap_dma_global_context_registers {
67         u32 dma_irqenable_l0;
68         u32 dma_ocp_sysconfig;
69         u32 dma_gcr;
70 } omap_dma_global_context;
71
72 struct dma_link_info {
73         int *linked_dmach_q;
74         int no_of_lchs_linked;
75
76         int q_count;
77         int q_tail;
78         int q_head;
79
80         int chain_state;
81         int chain_mode;
82
83 };
84
85 static struct dma_link_info *dma_linked_lch;
86
87 #ifndef CONFIG_ARCH_OMAP1
88
89 /* Chain handling macros */
90 #define OMAP_DMA_CHAIN_QINIT(chain_id)                                  \
91         do {                                                            \
92                 dma_linked_lch[chain_id].q_head =                       \
93                 dma_linked_lch[chain_id].q_tail =                       \
94                 dma_linked_lch[chain_id].q_count = 0;                   \
95         } while (0)
96 #define OMAP_DMA_CHAIN_QFULL(chain_id)                                  \
97                 (dma_linked_lch[chain_id].no_of_lchs_linked ==          \
98                 dma_linked_lch[chain_id].q_count)
99 #define OMAP_DMA_CHAIN_QLAST(chain_id)                                  \
100         do {                                                            \
101                 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) ==      \
102                 dma_linked_lch[chain_id].q_count)                       \
103         } while (0)
104 #define OMAP_DMA_CHAIN_QEMPTY(chain_id)                                 \
105                 (0 == dma_linked_lch[chain_id].q_count)
106 #define __OMAP_DMA_CHAIN_INCQ(end)                                      \
107         ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
108 #define OMAP_DMA_CHAIN_INCQHEAD(chain_id)                               \
109         do {                                                            \
110                 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
111                 dma_linked_lch[chain_id].q_count--;                     \
112         } while (0)
113
114 #define OMAP_DMA_CHAIN_INCQTAIL(chain_id)                               \
115         do {                                                            \
116                 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
117                 dma_linked_lch[chain_id].q_count++; \
118         } while (0)
119 #endif
120
121 static int dma_lch_count;
122 static int dma_chan_count;
123 static int omap_dma_reserve_channels;
124
125 static spinlock_t dma_chan_lock;
126 static struct omap_dma_lch *dma_chan;
127
128 static inline void disable_lnk(int lch);
129 static void omap_disable_channel_irq(int lch);
130 static inline void omap_enable_channel_irq(int lch);
131
132 #define REVISIT_24XX()          printk(KERN_ERR "FIXME: no %s on 24xx\n", \
133                                                 __func__);
134
135 #ifdef CONFIG_ARCH_OMAP15XX
136 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
137 static int omap_dma_in_1510_mode(void)
138 {
139         return enable_1510_mode;
140 }
141 #else
142 #define omap_dma_in_1510_mode()         0
143 #endif
144
145 #ifdef CONFIG_ARCH_OMAP1
146 static inline int get_gdma_dev(int req)
147 {
148         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
149         int shift = ((req - 1) % 5) * 6;
150
151         return ((omap_readl(reg) >> shift) & 0x3f) + 1;
152 }
153
154 static inline void set_gdma_dev(int req, int dev)
155 {
156         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
157         int shift = ((req - 1) % 5) * 6;
158         u32 l;
159
160         l = omap_readl(reg);
161         l &= ~(0x3f << shift);
162         l |= (dev - 1) << shift;
163         omap_writel(l, reg);
164 }
165 #else
166 #define set_gdma_dev(req, dev)  do {} while (0)
167 #endif
168
169 void omap_set_dma_priority(int lch, int dst_port, int priority)
170 {
171         unsigned long reg;
172         u32 l;
173
174         if (cpu_class_is_omap1()) {
175                 switch (dst_port) {
176                 case OMAP_DMA_PORT_OCP_T1:      /* FFFECC00 */
177                         reg = OMAP_TC_OCPT1_PRIOR;
178                         break;
179                 case OMAP_DMA_PORT_OCP_T2:      /* FFFECCD0 */
180                         reg = OMAP_TC_OCPT2_PRIOR;
181                         break;
182                 case OMAP_DMA_PORT_EMIFF:       /* FFFECC08 */
183                         reg = OMAP_TC_EMIFF_PRIOR;
184                         break;
185                 case OMAP_DMA_PORT_EMIFS:       /* FFFECC04 */
186                         reg = OMAP_TC_EMIFS_PRIOR;
187                         break;
188                 default:
189                         BUG();
190                         return;
191                 }
192                 l = omap_readl(reg);
193                 l &= ~(0xf << 8);
194                 l |= (priority & 0xf) << 8;
195                 omap_writel(l, reg);
196         }
197
198         if (cpu_class_is_omap2()) {
199                 u32 ccr;
200
201                 ccr = p->dma_read(CCR, lch);
202                 if (priority)
203                         ccr |= (1 << 6);
204                 else
205                         ccr &= ~(1 << 6);
206                 p->dma_write(ccr, CCR, lch);
207         }
208 }
209 EXPORT_SYMBOL(omap_set_dma_priority);
210
211 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
212                                   int frame_count, int sync_mode,
213                                   int dma_trigger, int src_or_dst_synch)
214 {
215         u32 l;
216
217         l = p->dma_read(CSDP, lch);
218         l &= ~0x03;
219         l |= data_type;
220         p->dma_write(l, CSDP, lch);
221
222         if (cpu_class_is_omap1()) {
223                 u16 ccr;
224
225                 ccr = p->dma_read(CCR, lch);
226                 ccr &= ~(1 << 5);
227                 if (sync_mode == OMAP_DMA_SYNC_FRAME)
228                         ccr |= 1 << 5;
229                 p->dma_write(ccr, CCR, lch);
230
231                 ccr = p->dma_read(CCR2, lch);
232                 ccr &= ~(1 << 2);
233                 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
234                         ccr |= 1 << 2;
235                 p->dma_write(ccr, CCR2, lch);
236         }
237
238         if (cpu_class_is_omap2() && dma_trigger) {
239                 u32 val;
240
241                 val = p->dma_read(CCR, lch);
242
243                 /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
244                 val &= ~((1 << 23) | (3 << 19) | 0x1f);
245                 val |= (dma_trigger & ~0x1f) << 14;
246                 val |= dma_trigger & 0x1f;
247
248                 if (sync_mode & OMAP_DMA_SYNC_FRAME)
249                         val |= 1 << 5;
250                 else
251                         val &= ~(1 << 5);
252
253                 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
254                         val |= 1 << 18;
255                 else
256                         val &= ~(1 << 18);
257
258                 if (src_or_dst_synch == OMAP_DMA_DST_SYNC_PREFETCH) {
259                         val &= ~(1 << 24);      /* dest synch */
260                         val |= (1 << 23);       /* Prefetch */
261                 } else if (src_or_dst_synch) {
262                         val |= 1 << 24;         /* source synch */
263                 } else {
264                         val &= ~(1 << 24);      /* dest synch */
265                 }
266                 p->dma_write(val, CCR, lch);
267         }
268
269         p->dma_write(elem_count, CEN, lch);
270         p->dma_write(frame_count, CFN, lch);
271 }
272 EXPORT_SYMBOL(omap_set_dma_transfer_params);
273
274 void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
275 {
276         BUG_ON(omap_dma_in_1510_mode());
277
278         if (cpu_class_is_omap1()) {
279                 u16 w;
280
281                 w = p->dma_read(CCR2, lch);
282                 w &= ~0x03;
283
284                 switch (mode) {
285                 case OMAP_DMA_CONSTANT_FILL:
286                         w |= 0x01;
287                         break;
288                 case OMAP_DMA_TRANSPARENT_COPY:
289                         w |= 0x02;
290                         break;
291                 case OMAP_DMA_COLOR_DIS:
292                         break;
293                 default:
294                         BUG();
295                 }
296                 p->dma_write(w, CCR2, lch);
297
298                 w = p->dma_read(LCH_CTRL, lch);
299                 w &= ~0x0f;
300                 /* Default is channel type 2D */
301                 if (mode) {
302                         p->dma_write(color, COLOR, lch);
303                         w |= 1;         /* Channel type G */
304                 }
305                 p->dma_write(w, LCH_CTRL, lch);
306         }
307
308         if (cpu_class_is_omap2()) {
309                 u32 val;
310
311                 val = p->dma_read(CCR, lch);
312                 val &= ~((1 << 17) | (1 << 16));
313
314                 switch (mode) {
315                 case OMAP_DMA_CONSTANT_FILL:
316                         val |= 1 << 16;
317                         break;
318                 case OMAP_DMA_TRANSPARENT_COPY:
319                         val |= 1 << 17;
320                         break;
321                 case OMAP_DMA_COLOR_DIS:
322                         break;
323                 default:
324                         BUG();
325                 }
326                 p->dma_write(val, CCR, lch);
327
328                 color &= 0xffffff;
329                 p->dma_write(color, COLOR, lch);
330         }
331 }
332 EXPORT_SYMBOL(omap_set_dma_color_mode);
333
334 void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
335 {
336         if (cpu_class_is_omap2()) {
337                 u32 csdp;
338
339                 csdp = p->dma_read(CSDP, lch);
340                 csdp &= ~(0x3 << 16);
341                 csdp |= (mode << 16);
342                 p->dma_write(csdp, CSDP, lch);
343         }
344 }
345 EXPORT_SYMBOL(omap_set_dma_write_mode);
346
347 void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
348 {
349         if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
350                 u32 l;
351
352                 l = p->dma_read(LCH_CTRL, lch);
353                 l &= ~0x7;
354                 l |= mode;
355                 p->dma_write(l, LCH_CTRL, lch);
356         }
357 }
358 EXPORT_SYMBOL(omap_set_dma_channel_mode);
359
360 /* Note that src_port is only for omap1 */
361 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
362                              unsigned long src_start,
363                              int src_ei, int src_fi)
364 {
365         u32 l;
366
367         if (cpu_class_is_omap1()) {
368                 u16 w;
369
370                 w = p->dma_read(CSDP, lch);
371                 w &= ~(0x1f << 2);
372                 w |= src_port << 2;
373                 p->dma_write(w, CSDP, lch);
374         }
375
376         l = p->dma_read(CCR, lch);
377         l &= ~(0x03 << 12);
378         l |= src_amode << 12;
379         p->dma_write(l, CCR, lch);
380
381         p->dma_write(src_start, CSSA, lch);
382
383         p->dma_write(src_ei, CSEI, lch);
384         p->dma_write(src_fi, CSFI, lch);
385 }
386 EXPORT_SYMBOL(omap_set_dma_src_params);
387
388 void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
389 {
390         omap_set_dma_transfer_params(lch, params->data_type,
391                                      params->elem_count, params->frame_count,
392                                      params->sync_mode, params->trigger,
393                                      params->src_or_dst_synch);
394         omap_set_dma_src_params(lch, params->src_port,
395                                 params->src_amode, params->src_start,
396                                 params->src_ei, params->src_fi);
397
398         omap_set_dma_dest_params(lch, params->dst_port,
399                                  params->dst_amode, params->dst_start,
400                                  params->dst_ei, params->dst_fi);
401         if (params->read_prio || params->write_prio)
402                 omap_dma_set_prio_lch(lch, params->read_prio,
403                                       params->write_prio);
404 }
405 EXPORT_SYMBOL(omap_set_dma_params);
406
407 void omap_set_dma_src_index(int lch, int eidx, int fidx)
408 {
409         if (cpu_class_is_omap2())
410                 return;
411
412         p->dma_write(eidx, CSEI, lch);
413         p->dma_write(fidx, CSFI, lch);
414 }
415 EXPORT_SYMBOL(omap_set_dma_src_index);
416
417 void omap_set_dma_src_data_pack(int lch, int enable)
418 {
419         u32 l;
420
421         l = p->dma_read(CSDP, lch);
422         l &= ~(1 << 6);
423         if (enable)
424                 l |= (1 << 6);
425         p->dma_write(l, CSDP, lch);
426 }
427 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
428
429 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
430 {
431         unsigned int burst = 0;
432         u32 l;
433
434         l = p->dma_read(CSDP, lch);
435         l &= ~(0x03 << 7);
436
437         switch (burst_mode) {
438         case OMAP_DMA_DATA_BURST_DIS:
439                 break;
440         case OMAP_DMA_DATA_BURST_4:
441                 if (cpu_class_is_omap2())
442                         burst = 0x1;
443                 else
444                         burst = 0x2;
445                 break;
446         case OMAP_DMA_DATA_BURST_8:
447                 if (cpu_class_is_omap2()) {
448                         burst = 0x2;
449                         break;
450                 }
451                 /*
452                  * not supported by current hardware on OMAP1
453                  * w |= (0x03 << 7);
454                  * fall through
455                  */
456         case OMAP_DMA_DATA_BURST_16:
457                 if (cpu_class_is_omap2()) {
458                         burst = 0x3;
459                         break;
460                 }
461                 /*
462                  * OMAP1 don't support burst 16
463                  * fall through
464                  */
465         default:
466                 BUG();
467         }
468
469         l |= (burst << 7);
470         p->dma_write(l, CSDP, lch);
471 }
472 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
473
474 /* Note that dest_port is only for OMAP1 */
475 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
476                               unsigned long dest_start,
477                               int dst_ei, int dst_fi)
478 {
479         u32 l;
480
481         if (cpu_class_is_omap1()) {
482                 l = p->dma_read(CSDP, lch);
483                 l &= ~(0x1f << 9);
484                 l |= dest_port << 9;
485                 p->dma_write(l, CSDP, lch);
486         }
487
488         l = p->dma_read(CCR, lch);
489         l &= ~(0x03 << 14);
490         l |= dest_amode << 14;
491         p->dma_write(l, CCR, lch);
492
493         p->dma_write(dest_start, CDSA, lch);
494
495         p->dma_write(dst_ei, CDEI, lch);
496         p->dma_write(dst_fi, CDFI, lch);
497 }
498 EXPORT_SYMBOL(omap_set_dma_dest_params);
499
500 void omap_set_dma_dest_index(int lch, int eidx, int fidx)
501 {
502         if (cpu_class_is_omap2())
503                 return;
504
505         p->dma_write(eidx, CDEI, lch);
506         p->dma_write(fidx, CDFI, lch);
507 }
508 EXPORT_SYMBOL(omap_set_dma_dest_index);
509
510 void omap_set_dma_dest_data_pack(int lch, int enable)
511 {
512         u32 l;
513
514         l = p->dma_read(CSDP, lch);
515         l &= ~(1 << 13);
516         if (enable)
517                 l |= 1 << 13;
518         p->dma_write(l, CSDP, lch);
519 }
520 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
521
522 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
523 {
524         unsigned int burst = 0;
525         u32 l;
526
527         l = p->dma_read(CSDP, lch);
528         l &= ~(0x03 << 14);
529
530         switch (burst_mode) {
531         case OMAP_DMA_DATA_BURST_DIS:
532                 break;
533         case OMAP_DMA_DATA_BURST_4:
534                 if (cpu_class_is_omap2())
535                         burst = 0x1;
536                 else
537                         burst = 0x2;
538                 break;
539         case OMAP_DMA_DATA_BURST_8:
540                 if (cpu_class_is_omap2())
541                         burst = 0x2;
542                 else
543                         burst = 0x3;
544                 break;
545         case OMAP_DMA_DATA_BURST_16:
546                 if (cpu_class_is_omap2()) {
547                         burst = 0x3;
548                         break;
549                 }
550                 /*
551                  * OMAP1 don't support burst 16
552                  * fall through
553                  */
554         default:
555                 printk(KERN_ERR "Invalid DMA burst mode\n");
556                 BUG();
557                 return;
558         }
559         l |= (burst << 14);
560         p->dma_write(l, CSDP, lch);
561 }
562 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
563
564 static inline void omap_enable_channel_irq(int lch)
565 {
566         /* Clear CSR */
567         if (cpu_class_is_omap1())
568                 p->dma_read(CSR, lch);
569         else
570                 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
571
572         /* Enable some nice interrupts. */
573         p->dma_write(dma_chan[lch].enabled_irqs, CICR, lch);
574 }
575
576 static inline void omap_disable_channel_irq(int lch)
577 {
578         /* disable channel interrupts */
579         p->dma_write(0, CICR, lch);
580         /* Clear CSR */
581         if (cpu_class_is_omap1())
582                 p->dma_read(CSR, lch);
583         else
584                 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
585 }
586
587 void omap_enable_dma_irq(int lch, u16 bits)
588 {
589         dma_chan[lch].enabled_irqs |= bits;
590 }
591 EXPORT_SYMBOL(omap_enable_dma_irq);
592
593 void omap_disable_dma_irq(int lch, u16 bits)
594 {
595         dma_chan[lch].enabled_irqs &= ~bits;
596 }
597 EXPORT_SYMBOL(omap_disable_dma_irq);
598
599 static inline void enable_lnk(int lch)
600 {
601         u32 l;
602
603         l = p->dma_read(CLNK_CTRL, lch);
604
605         if (cpu_class_is_omap1())
606                 l &= ~(1 << 14);
607
608         /* Set the ENABLE_LNK bits */
609         if (dma_chan[lch].next_lch != -1)
610                 l = dma_chan[lch].next_lch | (1 << 15);
611
612 #ifndef CONFIG_ARCH_OMAP1
613         if (cpu_class_is_omap2())
614                 if (dma_chan[lch].next_linked_ch != -1)
615                         l = dma_chan[lch].next_linked_ch | (1 << 15);
616 #endif
617
618         p->dma_write(l, CLNK_CTRL, lch);
619 }
620
621 static inline void disable_lnk(int lch)
622 {
623         u32 l;
624
625         l = p->dma_read(CLNK_CTRL, lch);
626
627         /* Disable interrupts */
628         omap_disable_channel_irq(lch);
629
630         if (cpu_class_is_omap1()) {
631                 /* Set the STOP_LNK bit */
632                 l |= 1 << 14;
633         }
634
635         if (cpu_class_is_omap2()) {
636                 /* Clear the ENABLE_LNK bit */
637                 l &= ~(1 << 15);
638         }
639
640         p->dma_write(l, CLNK_CTRL, lch);
641         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
642 }
643
644 static inline void omap2_enable_irq_lch(int lch)
645 {
646         u32 val;
647         unsigned long flags;
648
649         if (!cpu_class_is_omap2())
650                 return;
651
652         spin_lock_irqsave(&dma_chan_lock, flags);
653         /* clear IRQ STATUS */
654         p->dma_write(1 << lch, IRQSTATUS_L0, lch);
655         /* Enable interrupt */
656         val = p->dma_read(IRQENABLE_L0, lch);
657         val |= 1 << lch;
658         p->dma_write(val, IRQENABLE_L0, lch);
659         spin_unlock_irqrestore(&dma_chan_lock, flags);
660 }
661
662 static inline void omap2_disable_irq_lch(int lch)
663 {
664         u32 val;
665         unsigned long flags;
666
667         if (!cpu_class_is_omap2())
668                 return;
669
670         spin_lock_irqsave(&dma_chan_lock, flags);
671         /* Disable interrupt */
672         val = p->dma_read(IRQENABLE_L0, lch);
673         val &= ~(1 << lch);
674         p->dma_write(val, IRQENABLE_L0, lch);
675         /* clear IRQ STATUS */
676         p->dma_write(1 << lch, IRQSTATUS_L0, lch);
677         spin_unlock_irqrestore(&dma_chan_lock, flags);
678 }
679
680 int omap_request_dma(int dev_id, const char *dev_name,
681                      void (*callback)(int lch, u16 ch_status, void *data),
682                      void *data, int *dma_ch_out)
683 {
684         int ch, free_ch = -1;
685         unsigned long flags;
686         struct omap_dma_lch *chan;
687
688         spin_lock_irqsave(&dma_chan_lock, flags);
689         for (ch = 0; ch < dma_chan_count; ch++) {
690                 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
691                         free_ch = ch;
692                         if (dev_id == 0)
693                                 break;
694                 }
695         }
696         if (free_ch == -1) {
697                 spin_unlock_irqrestore(&dma_chan_lock, flags);
698                 return -EBUSY;
699         }
700         chan = dma_chan + free_ch;
701         chan->dev_id = dev_id;
702
703         if (p->clear_lch_regs)
704                 p->clear_lch_regs(free_ch);
705
706         if (cpu_class_is_omap2())
707                 omap_clear_dma(free_ch);
708
709         spin_unlock_irqrestore(&dma_chan_lock, flags);
710
711         chan->dev_name = dev_name;
712         chan->callback = callback;
713         chan->data = data;
714         chan->flags = 0;
715
716 #ifndef CONFIG_ARCH_OMAP1
717         if (cpu_class_is_omap2()) {
718                 chan->chain_id = -1;
719                 chan->next_linked_ch = -1;
720         }
721 #endif
722
723         chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
724
725         if (cpu_class_is_omap1())
726                 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
727         else if (cpu_class_is_omap2())
728                 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
729                         OMAP2_DMA_TRANS_ERR_IRQ;
730
731         if (cpu_is_omap16xx()) {
732                 /* If the sync device is set, configure it dynamically. */
733                 if (dev_id != 0) {
734                         set_gdma_dev(free_ch + 1, dev_id);
735                         dev_id = free_ch + 1;
736                 }
737                 /*
738                  * Disable the 1510 compatibility mode and set the sync device
739                  * id.
740                  */
741                 p->dma_write(dev_id | (1 << 10), CCR, free_ch);
742         } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) {
743                 p->dma_write(dev_id, CCR, free_ch);
744         }
745
746         if (cpu_class_is_omap2()) {
747                 omap_enable_channel_irq(free_ch);
748                 omap2_enable_irq_lch(free_ch);
749         }
750
751         *dma_ch_out = free_ch;
752
753         return 0;
754 }
755 EXPORT_SYMBOL(omap_request_dma);
756
757 void omap_free_dma(int lch)
758 {
759         unsigned long flags;
760
761         if (dma_chan[lch].dev_id == -1) {
762                 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
763                        lch);
764                 return;
765         }
766
767         /* Disable interrupt for logical channel */
768         if (cpu_class_is_omap2())
769                 omap2_disable_irq_lch(lch);
770
771         /* Disable all DMA interrupts for the channel. */
772         omap_disable_channel_irq(lch);
773
774         /* Make sure the DMA transfer is stopped. */
775         p->dma_write(0, CCR, lch);
776
777         /* Clear registers */
778         if (cpu_class_is_omap2())
779                 omap_clear_dma(lch);
780
781         spin_lock_irqsave(&dma_chan_lock, flags);
782         dma_chan[lch].dev_id = -1;
783         dma_chan[lch].next_lch = -1;
784         dma_chan[lch].callback = NULL;
785         spin_unlock_irqrestore(&dma_chan_lock, flags);
786 }
787 EXPORT_SYMBOL(omap_free_dma);
788
789 /**
790  * @brief omap_dma_set_global_params : Set global priority settings for dma
791  *
792  * @param arb_rate
793  * @param max_fifo_depth
794  * @param tparams - Number of threads to reserve : DMA_THREAD_RESERVE_NORM
795  *                                                 DMA_THREAD_RESERVE_ONET
796  *                                                 DMA_THREAD_RESERVE_TWOT
797  *                                                 DMA_THREAD_RESERVE_THREET
798  */
799 void
800 omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
801 {
802         u32 reg;
803
804         if (!cpu_class_is_omap2()) {
805                 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
806                 return;
807         }
808
809         if (max_fifo_depth == 0)
810                 max_fifo_depth = 1;
811         if (arb_rate == 0)
812                 arb_rate = 1;
813
814         reg = 0xff & max_fifo_depth;
815         reg |= (0x3 & tparams) << 12;
816         reg |= (arb_rate & 0xff) << 16;
817
818         p->dma_write(reg, GCR, 0);
819 }
820 EXPORT_SYMBOL(omap_dma_set_global_params);
821
822 /**
823  * @brief omap_dma_set_prio_lch : Set channel wise priority settings
824  *
825  * @param lch
826  * @param read_prio - Read priority
827  * @param write_prio - Write priority
828  * Both of the above can be set with one of the following values :
829  *      DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
830  */
831 int
832 omap_dma_set_prio_lch(int lch, unsigned char read_prio,
833                       unsigned char write_prio)
834 {
835         u32 l;
836
837         if (unlikely((lch < 0 || lch >= dma_lch_count))) {
838                 printk(KERN_ERR "Invalid channel id\n");
839                 return -EINVAL;
840         }
841         l = p->dma_read(CCR, lch);
842         l &= ~((1 << 6) | (1 << 26));
843         if (cpu_is_omap2430() || cpu_is_omap34xx() ||  cpu_is_omap44xx())
844                 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
845         else
846                 l |= ((read_prio & 0x1) << 6);
847
848         p->dma_write(l, CCR, lch);
849
850         return 0;
851 }
852 EXPORT_SYMBOL(omap_dma_set_prio_lch);
853
854 /*
855  * Clears any DMA state so the DMA engine is ready to restart with new buffers
856  * through omap_start_dma(). Any buffers in flight are discarded.
857  */
858 void omap_clear_dma(int lch)
859 {
860         unsigned long flags;
861
862         local_irq_save(flags);
863         p->clear_dma(lch);
864         local_irq_restore(flags);
865 }
866 EXPORT_SYMBOL(omap_clear_dma);
867
868 void omap_start_dma(int lch)
869 {
870         u32 l;
871
872         /*
873          * The CPC/CDAC register needs to be initialized to zero
874          * before starting dma transfer.
875          */
876         if (cpu_is_omap15xx())
877                 p->dma_write(0, CPC, lch);
878         else
879                 p->dma_write(0, CDAC, lch);
880
881         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
882                 int next_lch, cur_lch;
883                 char dma_chan_link_map[dma_lch_count];
884
885                 dma_chan_link_map[lch] = 1;
886                 /* Set the link register of the first channel */
887                 enable_lnk(lch);
888
889                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
890                 cur_lch = dma_chan[lch].next_lch;
891                 do {
892                         next_lch = dma_chan[cur_lch].next_lch;
893
894                         /* The loop case: we've been here already */
895                         if (dma_chan_link_map[cur_lch])
896                                 break;
897                         /* Mark the current channel */
898                         dma_chan_link_map[cur_lch] = 1;
899
900                         enable_lnk(cur_lch);
901                         omap_enable_channel_irq(cur_lch);
902
903                         cur_lch = next_lch;
904                 } while (next_lch != -1);
905         } else if (IS_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS))
906                 p->dma_write(lch, CLNK_CTRL, lch);
907
908         omap_enable_channel_irq(lch);
909
910         l = p->dma_read(CCR, lch);
911
912         if (IS_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING))
913                         l |= OMAP_DMA_CCR_BUFFERING_DISABLE;
914         l |= OMAP_DMA_CCR_EN;
915
916         /*
917          * As dma_write() uses IO accessors which are weakly ordered, there
918          * is no guarantee that data in coherent DMA memory will be visible
919          * to the DMA device.  Add a memory barrier here to ensure that any
920          * such data is visible prior to enabling DMA.
921          */
922         mb();
923         p->dma_write(l, CCR, lch);
924
925         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
926 }
927 EXPORT_SYMBOL(omap_start_dma);
928
929 void omap_stop_dma(int lch)
930 {
931         u32 l;
932
933         /* Disable all interrupts on the channel */
934         omap_disable_channel_irq(lch);
935
936         l = p->dma_read(CCR, lch);
937         if (IS_DMA_ERRATA(DMA_ERRATA_i541) &&
938                         (l & OMAP_DMA_CCR_SEL_SRC_DST_SYNC)) {
939                 int i = 0;
940                 u32 sys_cf;
941
942                 /* Configure No-Standby */
943                 l = p->dma_read(OCP_SYSCONFIG, lch);
944                 sys_cf = l;
945                 l &= ~DMA_SYSCONFIG_MIDLEMODE_MASK;
946                 l |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE);
947                 p->dma_write(l , OCP_SYSCONFIG, 0);
948
949                 l = p->dma_read(CCR, lch);
950                 l &= ~OMAP_DMA_CCR_EN;
951                 p->dma_write(l, CCR, lch);
952
953                 /* Wait for sDMA FIFO drain */
954                 l = p->dma_read(CCR, lch);
955                 while (i < 100 && (l & (OMAP_DMA_CCR_RD_ACTIVE |
956                                         OMAP_DMA_CCR_WR_ACTIVE))) {
957                         udelay(5);
958                         i++;
959                         l = p->dma_read(CCR, lch);
960                 }
961                 if (i >= 100)
962                         printk(KERN_ERR "DMA drain did not complete on "
963                                         "lch %d\n", lch);
964                 /* Restore OCP_SYSCONFIG */
965                 p->dma_write(sys_cf, OCP_SYSCONFIG, lch);
966         } else {
967                 l &= ~OMAP_DMA_CCR_EN;
968                 p->dma_write(l, CCR, lch);
969         }
970
971         /*
972          * Ensure that data transferred by DMA is visible to any access
973          * after DMA has been disabled.  This is important for coherent
974          * DMA regions.
975          */
976         mb();
977
978         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
979                 int next_lch, cur_lch = lch;
980                 char dma_chan_link_map[dma_lch_count];
981
982                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
983                 do {
984                         /* The loop case: we've been here already */
985                         if (dma_chan_link_map[cur_lch])
986                                 break;
987                         /* Mark the current channel */
988                         dma_chan_link_map[cur_lch] = 1;
989
990                         disable_lnk(cur_lch);
991
992                         next_lch = dma_chan[cur_lch].next_lch;
993                         cur_lch = next_lch;
994                 } while (next_lch != -1);
995         }
996
997         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
998 }
999 EXPORT_SYMBOL(omap_stop_dma);
1000
1001 /*
1002  * Allows changing the DMA callback function or data. This may be needed if
1003  * the driver shares a single DMA channel for multiple dma triggers.
1004  */
1005 int omap_set_dma_callback(int lch,
1006                           void (*callback)(int lch, u16 ch_status, void *data),
1007                           void *data)
1008 {
1009         unsigned long flags;
1010
1011         if (lch < 0)
1012                 return -ENODEV;
1013
1014         spin_lock_irqsave(&dma_chan_lock, flags);
1015         if (dma_chan[lch].dev_id == -1) {
1016                 printk(KERN_ERR "DMA callback for not set for free channel\n");
1017                 spin_unlock_irqrestore(&dma_chan_lock, flags);
1018                 return -EINVAL;
1019         }
1020         dma_chan[lch].callback = callback;
1021         dma_chan[lch].data = data;
1022         spin_unlock_irqrestore(&dma_chan_lock, flags);
1023
1024         return 0;
1025 }
1026 EXPORT_SYMBOL(omap_set_dma_callback);
1027
1028 /*
1029  * Returns current physical source address for the given DMA channel.
1030  * If the channel is running the caller must disable interrupts prior calling
1031  * this function and process the returned value before re-enabling interrupt to
1032  * prevent races with the interrupt handler. Note that in continuous mode there
1033  * is a chance for CSSA_L register overflow between the two reads resulting
1034  * in incorrect return value.
1035  */
1036 dma_addr_t omap_get_dma_src_pos(int lch)
1037 {
1038         dma_addr_t offset = 0;
1039
1040         if (cpu_is_omap15xx())
1041                 offset = p->dma_read(CPC, lch);
1042         else
1043                 offset = p->dma_read(CSAC, lch);
1044
1045         if (IS_DMA_ERRATA(DMA_ERRATA_3_3) && offset == 0)
1046                 offset = p->dma_read(CSAC, lch);
1047
1048         if (!cpu_is_omap15xx()) {
1049                 /*
1050                  * CDAC == 0 indicates that the DMA transfer on the channel has
1051                  * not been started (no data has been transferred so far).
1052                  * Return the programmed source start address in this case.
1053                  */
1054                 if (likely(p->dma_read(CDAC, lch)))
1055                         offset = p->dma_read(CSAC, lch);
1056                 else
1057                         offset = p->dma_read(CSSA, lch);
1058         }
1059
1060         if (cpu_class_is_omap1())
1061                 offset |= (p->dma_read(CSSA, lch) & 0xFFFF0000);
1062
1063         return offset;
1064 }
1065 EXPORT_SYMBOL(omap_get_dma_src_pos);
1066
1067 /*
1068  * Returns current physical destination address for the given DMA channel.
1069  * If the channel is running the caller must disable interrupts prior calling
1070  * this function and process the returned value before re-enabling interrupt to
1071  * prevent races with the interrupt handler. Note that in continuous mode there
1072  * is a chance for CDSA_L register overflow between the two reads resulting
1073  * in incorrect return value.
1074  */
1075 dma_addr_t omap_get_dma_dst_pos(int lch)
1076 {
1077         dma_addr_t offset = 0;
1078
1079         if (cpu_is_omap15xx())
1080                 offset = p->dma_read(CPC, lch);
1081         else
1082                 offset = p->dma_read(CDAC, lch);
1083
1084         /*
1085          * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1086          * read before the DMA controller finished disabling the channel.
1087          */
1088         if (!cpu_is_omap15xx() && offset == 0) {
1089                 offset = p->dma_read(CDAC, lch);
1090                 /*
1091                  * CDAC == 0 indicates that the DMA transfer on the channel has
1092                  * not been started (no data has been transferred so far).
1093                  * Return the programmed destination start address in this case.
1094                  */
1095                 if (unlikely(!offset))
1096                         offset = p->dma_read(CDSA, lch);
1097         }
1098
1099         if (cpu_class_is_omap1())
1100                 offset |= (p->dma_read(CDSA, lch) & 0xFFFF0000);
1101
1102         return offset;
1103 }
1104 EXPORT_SYMBOL(omap_get_dma_dst_pos);
1105
1106 int omap_get_dma_active_status(int lch)
1107 {
1108         return (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN) != 0;
1109 }
1110 EXPORT_SYMBOL(omap_get_dma_active_status);
1111
1112 int omap_dma_running(void)
1113 {
1114         int lch;
1115
1116         if (cpu_class_is_omap1())
1117                 if (omap_lcd_dma_running())
1118                         return 1;
1119
1120         for (lch = 0; lch < dma_chan_count; lch++)
1121                 if (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN)
1122                         return 1;
1123
1124         return 0;
1125 }
1126
1127 /*
1128  * lch_queue DMA will start right after lch_head one is finished.
1129  * For this DMA link to start, you still need to start (see omap_start_dma)
1130  * the first one. That will fire up the entire queue.
1131  */
1132 void omap_dma_link_lch(int lch_head, int lch_queue)
1133 {
1134         if (omap_dma_in_1510_mode()) {
1135                 if (lch_head == lch_queue) {
1136                         p->dma_write(p->dma_read(CCR, lch_head) | (3 << 8),
1137                                                                 CCR, lch_head);
1138                         return;
1139                 }
1140                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1141                 BUG();
1142                 return;
1143         }
1144
1145         if ((dma_chan[lch_head].dev_id == -1) ||
1146             (dma_chan[lch_queue].dev_id == -1)) {
1147                 printk(KERN_ERR "omap_dma: trying to link "
1148                        "non requested channels\n");
1149                 dump_stack();
1150         }
1151
1152         dma_chan[lch_head].next_lch = lch_queue;
1153 }
1154 EXPORT_SYMBOL(omap_dma_link_lch);
1155
1156 /*
1157  * Once the DMA queue is stopped, we can destroy it.
1158  */
1159 void omap_dma_unlink_lch(int lch_head, int lch_queue)
1160 {
1161         if (omap_dma_in_1510_mode()) {
1162                 if (lch_head == lch_queue) {
1163                         p->dma_write(p->dma_read(CCR, lch_head) & ~(3 << 8),
1164                                                                 CCR, lch_head);
1165                         return;
1166                 }
1167                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1168                 BUG();
1169                 return;
1170         }
1171
1172         if (dma_chan[lch_head].next_lch != lch_queue ||
1173             dma_chan[lch_head].next_lch == -1) {
1174                 printk(KERN_ERR "omap_dma: trying to unlink "
1175                        "non linked channels\n");
1176                 dump_stack();
1177         }
1178
1179         if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
1180             (dma_chan[lch_queue].flags & OMAP_DMA_ACTIVE)) {
1181                 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
1182                        "before unlinking\n");
1183                 dump_stack();
1184         }
1185
1186         dma_chan[lch_head].next_lch = -1;
1187 }
1188 EXPORT_SYMBOL(omap_dma_unlink_lch);
1189
1190 #ifndef CONFIG_ARCH_OMAP1
1191 /* Create chain of DMA channesls */
1192 static void create_dma_lch_chain(int lch_head, int lch_queue)
1193 {
1194         u32 l;
1195
1196         /* Check if this is the first link in chain */
1197         if (dma_chan[lch_head].next_linked_ch == -1) {
1198                 dma_chan[lch_head].next_linked_ch = lch_queue;
1199                 dma_chan[lch_head].prev_linked_ch = lch_queue;
1200                 dma_chan[lch_queue].next_linked_ch = lch_head;
1201                 dma_chan[lch_queue].prev_linked_ch = lch_head;
1202         }
1203
1204         /* a link exists, link the new channel in circular chain */
1205         else {
1206                 dma_chan[lch_queue].next_linked_ch =
1207                                         dma_chan[lch_head].next_linked_ch;
1208                 dma_chan[lch_queue].prev_linked_ch = lch_head;
1209                 dma_chan[lch_head].next_linked_ch = lch_queue;
1210                 dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
1211                                         lch_queue;
1212         }
1213
1214         l = p->dma_read(CLNK_CTRL, lch_head);
1215         l &= ~(0x1f);
1216         l |= lch_queue;
1217         p->dma_write(l, CLNK_CTRL, lch_head);
1218
1219         l = p->dma_read(CLNK_CTRL, lch_queue);
1220         l &= ~(0x1f);
1221         l |= (dma_chan[lch_queue].next_linked_ch);
1222         p->dma_write(l, CLNK_CTRL, lch_queue);
1223 }
1224
1225 /**
1226  * @brief omap_request_dma_chain : Request a chain of DMA channels
1227  *
1228  * @param dev_id - Device id using the dma channel
1229  * @param dev_name - Device name
1230  * @param callback - Call back function
1231  * @chain_id -
1232  * @no_of_chans - Number of channels requested
1233  * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1234  *                                            OMAP_DMA_DYNAMIC_CHAIN
1235  * @params - Channel parameters
1236  *
1237  * @return - Success : 0
1238  *           Failure: -EINVAL/-ENOMEM
1239  */
1240 int omap_request_dma_chain(int dev_id, const char *dev_name,
1241                            void (*callback) (int lch, u16 ch_status,
1242                                              void *data),
1243                            int *chain_id, int no_of_chans, int chain_mode,
1244                            struct omap_dma_channel_params params)
1245 {
1246         int *channels;
1247         int i, err;
1248
1249         /* Is the chain mode valid ? */
1250         if (chain_mode != OMAP_DMA_STATIC_CHAIN
1251                         && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
1252                 printk(KERN_ERR "Invalid chain mode requested\n");
1253                 return -EINVAL;
1254         }
1255
1256         if (unlikely((no_of_chans < 1
1257                         || no_of_chans > dma_lch_count))) {
1258                 printk(KERN_ERR "Invalid Number of channels requested\n");
1259                 return -EINVAL;
1260         }
1261
1262         /*
1263          * Allocate a queue to maintain the status of the channels
1264          * in the chain
1265          */
1266         channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
1267         if (channels == NULL) {
1268                 printk(KERN_ERR "omap_dma: No memory for channel queue\n");
1269                 return -ENOMEM;
1270         }
1271
1272         /* request and reserve DMA channels for the chain */
1273         for (i = 0; i < no_of_chans; i++) {
1274                 err = omap_request_dma(dev_id, dev_name,
1275                                         callback, NULL, &channels[i]);
1276                 if (err < 0) {
1277                         int j;
1278                         for (j = 0; j < i; j++)
1279                                 omap_free_dma(channels[j]);
1280                         kfree(channels);
1281                         printk(KERN_ERR "omap_dma: Request failed %d\n", err);
1282                         return err;
1283                 }
1284                 dma_chan[channels[i]].prev_linked_ch = -1;
1285                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1286
1287                 /*
1288                  * Allowing client drivers to set common parameters now,
1289                  * so that later only relevant (src_start, dest_start
1290                  * and element count) can be set
1291                  */
1292                 omap_set_dma_params(channels[i], &params);
1293         }
1294
1295         *chain_id = channels[0];
1296         dma_linked_lch[*chain_id].linked_dmach_q = channels;
1297         dma_linked_lch[*chain_id].chain_mode = chain_mode;
1298         dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1299         dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;
1300
1301         for (i = 0; i < no_of_chans; i++)
1302                 dma_chan[channels[i]].chain_id = *chain_id;
1303
1304         /* Reset the Queue pointers */
1305         OMAP_DMA_CHAIN_QINIT(*chain_id);
1306
1307         /* Set up the chain */
1308         if (no_of_chans == 1)
1309                 create_dma_lch_chain(channels[0], channels[0]);
1310         else {
1311                 for (i = 0; i < (no_of_chans - 1); i++)
1312                         create_dma_lch_chain(channels[i], channels[i + 1]);
1313         }
1314
1315         return 0;
1316 }
1317 EXPORT_SYMBOL(omap_request_dma_chain);
1318
1319 /**
1320  * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1321  * params after setting it. Dont do this while dma is running!!
1322  *
1323  * @param chain_id - Chained logical channel id.
1324  * @param params
1325  *
1326  * @return - Success : 0
1327  *           Failure : -EINVAL
1328  */
1329 int omap_modify_dma_chain_params(int chain_id,
1330                                 struct omap_dma_channel_params params)
1331 {
1332         int *channels;
1333         u32 i;
1334
1335         /* Check for input params */
1336         if (unlikely((chain_id < 0
1337                         || chain_id >= dma_lch_count))) {
1338                 printk(KERN_ERR "Invalid chain id\n");
1339                 return -EINVAL;
1340         }
1341
1342         /* Check if the chain exists */
1343         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1344                 printk(KERN_ERR "Chain doesn't exists\n");
1345                 return -EINVAL;
1346         }
1347         channels = dma_linked_lch[chain_id].linked_dmach_q;
1348
1349         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1350                 /*
1351                  * Allowing client drivers to set common parameters now,
1352                  * so that later only relevant (src_start, dest_start
1353                  * and element count) can be set
1354                  */
1355                 omap_set_dma_params(channels[i], &params);
1356         }
1357
1358         return 0;
1359 }
1360 EXPORT_SYMBOL(omap_modify_dma_chain_params);
1361
1362 /**
1363  * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1364  *
1365  * @param chain_id
1366  *
1367  * @return - Success : 0
1368  *           Failure : -EINVAL
1369  */
1370 int omap_free_dma_chain(int chain_id)
1371 {
1372         int *channels;
1373         u32 i;
1374
1375         /* Check for input params */
1376         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1377                 printk(KERN_ERR "Invalid chain id\n");
1378                 return -EINVAL;
1379         }
1380
1381         /* Check if the chain exists */
1382         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1383                 printk(KERN_ERR "Chain doesn't exists\n");
1384                 return -EINVAL;
1385         }
1386
1387         channels = dma_linked_lch[chain_id].linked_dmach_q;
1388         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1389                 dma_chan[channels[i]].next_linked_ch = -1;
1390                 dma_chan[channels[i]].prev_linked_ch = -1;
1391                 dma_chan[channels[i]].chain_id = -1;
1392                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1393                 omap_free_dma(channels[i]);
1394         }
1395
1396         kfree(channels);
1397
1398         dma_linked_lch[chain_id].linked_dmach_q = NULL;
1399         dma_linked_lch[chain_id].chain_mode = -1;
1400         dma_linked_lch[chain_id].chain_state = -1;
1401
1402         return (0);
1403 }
1404 EXPORT_SYMBOL(omap_free_dma_chain);
1405
1406 /**
1407  * @brief omap_dma_chain_status - Check if the chain is in
1408  * active / inactive state.
1409  * @param chain_id
1410  *
1411  * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1412  *           Failure : -EINVAL
1413  */
1414 int omap_dma_chain_status(int chain_id)
1415 {
1416         /* Check for input params */
1417         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1418                 printk(KERN_ERR "Invalid chain id\n");
1419                 return -EINVAL;
1420         }
1421
1422         /* Check if the chain exists */
1423         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1424                 printk(KERN_ERR "Chain doesn't exists\n");
1425                 return -EINVAL;
1426         }
1427         pr_debug("CHAINID=%d, qcnt=%d\n", chain_id,
1428                         dma_linked_lch[chain_id].q_count);
1429
1430         if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
1431                 return OMAP_DMA_CHAIN_INACTIVE;
1432
1433         return OMAP_DMA_CHAIN_ACTIVE;
1434 }
1435 EXPORT_SYMBOL(omap_dma_chain_status);
1436
1437 /**
1438  * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1439  * set the params and start the transfer.
1440  *
1441  * @param chain_id
1442  * @param src_start - buffer start address
1443  * @param dest_start - Dest address
1444  * @param elem_count
1445  * @param frame_count
1446  * @param callbk_data - channel callback parameter data.
1447  *
1448  * @return  - Success : 0
1449  *            Failure: -EINVAL/-EBUSY
1450  */
1451 int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1452                         int elem_count, int frame_count, void *callbk_data)
1453 {
1454         int *channels;
1455         u32 l, lch;
1456         int start_dma = 0;
1457
1458         /*
1459          * if buffer size is less than 1 then there is
1460          * no use of starting the chain
1461          */
1462         if (elem_count < 1) {
1463                 printk(KERN_ERR "Invalid buffer size\n");
1464                 return -EINVAL;
1465         }
1466
1467         /* Check for input params */
1468         if (unlikely((chain_id < 0
1469                         || chain_id >= dma_lch_count))) {
1470                 printk(KERN_ERR "Invalid chain id\n");
1471                 return -EINVAL;
1472         }
1473
1474         /* Check if the chain exists */
1475         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1476                 printk(KERN_ERR "Chain doesn't exist\n");
1477                 return -EINVAL;
1478         }
1479
1480         /* Check if all the channels in chain are in use */
1481         if (OMAP_DMA_CHAIN_QFULL(chain_id))
1482                 return -EBUSY;
1483
1484         /* Frame count may be negative in case of indexed transfers */
1485         channels = dma_linked_lch[chain_id].linked_dmach_q;
1486
1487         /* Get a free channel */
1488         lch = channels[dma_linked_lch[chain_id].q_tail];
1489
1490         /* Store the callback data */
1491         dma_chan[lch].data = callbk_data;
1492
1493         /* Increment the q_tail */
1494         OMAP_DMA_CHAIN_INCQTAIL(chain_id);
1495
1496         /* Set the params to the free channel */
1497         if (src_start != 0)
1498                 p->dma_write(src_start, CSSA, lch);
1499         if (dest_start != 0)
1500                 p->dma_write(dest_start, CDSA, lch);
1501
1502         /* Write the buffer size */
1503         p->dma_write(elem_count, CEN, lch);
1504         p->dma_write(frame_count, CFN, lch);
1505
1506         /*
1507          * If the chain is dynamically linked,
1508          * then we may have to start the chain if its not active
1509          */
1510         if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
1511
1512                 /*
1513                  * In Dynamic chain, if the chain is not started,
1514                  * queue the channel
1515                  */
1516                 if (dma_linked_lch[chain_id].chain_state ==
1517                                                 DMA_CHAIN_NOTSTARTED) {
1518                         /* Enable the link in previous channel */
1519                         if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1520                                                                 DMA_CH_QUEUED)
1521                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1522                         dma_chan[lch].state = DMA_CH_QUEUED;
1523                 }
1524
1525                 /*
1526                  * Chain is already started, make sure its active,
1527                  * if not then start the chain
1528                  */
1529                 else {
1530                         start_dma = 1;
1531
1532                         if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1533                                                         DMA_CH_STARTED) {
1534                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1535                                 dma_chan[lch].state = DMA_CH_QUEUED;
1536                                 start_dma = 0;
1537                                 if (0 == ((1 << 7) & p->dma_read(
1538                                         CCR, dma_chan[lch].prev_linked_ch))) {
1539                                         disable_lnk(dma_chan[lch].
1540                                                     prev_linked_ch);
1541                                         pr_debug("\n prev ch is stopped\n");
1542                                         start_dma = 1;
1543                                 }
1544                         }
1545
1546                         else if (dma_chan[dma_chan[lch].prev_linked_ch].state
1547                                                         == DMA_CH_QUEUED) {
1548                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1549                                 dma_chan[lch].state = DMA_CH_QUEUED;
1550                                 start_dma = 0;
1551                         }
1552                         omap_enable_channel_irq(lch);
1553
1554                         l = p->dma_read(CCR, lch);
1555
1556                         if ((0 == (l & (1 << 24))))
1557                                 l &= ~(1 << 25);
1558                         else
1559                                 l |= (1 << 25);
1560                         if (start_dma == 1) {
1561                                 if (0 == (l & (1 << 7))) {
1562                                         l |= (1 << 7);
1563                                         dma_chan[lch].state = DMA_CH_STARTED;
1564                                         pr_debug("starting %d\n", lch);
1565                                         p->dma_write(l, CCR, lch);
1566                                 } else
1567                                         start_dma = 0;
1568                         } else {
1569                                 if (0 == (l & (1 << 7)))
1570                                         p->dma_write(l, CCR, lch);
1571                         }
1572                         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1573                 }
1574         }
1575
1576         return 0;
1577 }
1578 EXPORT_SYMBOL(omap_dma_chain_a_transfer);
1579
1580 /**
1581  * @brief omap_start_dma_chain_transfers - Start the chain
1582  *
1583  * @param chain_id
1584  *
1585  * @return - Success : 0
1586  *           Failure : -EINVAL/-EBUSY
1587  */
1588 int omap_start_dma_chain_transfers(int chain_id)
1589 {
1590         int *channels;
1591         u32 l, i;
1592
1593         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1594                 printk(KERN_ERR "Invalid chain id\n");
1595                 return -EINVAL;
1596         }
1597
1598         channels = dma_linked_lch[chain_id].linked_dmach_q;
1599
1600         if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
1601                 printk(KERN_ERR "Chain is already started\n");
1602                 return -EBUSY;
1603         }
1604
1605         if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
1606                 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
1607                                                                         i++) {
1608                         enable_lnk(channels[i]);
1609                         omap_enable_channel_irq(channels[i]);
1610                 }
1611         } else {
1612                 omap_enable_channel_irq(channels[0]);
1613         }
1614
1615         l = p->dma_read(CCR, channels[0]);
1616         l |= (1 << 7);
1617         dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
1618         dma_chan[channels[0]].state = DMA_CH_STARTED;
1619
1620         if ((0 == (l & (1 << 24))))
1621                 l &= ~(1 << 25);
1622         else
1623                 l |= (1 << 25);
1624         p->dma_write(l, CCR, channels[0]);
1625
1626         dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
1627
1628         return 0;
1629 }
1630 EXPORT_SYMBOL(omap_start_dma_chain_transfers);
1631
1632 /**
1633  * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1634  *
1635  * @param chain_id
1636  *
1637  * @return - Success : 0
1638  *           Failure : EINVAL
1639  */
1640 int omap_stop_dma_chain_transfers(int chain_id)
1641 {
1642         int *channels;
1643         u32 l, i;
1644         u32 sys_cf = 0;
1645
1646         /* Check for input params */
1647         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1648                 printk(KERN_ERR "Invalid chain id\n");
1649                 return -EINVAL;
1650         }
1651
1652         /* Check if the chain exists */
1653         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1654                 printk(KERN_ERR "Chain doesn't exists\n");
1655                 return -EINVAL;
1656         }
1657         channels = dma_linked_lch[chain_id].linked_dmach_q;
1658
1659         if (IS_DMA_ERRATA(DMA_ERRATA_i88)) {
1660                 sys_cf = p->dma_read(OCP_SYSCONFIG, 0);
1661                 l = sys_cf;
1662                 /* Middle mode reg set no Standby */
1663                 l &= ~((1 << 12)|(1 << 13));
1664                 p->dma_write(l, OCP_SYSCONFIG, 0);
1665         }
1666
1667         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1668
1669                 /* Stop the Channel transmission */
1670                 l = p->dma_read(CCR, channels[i]);
1671                 l &= ~(1 << 7);
1672                 p->dma_write(l, CCR, channels[i]);
1673
1674                 /* Disable the link in all the channels */
1675                 disable_lnk(channels[i]);
1676                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1677
1678         }
1679         dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1680
1681         /* Reset the Queue pointers */
1682         OMAP_DMA_CHAIN_QINIT(chain_id);
1683
1684         if (IS_DMA_ERRATA(DMA_ERRATA_i88))
1685                 p->dma_write(sys_cf, OCP_SYSCONFIG, 0);
1686
1687         return 0;
1688 }
1689 EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
1690
1691 /* Get the index of the ongoing DMA in chain */
1692 /**
1693  * @brief omap_get_dma_chain_index - Get the element and frame index
1694  * of the ongoing DMA in chain
1695  *
1696  * @param chain_id
1697  * @param ei - Element index
1698  * @param fi - Frame index
1699  *
1700  * @return - Success : 0
1701  *           Failure : -EINVAL
1702  */
1703 int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1704 {
1705         int lch;
1706         int *channels;
1707
1708         /* Check for input params */
1709         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1710                 printk(KERN_ERR "Invalid chain id\n");
1711                 return -EINVAL;
1712         }
1713
1714         /* Check if the chain exists */
1715         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1716                 printk(KERN_ERR "Chain doesn't exists\n");
1717                 return -EINVAL;
1718         }
1719         if ((!ei) || (!fi))
1720                 return -EINVAL;
1721
1722         channels = dma_linked_lch[chain_id].linked_dmach_q;
1723
1724         /* Get the current channel */
1725         lch = channels[dma_linked_lch[chain_id].q_head];
1726
1727         *ei = p->dma_read(CCEN, lch);
1728         *fi = p->dma_read(CCFN, lch);
1729
1730         return 0;
1731 }
1732 EXPORT_SYMBOL(omap_get_dma_chain_index);
1733
1734 /**
1735  * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1736  * ongoing DMA in chain
1737  *
1738  * @param chain_id
1739  *
1740  * @return - Success : Destination position
1741  *           Failure : -EINVAL
1742  */
1743 int omap_get_dma_chain_dst_pos(int chain_id)
1744 {
1745         int lch;
1746         int *channels;
1747
1748         /* Check for input params */
1749         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1750                 printk(KERN_ERR "Invalid chain id\n");
1751                 return -EINVAL;
1752         }
1753
1754         /* Check if the chain exists */
1755         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1756                 printk(KERN_ERR "Chain doesn't exists\n");
1757                 return -EINVAL;
1758         }
1759
1760         channels = dma_linked_lch[chain_id].linked_dmach_q;
1761
1762         /* Get the current channel */
1763         lch = channels[dma_linked_lch[chain_id].q_head];
1764
1765         return p->dma_read(CDAC, lch);
1766 }
1767 EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
1768
1769 /**
1770  * @brief omap_get_dma_chain_src_pos - Get the source position
1771  * of the ongoing DMA in chain
1772  * @param chain_id
1773  *
1774  * @return - Success : Destination position
1775  *           Failure : -EINVAL
1776  */
1777 int omap_get_dma_chain_src_pos(int chain_id)
1778 {
1779         int lch;
1780         int *channels;
1781
1782         /* Check for input params */
1783         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1784                 printk(KERN_ERR "Invalid chain id\n");
1785                 return -EINVAL;
1786         }
1787
1788         /* Check if the chain exists */
1789         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1790                 printk(KERN_ERR "Chain doesn't exists\n");
1791                 return -EINVAL;
1792         }
1793
1794         channels = dma_linked_lch[chain_id].linked_dmach_q;
1795
1796         /* Get the current channel */
1797         lch = channels[dma_linked_lch[chain_id].q_head];
1798
1799         return p->dma_read(CSAC, lch);
1800 }
1801 EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
1802 #endif  /* ifndef CONFIG_ARCH_OMAP1 */
1803
1804 /*----------------------------------------------------------------------------*/
1805
1806 #ifdef CONFIG_ARCH_OMAP1
1807
1808 static int omap1_dma_handle_ch(int ch)
1809 {
1810         u32 csr;
1811
1812         if (enable_1510_mode && ch >= 6) {
1813                 csr = dma_chan[ch].saved_csr;
1814                 dma_chan[ch].saved_csr = 0;
1815         } else
1816                 csr = p->dma_read(CSR, ch);
1817         if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1818                 dma_chan[ch + 6].saved_csr = csr >> 7;
1819                 csr &= 0x7f;
1820         }
1821         if ((csr & 0x3f) == 0)
1822                 return 0;
1823         if (unlikely(dma_chan[ch].dev_id == -1)) {
1824                 printk(KERN_WARNING "Spurious interrupt from DMA channel "
1825                        "%d (CSR %04x)\n", ch, csr);
1826                 return 0;
1827         }
1828         if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
1829                 printk(KERN_WARNING "DMA timeout with device %d\n",
1830                        dma_chan[ch].dev_id);
1831         if (unlikely(csr & OMAP_DMA_DROP_IRQ))
1832                 printk(KERN_WARNING "DMA synchronization event drop occurred "
1833                        "with device %d\n", dma_chan[ch].dev_id);
1834         if (likely(csr & OMAP_DMA_BLOCK_IRQ))
1835                 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1836         if (likely(dma_chan[ch].callback != NULL))
1837                 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
1838
1839         return 1;
1840 }
1841
1842 static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1843 {
1844         int ch = ((int) dev_id) - 1;
1845         int handled = 0;
1846
1847         for (;;) {
1848                 int handled_now = 0;
1849
1850                 handled_now += omap1_dma_handle_ch(ch);
1851                 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
1852                         handled_now += omap1_dma_handle_ch(ch + 6);
1853                 if (!handled_now)
1854                         break;
1855                 handled += handled_now;
1856         }
1857
1858         return handled ? IRQ_HANDLED : IRQ_NONE;
1859 }
1860
1861 #else
1862 #define omap1_dma_irq_handler   NULL
1863 #endif
1864
1865 #ifdef CONFIG_ARCH_OMAP2PLUS
1866
1867 static int omap2_dma_handle_ch(int ch)
1868 {
1869         u32 status = p->dma_read(CSR, ch);
1870
1871         if (!status) {
1872                 if (printk_ratelimit())
1873                         printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
1874                                 ch);
1875                 p->dma_write(1 << ch, IRQSTATUS_L0, ch);
1876                 return 0;
1877         }
1878         if (unlikely(dma_chan[ch].dev_id == -1)) {
1879                 if (printk_ratelimit())
1880                         printk(KERN_WARNING "IRQ %04x for non-allocated DMA"
1881                                         "channel %d\n", status, ch);
1882                 return 0;
1883         }
1884         if (unlikely(status & OMAP_DMA_DROP_IRQ))
1885                 printk(KERN_INFO
1886                        "DMA synchronization event drop occurred with device "
1887                        "%d\n", dma_chan[ch].dev_id);
1888         if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
1889                 printk(KERN_INFO "DMA transaction error with device %d\n",
1890                        dma_chan[ch].dev_id);
1891                 if (IS_DMA_ERRATA(DMA_ERRATA_i378)) {
1892                         u32 ccr;
1893
1894                         ccr = p->dma_read(CCR, ch);
1895                         ccr &= ~OMAP_DMA_CCR_EN;
1896                         p->dma_write(ccr, CCR, ch);
1897                         dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1898                 }
1899         }
1900         if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
1901                 printk(KERN_INFO "DMA secure error with device %d\n",
1902                        dma_chan[ch].dev_id);
1903         if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
1904                 printk(KERN_INFO "DMA misaligned error with device %d\n",
1905                        dma_chan[ch].dev_id);
1906
1907         p->dma_write(status, CSR, ch);
1908         p->dma_write(1 << ch, IRQSTATUS_L0, ch);
1909         /* read back the register to flush the write */
1910         p->dma_read(IRQSTATUS_L0, ch);
1911
1912         /* If the ch is not chained then chain_id will be -1 */
1913         if (dma_chan[ch].chain_id != -1) {
1914                 int chain_id = dma_chan[ch].chain_id;
1915                 dma_chan[ch].state = DMA_CH_NOTSTARTED;
1916                 if (p->dma_read(CLNK_CTRL, ch) & (1 << 15))
1917                         dma_chan[dma_chan[ch].next_linked_ch].state =
1918                                                         DMA_CH_STARTED;
1919                 if (dma_linked_lch[chain_id].chain_mode ==
1920                                                 OMAP_DMA_DYNAMIC_CHAIN)
1921                         disable_lnk(ch);
1922
1923                 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1924                         OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1925
1926                 status = p->dma_read(CSR, ch);
1927                 p->dma_write(status, CSR, ch);
1928         }
1929
1930         if (likely(dma_chan[ch].callback != NULL))
1931                 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1932
1933         return 0;
1934 }
1935
1936 /* STATUS register count is from 1-32 while our is 0-31 */
1937 static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1938 {
1939         u32 val, enable_reg;
1940         int i;
1941
1942         val = p->dma_read(IRQSTATUS_L0, 0);
1943         if (val == 0) {
1944                 if (printk_ratelimit())
1945                         printk(KERN_WARNING "Spurious DMA IRQ\n");
1946                 return IRQ_HANDLED;
1947         }
1948         enable_reg = p->dma_read(IRQENABLE_L0, 0);
1949         val &= enable_reg; /* Dispatch only relevant interrupts */
1950         for (i = 0; i < dma_lch_count && val != 0; i++) {
1951                 if (val & 1)
1952                         omap2_dma_handle_ch(i);
1953                 val >>= 1;
1954         }
1955
1956         return IRQ_HANDLED;
1957 }
1958
1959 static struct irqaction omap24xx_dma_irq = {
1960         .name = "DMA",
1961         .handler = omap2_dma_irq_handler,
1962         .flags = IRQF_DISABLED
1963 };
1964
1965 #else
1966 static struct irqaction omap24xx_dma_irq;
1967 #endif
1968
1969 /*----------------------------------------------------------------------------*/
1970
1971 void omap_dma_global_context_save(void)
1972 {
1973         omap_dma_global_context.dma_irqenable_l0 =
1974                 p->dma_read(IRQENABLE_L0, 0);
1975         omap_dma_global_context.dma_ocp_sysconfig =
1976                 p->dma_read(OCP_SYSCONFIG, 0);
1977         omap_dma_global_context.dma_gcr = p->dma_read(GCR, 0);
1978 }
1979
1980 void omap_dma_global_context_restore(void)
1981 {
1982         int ch;
1983
1984         p->dma_write(omap_dma_global_context.dma_gcr, GCR, 0);
1985         p->dma_write(omap_dma_global_context.dma_ocp_sysconfig,
1986                 OCP_SYSCONFIG, 0);
1987         p->dma_write(omap_dma_global_context.dma_irqenable_l0,
1988                 IRQENABLE_L0, 0);
1989
1990         if (IS_DMA_ERRATA(DMA_ROMCODE_BUG))
1991                 p->dma_write(0x3 , IRQSTATUS_L0, 0);
1992
1993         for (ch = 0; ch < dma_chan_count; ch++)
1994                 if (dma_chan[ch].dev_id != -1)
1995                         omap_clear_dma(ch);
1996 }
1997
1998 static int __devinit omap_system_dma_probe(struct platform_device *pdev)
1999 {
2000         int ch, ret = 0;
2001         int dma_irq;
2002         char irq_name[4];
2003         int irq_rel;
2004
2005         p = pdev->dev.platform_data;
2006         if (!p) {
2007                 dev_err(&pdev->dev, "%s: System DMA initialized without"
2008                         "platform data\n", __func__);
2009                 return -EINVAL;
2010         }
2011
2012         d                       = p->dma_attr;
2013         errata                  = p->errata;
2014
2015         if ((d->dev_caps & RESERVE_CHANNEL) && omap_dma_reserve_channels
2016                         && (omap_dma_reserve_channels < d->lch_count))
2017                 d->lch_count    = omap_dma_reserve_channels;
2018
2019         dma_lch_count           = d->lch_count;
2020         dma_chan_count          = dma_lch_count;
2021         dma_chan                = d->chan;
2022         enable_1510_mode        = d->dev_caps & ENABLE_1510_MODE;
2023
2024         if (cpu_class_is_omap2()) {
2025                 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
2026                                                 dma_lch_count, GFP_KERNEL);
2027                 if (!dma_linked_lch) {
2028                         ret = -ENOMEM;
2029                         goto exit_dma_lch_fail;
2030                 }
2031         }
2032
2033         spin_lock_init(&dma_chan_lock);
2034         for (ch = 0; ch < dma_chan_count; ch++) {
2035                 omap_clear_dma(ch);
2036                 if (cpu_class_is_omap2())
2037                         omap2_disable_irq_lch(ch);
2038
2039                 dma_chan[ch].dev_id = -1;
2040                 dma_chan[ch].next_lch = -1;
2041
2042                 if (ch >= 6 && enable_1510_mode)
2043                         continue;
2044
2045                 if (cpu_class_is_omap1()) {
2046                         /*
2047                          * request_irq() doesn't like dev_id (ie. ch) being
2048                          * zero, so we have to kludge around this.
2049                          */
2050                         sprintf(&irq_name[0], "%d", ch);
2051                         dma_irq = platform_get_irq_byname(pdev, irq_name);
2052
2053                         if (dma_irq < 0) {
2054                                 ret = dma_irq;
2055                                 goto exit_dma_irq_fail;
2056                         }
2057
2058                         /* INT_DMA_LCD is handled in lcd_dma.c */
2059                         if (dma_irq == INT_DMA_LCD)
2060                                 continue;
2061
2062                         ret = request_irq(dma_irq,
2063                                         omap1_dma_irq_handler, 0, "DMA",
2064                                         (void *) (ch + 1));
2065                         if (ret != 0)
2066                                 goto exit_dma_irq_fail;
2067                 }
2068         }
2069
2070         if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx())
2071                 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
2072                                 DMA_DEFAULT_FIFO_DEPTH, 0);
2073
2074         if (cpu_class_is_omap2()) {
2075                 strcpy(irq_name, "0");
2076                 dma_irq = platform_get_irq_byname(pdev, irq_name);
2077                 if (dma_irq < 0) {
2078                         dev_err(&pdev->dev, "failed: request IRQ %d", dma_irq);
2079                         goto exit_dma_lch_fail;
2080                 }
2081                 ret = setup_irq(dma_irq, &omap24xx_dma_irq);
2082                 if (ret) {
2083                         dev_err(&pdev->dev, "set_up failed for IRQ %d"
2084                                 "for DMA (error %d)\n", dma_irq, ret);
2085                         goto exit_dma_lch_fail;
2086                 }
2087         }
2088
2089         /* reserve dma channels 0 and 1 in high security devices */
2090         if (cpu_is_omap34xx() &&
2091                 (omap_type() != OMAP2_DEVICE_TYPE_GP)) {
2092                 printk(KERN_INFO "Reserving DMA channels 0 and 1 for "
2093                                 "HS ROM code\n");
2094                 dma_chan[0].dev_id = 0;
2095                 dma_chan[1].dev_id = 1;
2096         }
2097         p->show_dma_caps();
2098         return 0;
2099
2100 exit_dma_irq_fail:
2101         dev_err(&pdev->dev, "unable to request IRQ %d"
2102                         "for DMA (error %d)\n", dma_irq, ret);
2103         for (irq_rel = 0; irq_rel < ch; irq_rel++) {
2104                 dma_irq = platform_get_irq(pdev, irq_rel);
2105                 free_irq(dma_irq, (void *)(irq_rel + 1));
2106         }
2107
2108 exit_dma_lch_fail:
2109         kfree(p);
2110         kfree(d);
2111         kfree(dma_chan);
2112         return ret;
2113 }
2114
2115 static int __devexit omap_system_dma_remove(struct platform_device *pdev)
2116 {
2117         int dma_irq;
2118
2119         if (cpu_class_is_omap2()) {
2120                 char irq_name[4];
2121                 strcpy(irq_name, "0");
2122                 dma_irq = platform_get_irq_byname(pdev, irq_name);
2123                 remove_irq(dma_irq, &omap24xx_dma_irq);
2124         } else {
2125                 int irq_rel = 0;
2126                 for ( ; irq_rel < dma_chan_count; irq_rel++) {
2127                         dma_irq = platform_get_irq(pdev, irq_rel);
2128                         free_irq(dma_irq, (void *)(irq_rel + 1));
2129                 }
2130         }
2131         kfree(p);
2132         kfree(d);
2133         kfree(dma_chan);
2134         return 0;
2135 }
2136
2137 static struct platform_driver omap_system_dma_driver = {
2138         .probe          = omap_system_dma_probe,
2139         .remove         = omap_system_dma_remove,
2140         .driver         = {
2141                 .name   = "omap_dma_system"
2142         },
2143 };
2144
2145 static int __init omap_system_dma_init(void)
2146 {
2147         return platform_driver_register(&omap_system_dma_driver);
2148 }
2149 arch_initcall(omap_system_dma_init);
2150
2151 static void __exit omap_system_dma_exit(void)
2152 {
2153         platform_driver_unregister(&omap_system_dma_driver);
2154 }
2155
2156 MODULE_DESCRIPTION("OMAP SYSTEM DMA DRIVER");
2157 MODULE_LICENSE("GPL");
2158 MODULE_ALIAS("platform:" DRIVER_NAME);
2159 MODULE_AUTHOR("Texas Instruments Inc");
2160
2161 /*
2162  * Reserve the omap SDMA channels using cmdline bootarg
2163  * "omap_dma_reserve_ch=". The valid range is 1 to 32
2164  */
2165 static int __init omap_dma_cmdline_reserve_ch(char *str)
2166 {
2167         if (get_option(&str, &omap_dma_reserve_channels) != 1)
2168                 omap_dma_reserve_channels = 0;
2169         return 1;
2170 }
2171
2172 __setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch);
2173
2174