arch/arm/plat-omap/dma.c

   1 /*
   2  * linux/arch/arm/plat-omap/dma.c
   3  *
   4  * Copyright (C) 2003 - 2008 Nokia Corporation
   5  * Author: Juha Yrjölä <juha.yrjola@nokia.com>
   6  * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
   7  * Graphics DMA and LCD DMA graphics tranformations
   8  * by Imre Deak <imre.deak@nokia.com>
   9  * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
  10  * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
  11  * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
  12  *
  13  * Copyright (C) 2009 Texas Instruments
  14  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  15  *
  16  * Support functions for the OMAP internal DMA channels.
  17  *
  18  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
  19  * Converted DMA library into DMA platform driver.
  20  *      - G, Manjunath Kondaiah <manjugk@ti.com>
  21  *
  22  * This program is free software; you can redistribute it and/or modify
  23  * it under the terms of the GNU General Public License version 2 as
  24  * published by the Free Software Foundation.
  25  *
  26  */
  27
  28 #include <linux/module.h>
  29 #include <linux/init.h>
  30 #include <linux/sched.h>
  31 #include <linux/spinlock.h>
  32 #include <linux/errno.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/irq.h>
  35 #include <linux/io.h>
  36 #include <linux/slab.h>
  37 #include <linux/delay.h>
  38
  39 #include <asm/system.h>
  40 #include <mach/hardware.h>
  41 #include <plat/dma.h>
  42
  43 #include <plat/tc.h>
  44
  45 #undef DEBUG
  46
  47 #ifndef CONFIG_ARCH_OMAP1
  48 enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
  49         DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
  50 };
  51
  52 enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
  53 #endif
  54
  55 #define OMAP_DMA_ACTIVE                 0x01
  56 #define OMAP2_DMA_CSR_CLEAR_MASK        0xffffffff
  57
  58 #define OMAP_FUNC_MUX_ARM_BASE          (0xfffe1000 + 0xec)
  59
  60 static struct omap_system_dma_plat_info *p;
  61 static struct omap_dma_dev_attr *d;
  62
  63 static int enable_1510_mode;
  64 static u32 errata;
  65
  66 static struct omap_dma_global_context_registers {
  67         u32 dma_irqenable_l0;
  68         u32 dma_ocp_sysconfig;
  69         u32 dma_gcr;
  70 } omap_dma_global_context;
  71
  72 struct dma_link_info {
  73         int *linked_dmach_q;
  74         int no_of_lchs_linked;
  75
  76         int q_count;
  77         int q_tail;
  78         int q_head;
  79
  80         int chain_state;
  81         int chain_mode;
  82
  83 };
  84
  85 static struct dma_link_info *dma_linked_lch;
  86
  87 #ifndef CONFIG_ARCH_OMAP1
  88
  89 /* Chain handling macros */
  90 #define OMAP_DMA_CHAIN_QINIT(chain_id)                                  \
  91         do {                                                            \
  92                 dma_linked_lch[chain_id].q_head =                       \
  93                 dma_linked_lch[chain_id].q_tail =                       \
  94                 dma_linked_lch[chain_id].q_count = 0;                   \
  95         } while (0)
  96 #define OMAP_DMA_CHAIN_QFULL(chain_id)                                  \
  97                 (dma_linked_lch[chain_id].no_of_lchs_linked ==          \
  98                 dma_linked_lch[chain_id].q_count)
  99 #define OMAP_DMA_CHAIN_QLAST(chain_id)                                  \
 100         do {                                                            \
 101                 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) ==      \
 102                 dma_linked_lch[chain_id].q_count)                       \
 103         } while (0)
 104 #define OMAP_DMA_CHAIN_QEMPTY(chain_id)                                 \
 105                 (0 == dma_linked_lch[chain_id].q_count)
 106 #define __OMAP_DMA_CHAIN_INCQ(end)                                      \
 107         ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
 108 #define OMAP_DMA_CHAIN_INCQHEAD(chain_id)                               \
 109         do {                                                            \
 110                 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
 111                 dma_linked_lch[chain_id].q_count--;                     \
 112         } while (0)
 113
 114 #define OMAP_DMA_CHAIN_INCQTAIL(chain_id)                               \
 115         do {                                                            \
 116                 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
 117                 dma_linked_lch[chain_id].q_count++; \
 118         } while (0)
 119 #endif
 120
 121 static int dma_lch_count;
 122 static int dma_chan_count;
 123 static int omap_dma_reserve_channels;
 124
 125 static spinlock_t dma_chan_lock;
 126 static struct omap_dma_lch *dma_chan;
 127
 128 static inline void disable_lnk(int lch);
 129 static void omap_disable_channel_irq(int lch);
 130 static inline void omap_enable_channel_irq(int lch);
 131
 132 #define REVISIT_24XX()          printk(KERN_ERR "FIXME: no %s on 24xx\n", \
 133                                                 __func__);
 134
 135 #ifdef CONFIG_ARCH_OMAP15XX
 136 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
 137 static int omap_dma_in_1510_mode(void)
 138 {
 139         return enable_1510_mode;
 140 }
 141 #else
 142 #define omap_dma_in_1510_mode()         0
 143 #endif
 144
 145 #ifdef CONFIG_ARCH_OMAP1
 146 static inline int get_gdma_dev(int req)
 147 {
 148         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
 149         int shift = ((req - 1) % 5) * 6;
 150
 151         return ((omap_readl(reg) >> shift) & 0x3f) + 1;
 152 }
 153
 154 static inline void set_gdma_dev(int req, int dev)
 155 {
 156         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
 157         int shift = ((req - 1) % 5) * 6;
 158         u32 l;
 159
 160         l = omap_readl(reg);
 161         l &= ~(0x3f << shift);
 162         l |= (dev - 1) << shift;
 163         omap_writel(l, reg);
 164 }
 165 #else
 166 #define set_gdma_dev(req, dev)  do {} while (0)
 167 #endif
 168
 169 void omap_set_dma_priority(int lch, int dst_port, int priority)
 170 {
 171         unsigned long reg;
 172         u32 l;
 173
 174         if (cpu_class_is_omap1()) {
 175                 switch (dst_port) {
 176                 case OMAP_DMA_PORT_OCP_T1:      /* FFFECC00 */
 177                         reg = OMAP_TC_OCPT1_PRIOR;
 178                         break;
 179                 case OMAP_DMA_PORT_OCP_T2:      /* FFFECCD0 */
 180                         reg = OMAP_TC_OCPT2_PRIOR;
 181                         break;
 182                 case OMAP_DMA_PORT_EMIFF:       /* FFFECC08 */
 183                         reg = OMAP_TC_EMIFF_PRIOR;
 184                         break;
 185                 case OMAP_DMA_PORT_EMIFS:       /* FFFECC04 */
 186                         reg = OMAP_TC_EMIFS_PRIOR;
 187                         break;
 188                 default:
 189                         BUG();
 190                         return;
 191                 }
 192                 l = omap_readl(reg);
 193                 l &= ~(0xf << 8);
 194                 l |= (priority & 0xf) << 8;
 195                 omap_writel(l, reg);
 196         }
 197
 198         if (cpu_class_is_omap2()) {
 199                 u32 ccr;
 200
 201                 ccr = p->dma_read(CCR, lch);
 202                 if (priority)
 203                         ccr |= (1 << 6);
 204                 else
 205                         ccr &= ~(1 << 6);
 206                 p->dma_write(ccr, CCR, lch);
 207         }
 208 }
 209 EXPORT_SYMBOL(omap_set_dma_priority);
 210
 211 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
 212                                   int frame_count, int sync_mode,
 213                                   int dma_trigger, int src_or_dst_synch)
 214 {
 215         u32 l;
 216
 217         l = p->dma_read(CSDP, lch);
 218         l &= ~0x03;
 219         l |= data_type;
 220         p->dma_write(l, CSDP, lch);
 221
 222         if (cpu_class_is_omap1()) {
 223                 u16 ccr;
 224
 225                 ccr = p->dma_read(CCR, lch);
 226                 ccr &= ~(1 << 5);
 227                 if (sync_mode == OMAP_DMA_SYNC_FRAME)
 228                         ccr |= 1 << 5;
 229                 p->dma_write(ccr, CCR, lch);
 230
 231                 ccr = p->dma_read(CCR2, lch);
 232                 ccr &= ~(1 << 2);
 233                 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
 234                         ccr |= 1 << 2;
 235                 p->dma_write(ccr, CCR2, lch);
 236         }
 237
 238         if (cpu_class_is_omap2() && dma_trigger) {
 239                 u32 val;
 240
 241                 val = p->dma_read(CCR, lch);
 242
 243                 /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
 244                 val &= ~((1 << 23) | (3 << 19) | 0x1f);
 245                 val |= (dma_trigger & ~0x1f) << 14;
 246                 val |= dma_trigger & 0x1f;
 247
 248                 if (sync_mode & OMAP_DMA_SYNC_FRAME)
 249                         val |= 1 << 5;
 250                 else
 251                         val &= ~(1 << 5);
 252
 253                 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
 254                         val |= 1 << 18;
 255                 else
 256                         val &= ~(1 << 18);
 257
 258                 if (src_or_dst_synch == OMAP_DMA_DST_SYNC_PREFETCH) {
 259                         val &= ~(1 << 24);      /* dest synch */
 260                         val |= (1 << 23);       /* Prefetch */
 261                 } else if (src_or_dst_synch) {
 262                         val |= 1 << 24;         /* source synch */
 263                 } else {
 264                         val &= ~(1 << 24);      /* dest synch */
 265                 }
 266                 p->dma_write(val, CCR, lch);
 267         }
 268
 269         p->dma_write(elem_count, CEN, lch);
 270         p->dma_write(frame_count, CFN, lch);
 271 }
 272 EXPORT_SYMBOL(omap_set_dma_transfer_params);
 273
 274 void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
 275 {
 276         BUG_ON(omap_dma_in_1510_mode());
 277
 278         if (cpu_class_is_omap1()) {
 279                 u16 w;
 280
 281                 w = p->dma_read(CCR2, lch);
 282                 w &= ~0x03;
 283
 284                 switch (mode) {
 285                 case OMAP_DMA_CONSTANT_FILL:
 286                         w |= 0x01;
 287                         break;
 288                 case OMAP_DMA_TRANSPARENT_COPY:
 289                         w |= 0x02;
 290                         break;
 291                 case OMAP_DMA_COLOR_DIS:
 292                         break;
 293                 default:
 294                         BUG();
 295                 }
 296                 p->dma_write(w, CCR2, lch);
 297
 298                 w = p->dma_read(LCH_CTRL, lch);
 299                 w &= ~0x0f;
 300                 /* Default is channel type 2D */
 301                 if (mode) {
 302                         p->dma_write(color, COLOR, lch);
 303                         w |= 1;         /* Channel type G */
 304                 }
 305                 p->dma_write(w, LCH_CTRL, lch);
 306         }
 307
 308         if (cpu_class_is_omap2()) {
 309                 u32 val;
 310
 311                 val = p->dma_read(CCR, lch);
 312                 val &= ~((1 << 17) | (1 << 16));
 313
 314                 switch (mode) {
 315                 case OMAP_DMA_CONSTANT_FILL:
 316                         val |= 1 << 16;
 317                         break;
 318                 case OMAP_DMA_TRANSPARENT_COPY:
 319                         val |= 1 << 17;
 320                         break;
 321                 case OMAP_DMA_COLOR_DIS:
 322                         break;
 323                 default:
 324                         BUG();
 325                 }
 326                 p->dma_write(val, CCR, lch);
 327
 328                 color &= 0xffffff;
 329                 p->dma_write(color, COLOR, lch);
 330         }
 331 }
 332 EXPORT_SYMBOL(omap_set_dma_color_mode);
 333
 334 void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
 335 {
 336         if (cpu_class_is_omap2()) {
 337                 u32 csdp;
 338
 339                 csdp = p->dma_read(CSDP, lch);
 340                 csdp &= ~(0x3 << 16);
 341                 csdp |= (mode << 16);
 342                 p->dma_write(csdp, CSDP, lch);
 343         }
 344 }
 345 EXPORT_SYMBOL(omap_set_dma_write_mode);
 346
 347 void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
 348 {
 349         if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
 350                 u32 l;
 351
 352                 l = p->dma_read(LCH_CTRL, lch);
 353                 l &= ~0x7;
 354                 l |= mode;
 355                 p->dma_write(l, LCH_CTRL, lch);
 356         }
 357 }
 358 EXPORT_SYMBOL(omap_set_dma_channel_mode);
 359
 360 /* Note that src_port is only for omap1 */
 361 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
 362                              unsigned long src_start,
 363                              int src_ei, int src_fi)
 364 {
 365         u32 l;
 366
 367         if (cpu_class_is_omap1()) {
 368                 u16 w;
 369
 370                 w = p->dma_read(CSDP, lch);
 371                 w &= ~(0x1f << 2);
 372                 w |= src_port << 2;
 373                 p->dma_write(w, CSDP, lch);
 374         }
 375
 376         l = p->dma_read(CCR, lch);
 377         l &= ~(0x03 << 12);
 378         l |= src_amode << 12;
 379         p->dma_write(l, CCR, lch);
 380
 381         p->dma_write(src_start, CSSA, lch);
 382
 383         p->dma_write(src_ei, CSEI, lch);
 384         p->dma_write(src_fi, CSFI, lch);
 385 }
 386 EXPORT_SYMBOL(omap_set_dma_src_params);
 387
 388 void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
 389 {
 390         omap_set_dma_transfer_params(lch, params->data_type,
 391                                      params->elem_count, params->frame_count,
 392                                      params->sync_mode, params->trigger,
 393                                      params->src_or_dst_synch);
 394         omap_set_dma_src_params(lch, params->src_port,
 395                                 params->src_amode, params->src_start,
 396                                 params->src_ei, params->src_fi);
 397
 398         omap_set_dma_dest_params(lch, params->dst_port,
 399                                  params->dst_amode, params->dst_start,
 400                                  params->dst_ei, params->dst_fi);
 401         if (params->read_prio || params->write_prio)
 402                 omap_dma_set_prio_lch(lch, params->read_prio,
 403                                       params->write_prio);
 404 }
 405 EXPORT_SYMBOL(omap_set_dma_params);
 406
 407 void omap_set_dma_src_index(int lch, int eidx, int fidx)
 408 {
 409         if (cpu_class_is_omap2())
 410                 return;
 411
 412         p->dma_write(eidx, CSEI, lch);
 413         p->dma_write(fidx, CSFI, lch);
 414 }
 415 EXPORT_SYMBOL(omap_set_dma_src_index);
 416
 417 void omap_set_dma_src_data_pack(int lch, int enable)
 418 {
 419         u32 l;
 420
 421         l = p->dma_read(CSDP, lch);
 422         l &= ~(1 << 6);
 423         if (enable)
 424                 l |= (1 << 6);
 425         p->dma_write(l, CSDP, lch);
 426 }
 427 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
 428
 429 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
 430 {
 431         unsigned int burst = 0;
 432         u32 l;
 433
 434         l = p->dma_read(CSDP, lch);
 435         l &= ~(0x03 << 7);
 436
 437         switch (burst_mode) {
 438         case OMAP_DMA_DATA_BURST_DIS:
 439                 break;
 440         case OMAP_DMA_DATA_BURST_4:
 441                 if (cpu_class_is_omap2())
 442                         burst = 0x1;
 443                 else
 444                         burst = 0x2;
 445                 break;
 446         case OMAP_DMA_DATA_BURST_8:
 447                 if (cpu_class_is_omap2()) {
 448                         burst = 0x2;
 449                         break;
 450                 }
 451                 /*
 452                  * not supported by current hardware on OMAP1
 453                  * w |= (0x03 << 7);
 454                  * fall through
 455                  */
 456         case OMAP_DMA_DATA_BURST_16:
 457                 if (cpu_class_is_omap2()) {
 458                         burst = 0x3;
 459                         break;
 460                 }
 461                 /*
 462                  * OMAP1 don't support burst 16
 463                  * fall through
 464                  */
 465         default:
 466                 BUG();
 467         }
 468
 469         l |= (burst << 7);
 470         p->dma_write(l, CSDP, lch);
 471 }
 472 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
 473
 474 /* Note that dest_port is only for OMAP1 */
 475 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
 476                               unsigned long dest_start,
 477                               int dst_ei, int dst_fi)
 478 {
 479         u32 l;
 480
 481         if (cpu_class_is_omap1()) {
 482                 l = p->dma_read(CSDP, lch);
 483                 l &= ~(0x1f << 9);
 484                 l |= dest_port << 9;
 485                 p->dma_write(l, CSDP, lch);
 486         }
 487
 488         l = p->dma_read(CCR, lch);
 489         l &= ~(0x03 << 14);
 490         l |= dest_amode << 14;
 491         p->dma_write(l, CCR, lch);
 492
 493         p->dma_write(dest_start, CDSA, lch);
 494
 495         p->dma_write(dst_ei, CDEI, lch);
 496         p->dma_write(dst_fi, CDFI, lch);
 497 }
 498 EXPORT_SYMBOL(omap_set_dma_dest_params);
 499
 500 void omap_set_dma_dest_index(int lch, int eidx, int fidx)
 501 {
 502         if (cpu_class_is_omap2())
 503                 return;
 504
 505         p->dma_write(eidx, CDEI, lch);
 506         p->dma_write(fidx, CDFI, lch);
 507 }
 508 EXPORT_SYMBOL(omap_set_dma_dest_index);
 509
 510 void omap_set_dma_dest_data_pack(int lch, int enable)
 511 {
 512         u32 l;
 513
 514         l = p->dma_read(CSDP, lch);
 515         l &= ~(1 << 13);
 516         if (enable)
 517                 l |= 1 << 13;
 518         p->dma_write(l, CSDP, lch);
 519 }
 520 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
 521
 522 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
 523 {
 524         unsigned int burst = 0;
 525         u32 l;
 526
 527         l = p->dma_read(CSDP, lch);
 528         l &= ~(0x03 << 14);
 529
 530         switch (burst_mode) {
 531         case OMAP_DMA_DATA_BURST_DIS:
 532                 break;
 533         case OMAP_DMA_DATA_BURST_4:
 534                 if (cpu_class_is_omap2())
 535                         burst = 0x1;
 536                 else
 537                         burst = 0x2;
 538                 break;
 539         case OMAP_DMA_DATA_BURST_8:
 540                 if (cpu_class_is_omap2())
 541                         burst = 0x2;
 542                 else
 543                         burst = 0x3;
 544                 break;
 545         case OMAP_DMA_DATA_BURST_16:
 546                 if (cpu_class_is_omap2()) {
 547                         burst = 0x3;
 548                         break;
 549                 }
 550                 /*
 551                  * OMAP1 don't support burst 16
 552                  * fall through
 553                  */
 554         default:
 555                 printk(KERN_ERR "Invalid DMA burst mode\n");
 556                 BUG();
 557                 return;
 558         }
 559         l |= (burst << 14);
 560         p->dma_write(l, CSDP, lch);
 561 }
 562 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
 563
 564 static inline void omap_enable_channel_irq(int lch)
 565 {
 566         /* Clear CSR */
 567         if (cpu_class_is_omap1())
 568                 p->dma_read(CSR, lch);
 569         else
 570                 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
 571
 572         /* Enable some nice interrupts. */
 573         p->dma_write(dma_chan[lch].enabled_irqs, CICR, lch);
 574 }
 575
 576 static inline void omap_disable_channel_irq(int lch)
 577 {
 578         /* disable channel interrupts */
 579         p->dma_write(0, CICR, lch);
 580         /* Clear CSR */
 581         if (cpu_class_is_omap1())
 582                 p->dma_read(CSR, lch);
 583         else
 584                 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
 585 }
 586
 587 void omap_enable_dma_irq(int lch, u16 bits)
 588 {
 589         dma_chan[lch].enabled_irqs |= bits;
 590 }
 591 EXPORT_SYMBOL(omap_enable_dma_irq);
 592
 593 void omap_disable_dma_irq(int lch, u16 bits)
 594 {
 595         dma_chan[lch].enabled_irqs &= ~bits;
 596 }
 597 EXPORT_SYMBOL(omap_disable_dma_irq);
 598
 599 static inline void enable_lnk(int lch)
 600 {
 601         u32 l;
 602
 603         l = p->dma_read(CLNK_CTRL, lch);
 604
 605         if (cpu_class_is_omap1())
 606                 l &= ~(1 << 14);
 607
 608         /* Set the ENABLE_LNK bits */
 609         if (dma_chan[lch].next_lch != -1)
 610                 l = dma_chan[lch].next_lch | (1 << 15);
 611
 612 #ifndef CONFIG_ARCH_OMAP1
 613         if (cpu_class_is_omap2())
 614                 if (dma_chan[lch].next_linked_ch != -1)
 615                         l = dma_chan[lch].next_linked_ch | (1 << 15);
 616 #endif
 617
 618         p->dma_write(l, CLNK_CTRL, lch);
 619 }
 620
 621 static inline void disable_lnk(int lch)
 622 {
 623         u32 l;
 624
 625         l = p->dma_read(CLNK_CTRL, lch);
 626
 627         /* Disable interrupts */
 628         omap_disable_channel_irq(lch);
 629
 630         if (cpu_class_is_omap1()) {
 631                 /* Set the STOP_LNK bit */
 632                 l |= 1 << 14;
 633         }
 634
 635         if (cpu_class_is_omap2()) {
 636                 /* Clear the ENABLE_LNK bit */
 637                 l &= ~(1 << 15);
 638         }
 639
 640         p->dma_write(l, CLNK_CTRL, lch);
 641         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
 642 }
 643
 644 static inline void omap2_enable_irq_lch(int lch)
 645 {
 646         u32 val;
 647         unsigned long flags;
 648
 649         if (!cpu_class_is_omap2())
 650                 return;
 651
 652         spin_lock_irqsave(&dma_chan_lock, flags);
 653         /* clear IRQ STATUS */
 654         p->dma_write(1 << lch, IRQSTATUS_L0, lch);
 655         /* Enable interrupt */
 656         val = p->dma_read(IRQENABLE_L0, lch);
 657         val |= 1 << lch;
 658         p->dma_write(val, IRQENABLE_L0, lch);
 659         spin_unlock_irqrestore(&dma_chan_lock, flags);
 660 }
 661
 662 static inline void omap2_disable_irq_lch(int lch)
 663 {
 664         u32 val;
 665         unsigned long flags;
 666
 667         if (!cpu_class_is_omap2())
 668                 return;
 669
 670         spin_lock_irqsave(&dma_chan_lock, flags);
 671         /* Disable interrupt */
 672         val = p->dma_read(IRQENABLE_L0, lch);
 673         val &= ~(1 << lch);
 674         p->dma_write(val, IRQENABLE_L0, lch);
 675         /* clear IRQ STATUS */
 676         p->dma_write(1 << lch, IRQSTATUS_L0, lch);
 677         spin_unlock_irqrestore(&dma_chan_lock, flags);
 678 }
 679
 680 int omap_request_dma(int dev_id, const char *dev_name,
 681                      void (*callback)(int lch, u16 ch_status, void *data),
 682                      void *data, int *dma_ch_out)
 683 {
 684         int ch, free_ch = -1;
 685         unsigned long flags;
 686         struct omap_dma_lch *chan;
 687
 688         spin_lock_irqsave(&dma_chan_lock, flags);
 689         for (ch = 0; ch < dma_chan_count; ch++) {
 690                 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
 691                         free_ch = ch;
 692                         /* Exit after first free channel found */
 693                         break;
 694                 }
 695         }
 696         if (free_ch == -1) {
 697                 spin_unlock_irqrestore(&dma_chan_lock, flags);
 698                 return -EBUSY;
 699         }
 700         chan = dma_chan + free_ch;
 701         chan->dev_id = dev_id;
 702
 703         if (p->clear_lch_regs)
 704                 p->clear_lch_regs(free_ch);
 705
 706         if (cpu_class_is_omap2())
 707                 omap_clear_dma(free_ch);
 708
 709         spin_unlock_irqrestore(&dma_chan_lock, flags);
 710
 711         chan->dev_name = dev_name;
 712         chan->callback = callback;
 713         chan->data = data;
 714         chan->flags = 0;
 715
 716 #ifndef CONFIG_ARCH_OMAP1
 717         if (cpu_class_is_omap2()) {
 718                 chan->chain_id = -1;
 719                 chan->next_linked_ch = -1;
 720         }
 721 #endif
 722
 723         chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
 724
 725         if (cpu_class_is_omap1())
 726                 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
 727         else if (cpu_class_is_omap2())
 728                 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
 729                         OMAP2_DMA_TRANS_ERR_IRQ;
 730
 731         if (cpu_is_omap16xx()) {
 732                 /* If the sync device is set, configure it dynamically. */
 733                 if (dev_id != 0) {
 734                         set_gdma_dev(free_ch + 1, dev_id);
 735                         dev_id = free_ch + 1;
 736                 }
 737                 /*
 738                  * Disable the 1510 compatibility mode and set the sync device
 739                  * id.
 740                  */
 741                 p->dma_write(dev_id | (1 << 10), CCR, free_ch);
 742         } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) {
 743                 p->dma_write(dev_id, CCR, free_ch);
 744         }
 745
 746         if (cpu_class_is_omap2()) {
 747                 omap_enable_channel_irq(free_ch);
 748                 omap2_enable_irq_lch(free_ch);
 749         }
 750
 751         *dma_ch_out = free_ch;
 752
 753         return 0;
 754 }
 755 EXPORT_SYMBOL(omap_request_dma);
 756
 757 void omap_free_dma(int lch)
 758 {
 759         unsigned long flags;
 760
 761         if (dma_chan[lch].dev_id == -1) {
 762                 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
 763                        lch);
 764                 return;
 765         }
 766
 767         /* Disable interrupt for logical channel */
 768         if (cpu_class_is_omap2())
 769                 omap2_disable_irq_lch(lch);
 770
 771         /* Disable all DMA interrupts for the channel. */
 772         omap_disable_channel_irq(lch);
 773
 774         /* Make sure the DMA transfer is stopped. */
 775         p->dma_write(0, CCR, lch);
 776
 777         /* Clear registers */
 778         if (cpu_class_is_omap2())
 779                 omap_clear_dma(lch);
 780
 781         spin_lock_irqsave(&dma_chan_lock, flags);
 782         dma_chan[lch].dev_id = -1;
 783         dma_chan[lch].next_lch = -1;
 784         dma_chan[lch].callback = NULL;
 785         spin_unlock_irqrestore(&dma_chan_lock, flags);
 786 }
 787 EXPORT_SYMBOL(omap_free_dma);
 788
 789 /**
 790  * @brief omap_dma_set_global_params : Set global priority settings for dma
 791  *
 792  * @param arb_rate
 793  * @param max_fifo_depth
 794  * @param tparams - Number of threads to reserve : DMA_THREAD_RESERVE_NORM
 795  *                                                 DMA_THREAD_RESERVE_ONET
 796  *                                                 DMA_THREAD_RESERVE_TWOT
 797  *                                                 DMA_THREAD_RESERVE_THREET
 798  */
 799 void
 800 omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
 801 {
 802         u32 reg;
 803
 804         if (!cpu_class_is_omap2()) {
 805                 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
 806                 return;
 807         }
 808
 809         if (max_fifo_depth == 0)
 810                 max_fifo_depth = 1;
 811         if (arb_rate == 0)
 812                 arb_rate = 1;
 813
 814         reg = 0xff & max_fifo_depth;
 815         reg |= (0x3 & tparams) << 12;
 816         reg |= (arb_rate & 0xff) << 16;
 817
 818         p->dma_write(reg, GCR, 0);
 819 }
 820 EXPORT_SYMBOL(omap_dma_set_global_params);
 821
 822 /**
 823  * @brief omap_dma_set_prio_lch : Set channel wise priority settings
 824  *
 825  * @param lch
 826  * @param read_prio - Read priority
 827  * @param write_prio - Write priority
 828  * Both of the above can be set with one of the following values :
 829  *      DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
 830  */
 831 int
 832 omap_dma_set_prio_lch(int lch, unsigned char read_prio,
 833                       unsigned char write_prio)
 834 {
 835         u32 l;
 836
 837         if (unlikely((lch < 0 || lch >= dma_lch_count))) {
 838                 printk(KERN_ERR "Invalid channel id\n");
 839                 return -EINVAL;
 840         }
 841         l = p->dma_read(CCR, lch);
 842         l &= ~((1 << 6) | (1 << 26));
 843         if (cpu_is_omap2430() || cpu_is_omap34xx() ||  cpu_is_omap44xx())
 844                 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
 845         else
 846                 l |= ((read_prio & 0x1) << 6);
 847
 848         p->dma_write(l, CCR, lch);
 849
 850         return 0;
 851 }
 852 EXPORT_SYMBOL(omap_dma_set_prio_lch);
 853
 854 /*
 855  * Clears any DMA state so the DMA engine is ready to restart with new buffers
 856  * through omap_start_dma(). Any buffers in flight are discarded.
 857  */
 858 void omap_clear_dma(int lch)
 859 {
 860         unsigned long flags;
 861
 862         local_irq_save(flags);
 863         p->clear_dma(lch);
 864         local_irq_restore(flags);
 865 }
 866 EXPORT_SYMBOL(omap_clear_dma);
 867
 868 void omap_start_dma(int lch)
 869 {
 870         u32 l;
 871
 872         /*
 873          * The CPC/CDAC register needs to be initialized to zero
 874          * before starting dma transfer.
 875          */
 876         if (cpu_is_omap15xx())
 877                 p->dma_write(0, CPC, lch);
 878         else
 879                 p->dma_write(0, CDAC, lch);
 880
 881         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
 882                 int next_lch, cur_lch;
 883                 char dma_chan_link_map[dma_lch_count];
 884
 885                 /* Set the link register of the first channel */
 886                 enable_lnk(lch);
 887
 888                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
 889                 dma_chan_link_map[lch] = 1;
 890
 891                 cur_lch = dma_chan[lch].next_lch;
 892                 do {
 893                         next_lch = dma_chan[cur_lch].next_lch;
 894
 895                         /* The loop case: we've been here already */
 896                         if (dma_chan_link_map[cur_lch])
 897                                 break;
 898                         /* Mark the current channel */
 899                         dma_chan_link_map[cur_lch] = 1;
 900
 901                         enable_lnk(cur_lch);
 902                         omap_enable_channel_irq(cur_lch);
 903
 904                         cur_lch = next_lch;
 905                 } while (next_lch != -1);
 906         } else if (IS_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS))
 907                 p->dma_write(lch, CLNK_CTRL, lch);
 908
 909         omap_enable_channel_irq(lch);
 910
 911         l = p->dma_read(CCR, lch);
 912
 913         if (IS_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING))
 914                         l |= OMAP_DMA_CCR_BUFFERING_DISABLE;
 915         l |= OMAP_DMA_CCR_EN;
 916
 917         /*
 918          * As dma_write() uses IO accessors which are weakly ordered, there
 919          * is no guarantee that data in coherent DMA memory will be visible
 920          * to the DMA device.  Add a memory barrier here to ensure that any
 921          * such data is visible prior to enabling DMA.
 922          */
 923         mb();
 924         p->dma_write(l, CCR, lch);
 925
 926         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
 927 }
 928 EXPORT_SYMBOL(omap_start_dma);
 929
 930 void omap_stop_dma(int lch)
 931 {
 932         u32 l;
 933
 934         /* Disable all interrupts on the channel */
 935         omap_disable_channel_irq(lch);
 936
 937         l = p->dma_read(CCR, lch);
 938         if (IS_DMA_ERRATA(DMA_ERRATA_i541) &&
 939                         (l & OMAP_DMA_CCR_SEL_SRC_DST_SYNC)) {
 940                 int i = 0;
 941                 u32 sys_cf;
 942
 943                 /* Configure No-Standby */
 944                 l = p->dma_read(OCP_SYSCONFIG, lch);
 945                 sys_cf = l;
 946                 l &= ~DMA_SYSCONFIG_MIDLEMODE_MASK;
 947                 l |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE);
 948                 p->dma_write(l , OCP_SYSCONFIG, 0);
 949
 950                 l = p->dma_read(CCR, lch);
 951                 l &= ~OMAP_DMA_CCR_EN;
 952                 p->dma_write(l, CCR, lch);
 953
 954                 /* Wait for sDMA FIFO drain */
 955                 l = p->dma_read(CCR, lch);
 956                 while (i < 100 && (l & (OMAP_DMA_CCR_RD_ACTIVE |
 957                                         OMAP_DMA_CCR_WR_ACTIVE))) {
 958                         udelay(5);
 959                         i++;
 960                         l = p->dma_read(CCR, lch);
 961                 }
 962                 if (i >= 100)
 963                         printk(KERN_ERR "DMA drain did not complete on "
 964                                         "lch %d\n", lch);
 965                 /* Restore OCP_SYSCONFIG */
 966                 p->dma_write(sys_cf, OCP_SYSCONFIG, lch);
 967         } else {
 968                 l &= ~OMAP_DMA_CCR_EN;
 969                 p->dma_write(l, CCR, lch);
 970         }
 971
 972         /*
 973          * Ensure that data transferred by DMA is visible to any access
 974          * after DMA has been disabled.  This is important for coherent
 975          * DMA regions.
 976          */
 977         mb();
 978
 979         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
 980                 int next_lch, cur_lch = lch;
 981                 char dma_chan_link_map[dma_lch_count];
 982
 983                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
 984                 do {
 985                         /* The loop case: we've been here already */
 986                         if (dma_chan_link_map[cur_lch])
 987                                 break;
 988                         /* Mark the current channel */
 989                         dma_chan_link_map[cur_lch] = 1;
 990
 991                         disable_lnk(cur_lch);
 992
 993                         next_lch = dma_chan[cur_lch].next_lch;
 994                         cur_lch = next_lch;
 995                 } while (next_lch != -1);
 996         }
 997
 998         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
 999 }
1000 EXPORT_SYMBOL(omap_stop_dma);
1001
1002 /*
1003  * Allows changing the DMA callback function or data. This may be needed if
1004  * the driver shares a single DMA channel for multiple dma triggers.
1005  */
1006 int omap_set_dma_callback(int lch,
1007                           void (*callback)(int lch, u16 ch_status, void *data),
1008                           void *data)
1009 {
1010         unsigned long flags;
1011
1012         if (lch < 0)
1013                 return -ENODEV;
1014
1015         spin_lock_irqsave(&dma_chan_lock, flags);
1016         if (dma_chan[lch].dev_id == -1) {
1017                 printk(KERN_ERR "DMA callback for not set for free channel\n");
1018                 spin_unlock_irqrestore(&dma_chan_lock, flags);
1019                 return -EINVAL;
1020         }
1021         dma_chan[lch].callback = callback;
1022         dma_chan[lch].data = data;
1023         spin_unlock_irqrestore(&dma_chan_lock, flags);
1024
1025         return 0;
1026 }
1027 EXPORT_SYMBOL(omap_set_dma_callback);
1028
1029 /*
1030  * Returns current physical source address for the given DMA channel.
1031  * If the channel is running the caller must disable interrupts prior calling
1032  * this function and process the returned value before re-enabling interrupt to
1033  * prevent races with the interrupt handler. Note that in continuous mode there
1034  * is a chance for CSSA_L register overflow between the two reads resulting
1035  * in incorrect return value.
1036  */
1037 dma_addr_t omap_get_dma_src_pos(int lch)
1038 {
1039         dma_addr_t offset = 0;
1040
1041         if (cpu_is_omap15xx())
1042                 offset = p->dma_read(CPC, lch);
1043         else
1044                 offset = p->dma_read(CSAC, lch);
1045
1046         if (IS_DMA_ERRATA(DMA_ERRATA_3_3) && offset == 0)
1047                 offset = p->dma_read(CSAC, lch);
1048
1049         if (!cpu_is_omap15xx()) {
1050                 /*
1051                  * CDAC == 0 indicates that the DMA transfer on the channel has
1052                  * not been started (no data has been transferred so far).
1053                  * Return the programmed source start address in this case.
1054                  */
1055                 if (likely(p->dma_read(CDAC, lch)))
1056                         offset = p->dma_read(CSAC, lch);
1057                 else
1058                         offset = p->dma_read(CSSA, lch);
1059         }
1060
1061         if (cpu_class_is_omap1())
1062                 offset |= (p->dma_read(CSSA, lch) & 0xFFFF0000);
1063
1064         return offset;
1065 }
1066 EXPORT_SYMBOL(omap_get_dma_src_pos);
1067
1068 /*
1069  * Returns current physical destination address for the given DMA channel.
1070  * If the channel is running the caller must disable interrupts prior calling
1071  * this function and process the returned value before re-enabling interrupt to
1072  * prevent races with the interrupt handler. Note that in continuous mode there
1073  * is a chance for CDSA_L register overflow between the two reads resulting
1074  * in incorrect return value.
1075  */
1076 dma_addr_t omap_get_dma_dst_pos(int lch)
1077 {
1078         dma_addr_t offset = 0;
1079
1080         if (cpu_is_omap15xx())
1081                 offset = p->dma_read(CPC, lch);
1082         else
1083                 offset = p->dma_read(CDAC, lch);
1084
1085         /*
1086          * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1087          * read before the DMA controller finished disabling the channel.
1088          */
1089         if (!cpu_is_omap15xx() && offset == 0) {
1090                 offset = p->dma_read(CDAC, lch);
1091                 /*
1092                  * CDAC == 0 indicates that the DMA transfer on the channel has
1093                  * not been started (no data has been transferred so far).
1094                  * Return the programmed destination start address in this case.
1095                  */
1096                 if (unlikely(!offset))
1097                         offset = p->dma_read(CDSA, lch);
1098         }
1099
1100         if (cpu_class_is_omap1())
1101                 offset |= (p->dma_read(CDSA, lch) & 0xFFFF0000);
1102
1103         return offset;
1104 }
1105 EXPORT_SYMBOL(omap_get_dma_dst_pos);
1106
1107 int omap_get_dma_active_status(int lch)
1108 {
1109         return (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN) != 0;
1110 }
1111 EXPORT_SYMBOL(omap_get_dma_active_status);
1112
1113 int omap_dma_running(void)
1114 {
1115         int lch;
1116
1117         if (cpu_class_is_omap1())
1118                 if (omap_lcd_dma_running())
1119                         return 1;
1120
1121         for (lch = 0; lch < dma_chan_count; lch++)
1122                 if (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN)
1123                         return 1;
1124
1125         return 0;
1126 }
1127
1128 /*
1129  * lch_queue DMA will start right after lch_head one is finished.
1130  * For this DMA link to start, you still need to start (see omap_start_dma)
1131  * the first one. That will fire up the entire queue.
1132  */
1133 void omap_dma_link_lch(int lch_head, int lch_queue)
1134 {
1135         if (omap_dma_in_1510_mode()) {
1136                 if (lch_head == lch_queue) {
1137                         p->dma_write(p->dma_read(CCR, lch_head) | (3 << 8),
1138                                                                 CCR, lch_head);
1139                         return;
1140                 }
1141                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1142                 BUG();
1143                 return;
1144         }
1145
1146         if ((dma_chan[lch_head].dev_id == -1) ||
1147             (dma_chan[lch_queue].dev_id == -1)) {
1148                 printk(KERN_ERR "omap_dma: trying to link "
1149                        "non requested channels\n");
1150                 dump_stack();
1151         }
1152
1153         dma_chan[lch_head].next_lch = lch_queue;
1154 }
1155 EXPORT_SYMBOL(omap_dma_link_lch);
1156
1157 /*
1158  * Once the DMA queue is stopped, we can destroy it.
1159  */
1160 void omap_dma_unlink_lch(int lch_head, int lch_queue)
1161 {
1162         if (omap_dma_in_1510_mode()) {
1163                 if (lch_head == lch_queue) {
1164                         p->dma_write(p->dma_read(CCR, lch_head) & ~(3 << 8),
1165                                                                 CCR, lch_head);
1166                         return;
1167                 }
1168                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1169                 BUG();
1170                 return;
1171         }
1172
1173         if (dma_chan[lch_head].next_lch != lch_queue ||
1174             dma_chan[lch_head].next_lch == -1) {
1175                 printk(KERN_ERR "omap_dma: trying to unlink "
1176                        "non linked channels\n");
1177                 dump_stack();
1178         }
1179
1180         if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
1181             (dma_chan[lch_queue].flags & OMAP_DMA_ACTIVE)) {
1182                 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
1183                        "before unlinking\n");
1184                 dump_stack();
1185         }
1186
1187         dma_chan[lch_head].next_lch = -1;
1188 }
1189 EXPORT_SYMBOL(omap_dma_unlink_lch);
1190
1191 #ifndef CONFIG_ARCH_OMAP1
1192 /* Create chain of DMA channesls */
1193 static void create_dma_lch_chain(int lch_head, int lch_queue)
1194 {
1195         u32 l;
1196
1197         /* Check if this is the first link in chain */
1198         if (dma_chan[lch_head].next_linked_ch == -1) {
1199                 dma_chan[lch_head].next_linked_ch = lch_queue;
1200                 dma_chan[lch_head].prev_linked_ch = lch_queue;
1201                 dma_chan[lch_queue].next_linked_ch = lch_head;
1202                 dma_chan[lch_queue].prev_linked_ch = lch_head;
1203         }
1204
1205         /* a link exists, link the new channel in circular chain */
1206         else {
1207                 dma_chan[lch_queue].next_linked_ch =
1208                                         dma_chan[lch_head].next_linked_ch;
1209                 dma_chan[lch_queue].prev_linked_ch = lch_head;
1210                 dma_chan[lch_head].next_linked_ch = lch_queue;
1211                 dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
1212                                         lch_queue;
1213         }
1214
1215         l = p->dma_read(CLNK_CTRL, lch_head);
1216         l &= ~(0x1f);
1217         l |= lch_queue;
1218         p->dma_write(l, CLNK_CTRL, lch_head);
1219
1220         l = p->dma_read(CLNK_CTRL, lch_queue);
1221         l &= ~(0x1f);
1222         l |= (dma_chan[lch_queue].next_linked_ch);
1223         p->dma_write(l, CLNK_CTRL, lch_queue);
1224 }
1225
1226 /**
1227  * @brief omap_request_dma_chain : Request a chain of DMA channels
1228  *
1229  * @param dev_id - Device id using the dma channel
1230  * @param dev_name - Device name
1231  * @param callback - Call back function
1232  * @chain_id -
1233  * @no_of_chans - Number of channels requested
1234  * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1235  *                                            OMAP_DMA_DYNAMIC_CHAIN
1236  * @params - Channel parameters
1237  *
1238  * @return - Success : 0
1239  *           Failure: -EINVAL/-ENOMEM
1240  */
1241 int omap_request_dma_chain(int dev_id, const char *dev_name,
1242                            void (*callback) (int lch, u16 ch_status,
1243                                              void *data),
1244                            int *chain_id, int no_of_chans, int chain_mode,
1245                            struct omap_dma_channel_params params)
1246 {
1247         int *channels;
1248         int i, err;
1249
1250         /* Is the chain mode valid ? */
1251         if (chain_mode != OMAP_DMA_STATIC_CHAIN
1252                         && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
1253                 printk(KERN_ERR "Invalid chain mode requested\n");
1254                 return -EINVAL;
1255         }
1256
1257         if (unlikely((no_of_chans < 1
1258                         || no_of_chans > dma_lch_count))) {
1259                 printk(KERN_ERR "Invalid Number of channels requested\n");
1260                 return -EINVAL;
1261         }
1262
1263         /*
1264          * Allocate a queue to maintain the status of the channels
1265          * in the chain
1266          */
1267         channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
1268         if (channels == NULL) {
1269                 printk(KERN_ERR "omap_dma: No memory for channel queue\n");
1270                 return -ENOMEM;
1271         }
1272
1273         /* request and reserve DMA channels for the chain */
1274         for (i = 0; i < no_of_chans; i++) {
1275                 err = omap_request_dma(dev_id, dev_name,
1276                                         callback, NULL, &channels[i]);
1277                 if (err < 0) {
1278                         int j;
1279                         for (j = 0; j < i; j++)
1280                                 omap_free_dma(channels[j]);
1281                         kfree(channels);
1282                         printk(KERN_ERR "omap_dma: Request failed %d\n", err);
1283                         return err;
1284                 }
1285                 dma_chan[channels[i]].prev_linked_ch = -1;
1286                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1287
1288                 /*
1289                  * Allowing client drivers to set common parameters now,
1290                  * so that later only relevant (src_start, dest_start
1291                  * and element count) can be set
1292                  */
1293                 omap_set_dma_params(channels[i], &params);
1294         }
1295
1296         *chain_id = channels[0];
1297         dma_linked_lch[*chain_id].linked_dmach_q = channels;
1298         dma_linked_lch[*chain_id].chain_mode = chain_mode;
1299         dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1300         dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;
1301
1302         for (i = 0; i < no_of_chans; i++)
1303                 dma_chan[channels[i]].chain_id = *chain_id;
1304
1305         /* Reset the Queue pointers */
1306         OMAP_DMA_CHAIN_QINIT(*chain_id);
1307
1308         /* Set up the chain */
1309         if (no_of_chans == 1)
1310                 create_dma_lch_chain(channels[0], channels[0]);
1311         else {
1312                 for (i = 0; i < (no_of_chans - 1); i++)
1313                         create_dma_lch_chain(channels[i], channels[i + 1]);
1314         }
1315
1316         return 0;
1317 }
1318 EXPORT_SYMBOL(omap_request_dma_chain);
1319
1320 /**
1321  * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1322  * params after setting it. Dont do this while dma is running!!
1323  *
1324  * @param chain_id - Chained logical channel id.
1325  * @param params
1326  *
1327  * @return - Success : 0
1328  *           Failure : -EINVAL
1329  */
1330 int omap_modify_dma_chain_params(int chain_id,
1331                                 struct omap_dma_channel_params params)
1332 {
1333         int *channels;
1334         u32 i;
1335
1336         /* Check for input params */
1337         if (unlikely((chain_id < 0
1338                         || chain_id >= dma_lch_count))) {
1339                 printk(KERN_ERR "Invalid chain id\n");
1340                 return -EINVAL;
1341         }
1342
1343         /* Check if the chain exists */
1344         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1345                 printk(KERN_ERR "Chain doesn't exists\n");
1346                 return -EINVAL;
1347         }
1348         channels = dma_linked_lch[chain_id].linked_dmach_q;
1349
1350         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1351                 /*
1352                  * Allowing client drivers to set common parameters now,
1353                  * so that later only relevant (src_start, dest_start
1354                  * and element count) can be set
1355                  */
1356                 omap_set_dma_params(channels[i], &params);
1357         }
1358
1359         return 0;
1360 }
1361 EXPORT_SYMBOL(omap_modify_dma_chain_params);
1362
1363 /**
1364  * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1365  *
1366  * @param chain_id
1367  *
1368  * @return - Success : 0
1369  *           Failure : -EINVAL
1370  */
1371 int omap_free_dma_chain(int chain_id)
1372 {
1373         int *channels;
1374         u32 i;
1375
1376         /* Check for input params */
1377         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1378                 printk(KERN_ERR "Invalid chain id\n");
1379                 return -EINVAL;
1380         }
1381
1382         /* Check if the chain exists */
1383         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1384                 printk(KERN_ERR "Chain doesn't exists\n");
1385                 return -EINVAL;
1386         }
1387
1388         channels = dma_linked_lch[chain_id].linked_dmach_q;
1389         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1390                 dma_chan[channels[i]].next_linked_ch = -1;
1391                 dma_chan[channels[i]].prev_linked_ch = -1;
1392                 dma_chan[channels[i]].chain_id = -1;
1393                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1394                 omap_free_dma(channels[i]);
1395         }
1396
1397         kfree(channels);
1398
1399         dma_linked_lch[chain_id].linked_dmach_q = NULL;
1400         dma_linked_lch[chain_id].chain_mode = -1;
1401         dma_linked_lch[chain_id].chain_state = -1;
1402
1403         return (0);
1404 }
1405 EXPORT_SYMBOL(omap_free_dma_chain);
1406
1407 /**
1408  * @brief omap_dma_chain_status - Check if the chain is in
1409  * active / inactive state.
1410  * @param chain_id
1411  *
1412  * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1413  *           Failure : -EINVAL
1414  */
1415 int omap_dma_chain_status(int chain_id)
1416 {
1417         /* Check for input params */
1418         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1419                 printk(KERN_ERR "Invalid chain id\n");
1420                 return -EINVAL;
1421         }
1422
1423         /* Check if the chain exists */
1424         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1425                 printk(KERN_ERR "Chain doesn't exists\n");
1426                 return -EINVAL;
1427         }
1428         pr_debug("CHAINID=%d, qcnt=%d\n", chain_id,
1429                         dma_linked_lch[chain_id].q_count);
1430
1431         if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
1432                 return OMAP_DMA_CHAIN_INACTIVE;
1433
1434         return OMAP_DMA_CHAIN_ACTIVE;
1435 }
1436 EXPORT_SYMBOL(omap_dma_chain_status);
1437
1438 /**
1439  * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1440  * set the params and start the transfer.
1441  *
1442  * @param chain_id
1443  * @param src_start - buffer start address
1444  * @param dest_start - Dest address
1445  * @param elem_count
1446  * @param frame_count
1447  * @param callbk_data - channel callback parameter data.
1448  *
1449  * @return  - Success : 0
1450  *            Failure: -EINVAL/-EBUSY
1451  */
1452 int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1453                         int elem_count, int frame_count, void *callbk_data)
1454 {
1455         int *channels;
1456         u32 l, lch;
1457         int start_dma = 0;
1458
1459         /*
1460          * if buffer size is less than 1 then there is
1461          * no use of starting the chain
1462          */
1463         if (elem_count < 1) {
1464                 printk(KERN_ERR "Invalid buffer size\n");
1465                 return -EINVAL;
1466         }
1467
1468         /* Check for input params */
1469         if (unlikely((chain_id < 0
1470                         || chain_id >= dma_lch_count))) {
1471                 printk(KERN_ERR "Invalid chain id\n");
1472                 return -EINVAL;
1473         }
1474
1475         /* Check if the chain exists */
1476         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1477                 printk(KERN_ERR "Chain doesn't exist\n");
1478                 return -EINVAL;
1479         }
1480
1481         /* Check if all the channels in chain are in use */
1482         if (OMAP_DMA_CHAIN_QFULL(chain_id))
1483                 return -EBUSY;
1484
1485         /* Frame count may be negative in case of indexed transfers */
1486         channels = dma_linked_lch[chain_id].linked_dmach_q;
1487
1488         /* Get a free channel */
1489         lch = channels[dma_linked_lch[chain_id].q_tail];
1490
1491         /* Store the callback data */
1492         dma_chan[lch].data = callbk_data;
1493
1494         /* Increment the q_tail */
1495         OMAP_DMA_CHAIN_INCQTAIL(chain_id);
1496
1497         /* Set the params to the free channel */
1498         if (src_start != 0)
1499                 p->dma_write(src_start, CSSA, lch);
1500         if (dest_start != 0)
1501                 p->dma_write(dest_start, CDSA, lch);
1502
1503         /* Write the buffer size */
1504         p->dma_write(elem_count, CEN, lch);
1505         p->dma_write(frame_count, CFN, lch);
1506
1507         /*
1508          * If the chain is dynamically linked,
1509          * then we may have to start the chain if its not active
1510          */
1511         if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
1512
1513                 /*
1514                  * In Dynamic chain, if the chain is not started,
1515                  * queue the channel
1516                  */
1517                 if (dma_linked_lch[chain_id].chain_state ==
1518                                                 DMA_CHAIN_NOTSTARTED) {
1519                         /* Enable the link in previous channel */
1520                         if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1521                                                                 DMA_CH_QUEUED)
1522                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1523                         dma_chan[lch].state = DMA_CH_QUEUED;
1524                 }
1525
1526                 /*
1527                  * Chain is already started, make sure its active,
1528                  * if not then start the chain
1529                  */
1530                 else {
1531                         start_dma = 1;
1532
1533                         if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1534                                                         DMA_CH_STARTED) {
1535                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1536                                 dma_chan[lch].state = DMA_CH_QUEUED;
1537                                 start_dma = 0;
1538                                 if (0 == ((1 << 7) & p->dma_read(
1539                                         CCR, dma_chan[lch].prev_linked_ch))) {
1540                                         disable_lnk(dma_chan[lch].
1541                                                     prev_linked_ch);
1542                                         pr_debug("\n prev ch is stopped\n");
1543                                         start_dma = 1;
1544                                 }
1545                         }
1546
1547                         else if (dma_chan[dma_chan[lch].prev_linked_ch].state
1548                                                         == DMA_CH_QUEUED) {
1549                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1550                                 dma_chan[lch].state = DMA_CH_QUEUED;
1551                                 start_dma = 0;
1552                         }
1553                         omap_enable_channel_irq(lch);
1554
1555                         l = p->dma_read(CCR, lch);
1556
1557                         if ((0 == (l & (1 << 24))))
1558                                 l &= ~(1 << 25);
1559                         else
1560                                 l |= (1 << 25);
1561                         if (start_dma == 1) {
1562                                 if (0 == (l & (1 << 7))) {
1563                                         l |= (1 << 7);
1564                                         dma_chan[lch].state = DMA_CH_STARTED;
1565                                         pr_debug("starting %d\n", lch);
1566                                         p->dma_write(l, CCR, lch);
1567                                 } else
1568                                         start_dma = 0;
1569                         } else {
1570                                 if (0 == (l & (1 << 7)))
1571                                         p->dma_write(l, CCR, lch);
1572                         }
1573                         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1574                 }
1575         }
1576
1577         return 0;
1578 }
1579 EXPORT_SYMBOL(omap_dma_chain_a_transfer);
1580
1581 /**
1582  * @brief omap_start_dma_chain_transfers - Start the chain
1583  *
1584  * @param chain_id
1585  *
1586  * @return - Success : 0
1587  *           Failure : -EINVAL/-EBUSY
1588  */
1589 int omap_start_dma_chain_transfers(int chain_id)
1590 {
1591         int *channels;
1592         u32 l, i;
1593
1594         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1595                 printk(KERN_ERR "Invalid chain id\n");
1596                 return -EINVAL;
1597         }
1598
1599         channels = dma_linked_lch[chain_id].linked_dmach_q;
1600
1601         if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
1602                 printk(KERN_ERR "Chain is already started\n");
1603                 return -EBUSY;
1604         }
1605
1606         if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
1607                 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
1608                                                                         i++) {
1609                         enable_lnk(channels[i]);
1610                         omap_enable_channel_irq(channels[i]);
1611                 }
1612         } else {
1613                 omap_enable_channel_irq(channels[0]);
1614         }
1615
1616         l = p->dma_read(CCR, channels[0]);
1617         l |= (1 << 7);
1618         dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
1619         dma_chan[channels[0]].state = DMA_CH_STARTED;
1620
1621         if ((0 == (l & (1 << 24))))
1622                 l &= ~(1 << 25);
1623         else
1624                 l |= (1 << 25);
1625         p->dma_write(l, CCR, channels[0]);
1626
1627         dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
1628
1629         return 0;
1630 }
1631 EXPORT_SYMBOL(omap_start_dma_chain_transfers);
1632
1633 /**
1634  * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1635  *
1636  * @param chain_id
1637  *
1638  * @return - Success : 0
1639  *           Failure : EINVAL
1640  */
1641 int omap_stop_dma_chain_transfers(int chain_id)
1642 {
1643         int *channels;
1644         u32 l, i;
1645         u32 sys_cf = 0;
1646
1647         /* Check for input params */
1648         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1649                 printk(KERN_ERR "Invalid chain id\n");
1650                 return -EINVAL;
1651         }
1652
1653         /* Check if the chain exists */
1654         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1655                 printk(KERN_ERR "Chain doesn't exists\n");
1656                 return -EINVAL;
1657         }
1658         channels = dma_linked_lch[chain_id].linked_dmach_q;
1659
1660         if (IS_DMA_ERRATA(DMA_ERRATA_i88)) {
1661                 sys_cf = p->dma_read(OCP_SYSCONFIG, 0);
1662                 l = sys_cf;
1663                 /* Middle mode reg set no Standby */
1664                 l &= ~((1 << 12)|(1 << 13));
1665                 p->dma_write(l, OCP_SYSCONFIG, 0);
1666         }
1667
1668         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1669
1670                 /* Stop the Channel transmission */
1671                 l = p->dma_read(CCR, channels[i]);
1672                 l &= ~(1 << 7);
1673                 p->dma_write(l, CCR, channels[i]);
1674
1675                 /* Disable the link in all the channels */
1676                 disable_lnk(channels[i]);
1677                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1678
1679         }
1680         dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1681
1682         /* Reset the Queue pointers */
1683         OMAP_DMA_CHAIN_QINIT(chain_id);
1684
1685         if (IS_DMA_ERRATA(DMA_ERRATA_i88))
1686                 p->dma_write(sys_cf, OCP_SYSCONFIG, 0);
1687
1688         return 0;
1689 }
1690 EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
1691
1692 /* Get the index of the ongoing DMA in chain */
1693 /**
1694  * @brief omap_get_dma_chain_index - Get the element and frame index
1695  * of the ongoing DMA in chain
1696  *
1697  * @param chain_id
1698  * @param ei - Element index
1699  * @param fi - Frame index
1700  *
1701  * @return - Success : 0
1702  *           Failure : -EINVAL
1703  */
1704 int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1705 {
1706         int lch;
1707         int *channels;
1708
1709         /* Check for input params */
1710         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1711                 printk(KERN_ERR "Invalid chain id\n");
1712                 return -EINVAL;
1713         }
1714
1715         /* Check if the chain exists */
1716         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1717                 printk(KERN_ERR "Chain doesn't exists\n");
1718                 return -EINVAL;
1719         }
1720         if ((!ei) || (!fi))
1721                 return -EINVAL;
1722
1723         channels = dma_linked_lch[chain_id].linked_dmach_q;
1724
1725         /* Get the current channel */
1726         lch = channels[dma_linked_lch[chain_id].q_head];
1727
1728         *ei = p->dma_read(CCEN, lch);
1729         *fi = p->dma_read(CCFN, lch);
1730
1731         return 0;
1732 }
1733 EXPORT_SYMBOL(omap_get_dma_chain_index);
1734
1735 /**
1736  * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1737  * ongoing DMA in chain
1738  *
1739  * @param chain_id
1740  *
1741  * @return - Success : Destination position
1742  *           Failure : -EINVAL
1743  */
1744 int omap_get_dma_chain_dst_pos(int chain_id)
1745 {
1746         int lch;
1747         int *channels;
1748
1749         /* Check for input params */
1750         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1751                 printk(KERN_ERR "Invalid chain id\n");
1752                 return -EINVAL;
1753         }
1754
1755         /* Check if the chain exists */
1756         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1757                 printk(KERN_ERR "Chain doesn't exists\n");
1758                 return -EINVAL;
1759         }
1760
1761         channels = dma_linked_lch[chain_id].linked_dmach_q;
1762
1763         /* Get the current channel */
1764         lch = channels[dma_linked_lch[chain_id].q_head];
1765
1766         return p->dma_read(CDAC, lch);
1767 }
1768 EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
1769
1770 /**
1771  * @brief omap_get_dma_chain_src_pos - Get the source position
1772  * of the ongoing DMA in chain
1773  * @param chain_id
1774  *
1775  * @return - Success : Destination position
1776  *           Failure : -EINVAL
1777  */
1778 int omap_get_dma_chain_src_pos(int chain_id)
1779 {
1780         int lch;
1781         int *channels;
1782
1783         /* Check for input params */
1784         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1785                 printk(KERN_ERR "Invalid chain id\n");
1786                 return -EINVAL;
1787         }
1788
1789         /* Check if the chain exists */
1790         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1791                 printk(KERN_ERR "Chain doesn't exists\n");
1792                 return -EINVAL;
1793         }
1794
1795         channels = dma_linked_lch[chain_id].linked_dmach_q;
1796
1797         /* Get the current channel */
1798         lch = channels[dma_linked_lch[chain_id].q_head];
1799
1800         return p->dma_read(CSAC, lch);
1801 }
1802 EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
1803 #endif  /* ifndef CONFIG_ARCH_OMAP1 */
1804
1805 /*----------------------------------------------------------------------------*/
1806
1807 #ifdef CONFIG_ARCH_OMAP1
1808
1809 static int omap1_dma_handle_ch(int ch)
1810 {
1811         u32 csr;
1812
1813         if (enable_1510_mode && ch >= 6) {
1814                 csr = dma_chan[ch].saved_csr;
1815                 dma_chan[ch].saved_csr = 0;
1816         } else
1817                 csr = p->dma_read(CSR, ch);
1818         if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1819                 dma_chan[ch + 6].saved_csr = csr >> 7;
1820                 csr &= 0x7f;
1821         }
1822         if ((csr & 0x3f) == 0)
1823                 return 0;
1824         if (unlikely(dma_chan[ch].dev_id == -1)) {
1825                 printk(KERN_WARNING "Spurious interrupt from DMA channel "
1826                        "%d (CSR %04x)\n", ch, csr);
1827                 return 0;
1828         }
1829         if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
1830                 printk(KERN_WARNING "DMA timeout with device %d\n",
1831                        dma_chan[ch].dev_id);
1832         if (unlikely(csr & OMAP_DMA_DROP_IRQ))
1833                 printk(KERN_WARNING "DMA synchronization event drop occurred "
1834                        "with device %d\n", dma_chan[ch].dev_id);
1835         if (likely(csr & OMAP_DMA_BLOCK_IRQ))
1836                 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1837         if (likely(dma_chan[ch].callback != NULL))
1838                 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
1839
1840         return 1;
1841 }
1842
1843 static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1844 {
1845         int ch = ((int) dev_id) - 1;
1846         int handled = 0;
1847
1848         for (;;) {
1849                 int handled_now = 0;
1850
1851                 handled_now += omap1_dma_handle_ch(ch);
1852                 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
1853                         handled_now += omap1_dma_handle_ch(ch + 6);
1854                 if (!handled_now)
1855                         break;
1856                 handled += handled_now;
1857         }
1858
1859         return handled ? IRQ_HANDLED : IRQ_NONE;
1860 }
1861
1862 #else
1863 #define omap1_dma_irq_handler   NULL
1864 #endif
1865
1866 #ifdef CONFIG_ARCH_OMAP2PLUS
1867
1868 static int omap2_dma_handle_ch(int ch)
1869 {
1870         u32 status = p->dma_read(CSR, ch);
1871
1872         if (!status) {
1873                 if (printk_ratelimit())
1874                         printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
1875                                 ch);
1876                 p->dma_write(1 << ch, IRQSTATUS_L0, ch);
1877                 return 0;
1878         }
1879         if (unlikely(dma_chan[ch].dev_id == -1)) {
1880                 if (printk_ratelimit())
1881                         printk(KERN_WARNING "IRQ %04x for non-allocated DMA"
1882                                         "channel %d\n", status, ch);
1883                 return 0;
1884         }
1885         if (unlikely(status & OMAP_DMA_DROP_IRQ))
1886                 printk(KERN_INFO
1887                        "DMA synchronization event drop occurred with device "
1888                        "%d\n", dma_chan[ch].dev_id);
1889         if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
1890                 printk(KERN_INFO "DMA transaction error with device %d\n",
1891                        dma_chan[ch].dev_id);
1892                 if (IS_DMA_ERRATA(DMA_ERRATA_i378)) {
1893                         u32 ccr;
1894
1895                         ccr = p->dma_read(CCR, ch);
1896                         ccr &= ~OMAP_DMA_CCR_EN;
1897                         p->dma_write(ccr, CCR, ch);
1898                         dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1899                 }
1900         }
1901         if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
1902                 printk(KERN_INFO "DMA secure error with device %d\n",
1903                        dma_chan[ch].dev_id);
1904         if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
1905                 printk(KERN_INFO "DMA misaligned error with device %d\n",
1906                        dma_chan[ch].dev_id);
1907
1908         p->dma_write(status, CSR, ch);
1909         p->dma_write(1 << ch, IRQSTATUS_L0, ch);
1910         /* read back the register to flush the write */
1911         p->dma_read(IRQSTATUS_L0, ch);
1912
1913         /* If the ch is not chained then chain_id will be -1 */
1914         if (dma_chan[ch].chain_id != -1) {
1915                 int chain_id = dma_chan[ch].chain_id;
1916                 dma_chan[ch].state = DMA_CH_NOTSTARTED;
1917                 if (p->dma_read(CLNK_CTRL, ch) & (1 << 15))
1918                         dma_chan[dma_chan[ch].next_linked_ch].state =
1919                                                         DMA_CH_STARTED;
1920                 if (dma_linked_lch[chain_id].chain_mode ==
1921                                                 OMAP_DMA_DYNAMIC_CHAIN)
1922                         disable_lnk(ch);
1923
1924                 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1925                         OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1926
1927                 status = p->dma_read(CSR, ch);
1928                 p->dma_write(status, CSR, ch);
1929         }
1930
1931         if (likely(dma_chan[ch].callback != NULL))
1932                 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1933
1934         return 0;
1935 }
1936
1937 /* STATUS register count is from 1-32 while our is 0-31 */
1938 static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1939 {
1940         u32 val, enable_reg;
1941         int i;
1942
1943         val = p->dma_read(IRQSTATUS_L0, 0);
1944         if (val == 0) {
1945                 if (printk_ratelimit())
1946                         printk(KERN_WARNING "Spurious DMA IRQ\n");
1947                 return IRQ_HANDLED;
1948         }
1949         enable_reg = p->dma_read(IRQENABLE_L0, 0);
1950         val &= enable_reg; /* Dispatch only relevant interrupts */
1951         for (i = 0; i < dma_lch_count && val != 0; i++) {
1952                 if (val & 1)
1953                         omap2_dma_handle_ch(i);
1954                 val >>= 1;
1955         }
1956
1957         return IRQ_HANDLED;
1958 }
1959
1960 static struct irqaction omap24xx_dma_irq = {
1961         .name = "DMA",
1962         .handler = omap2_dma_irq_handler,
1963         .flags = IRQF_DISABLED
1964 };
1965
1966 #else
1967 static struct irqaction omap24xx_dma_irq;
1968 #endif
1969
1970 /*----------------------------------------------------------------------------*/
1971
1972 void omap_dma_global_context_save(void)
1973 {
1974         omap_dma_global_context.dma_irqenable_l0 =
1975                 p->dma_read(IRQENABLE_L0, 0);
1976         omap_dma_global_context.dma_ocp_sysconfig =
1977                 p->dma_read(OCP_SYSCONFIG, 0);
1978         omap_dma_global_context.dma_gcr = p->dma_read(GCR, 0);
1979 }
1980
1981 void omap_dma_global_context_restore(void)
1982 {
1983         int ch;
1984
1985         p->dma_write(omap_dma_global_context.dma_gcr, GCR, 0);
1986         p->dma_write(omap_dma_global_context.dma_ocp_sysconfig,
1987                 OCP_SYSCONFIG, 0);
1988         p->dma_write(omap_dma_global_context.dma_irqenable_l0,
1989                 IRQENABLE_L0, 0);
1990
1991         if (IS_DMA_ERRATA(DMA_ROMCODE_BUG))
1992                 p->dma_write(0x3 , IRQSTATUS_L0, 0);
1993
1994         for (ch = 0; ch < dma_chan_count; ch++)
1995                 if (dma_chan[ch].dev_id != -1)
1996                         omap_clear_dma(ch);
1997 }
1998
1999 static int __devinit omap_system_dma_probe(struct platform_device *pdev)
2000 {
2001         int ch, ret = 0;
2002         int dma_irq;
2003         char irq_name[4];
2004         int irq_rel;
2005
2006         p = pdev->dev.platform_data;
2007         if (!p) {
2008                 dev_err(&pdev->dev, "%s: System DMA initialized without"
2009                         "platform data\n", __func__);
2010                 return -EINVAL;
2011         }
2012
2013         d                       = p->dma_attr;
2014         errata                  = p->errata;
2015
2016         if ((d->dev_caps & RESERVE_CHANNEL) && omap_dma_reserve_channels
2017                         && (omap_dma_reserve_channels < d->lch_count))
2018                 d->lch_count    = omap_dma_reserve_channels;
2019
2020         dma_lch_count           = d->lch_count;
2021         dma_chan_count          = dma_lch_count;
2022         dma_chan                = d->chan;
2023         enable_1510_mode        = d->dev_caps & ENABLE_1510_MODE;
2024
2025         if (cpu_class_is_omap2()) {
2026                 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
2027                                                 dma_lch_count, GFP_KERNEL);
2028                 if (!dma_linked_lch) {
2029                         ret = -ENOMEM;
2030                         goto exit_dma_lch_fail;
2031                 }
2032         }
2033
2034         spin_lock_init(&dma_chan_lock);
2035         for (ch = 0; ch < dma_chan_count; ch++) {
2036                 omap_clear_dma(ch);
2037                 if (cpu_class_is_omap2())
2038                         omap2_disable_irq_lch(ch);
2039
2040                 dma_chan[ch].dev_id = -1;
2041                 dma_chan[ch].next_lch = -1;
2042
2043                 if (ch >= 6 && enable_1510_mode)
2044                         continue;
2045
2046                 if (cpu_class_is_omap1()) {
2047                         /*
2048                          * request_irq() doesn't like dev_id (ie. ch) being
2049                          * zero, so we have to kludge around this.
2050                          */
2051                         sprintf(&irq_name[0], "%d", ch);
2052                         dma_irq = platform_get_irq_byname(pdev, irq_name);
2053
2054                         if (dma_irq < 0) {
2055                                 ret = dma_irq;
2056                                 goto exit_dma_irq_fail;
2057                         }
2058
2059                         /* INT_DMA_LCD is handled in lcd_dma.c */
2060                         if (dma_irq == INT_DMA_LCD)
2061                                 continue;
2062
2063                         ret = request_irq(dma_irq,
2064                                         omap1_dma_irq_handler, 0, "DMA",
2065                                         (void *) (ch + 1));
2066                         if (ret != 0)
2067                                 goto exit_dma_irq_fail;
2068                 }
2069         }
2070
2071         if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx())
2072                 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
2073                                 DMA_DEFAULT_FIFO_DEPTH, 0);
2074
2075         if (cpu_class_is_omap2()) {
2076                 strcpy(irq_name, "0");
2077                 dma_irq = platform_get_irq_byname(pdev, irq_name);
2078                 if (dma_irq < 0) {
2079                         dev_err(&pdev->dev, "failed: request IRQ %d", dma_irq);
2080                         goto exit_dma_lch_fail;
2081                 }
2082                 ret = setup_irq(dma_irq, &omap24xx_dma_irq);
2083                 if (ret) {
2084                         dev_err(&pdev->dev, "set_up failed for IRQ %d"
2085                                 "for DMA (error %d)\n", dma_irq, ret);
2086                         goto exit_dma_lch_fail;
2087                 }
2088         }
2089
2090         /* reserve dma channels 0 and 1 in high security devices */
2091         if (cpu_is_omap34xx() &&
2092                 (omap_type() != OMAP2_DEVICE_TYPE_GP)) {
2093                 printk(KERN_INFO "Reserving DMA channels 0 and 1 for "
2094                                 "HS ROM code\n");
2095                 dma_chan[0].dev_id = 0;
2096                 dma_chan[1].dev_id = 1;
2097         }
2098         p->show_dma_caps();
2099         return 0;
2100
2101 exit_dma_irq_fail:
2102         dev_err(&pdev->dev, "unable to request IRQ %d"
2103                         "for DMA (error %d)\n", dma_irq, ret);
2104         for (irq_rel = 0; irq_rel < ch; irq_rel++) {
2105                 dma_irq = platform_get_irq(pdev, irq_rel);
2106                 free_irq(dma_irq, (void *)(irq_rel + 1));
2107         }
2108
2109 exit_dma_lch_fail:
2110         kfree(dma_chan);
2111         return ret;
2112 }
2113
2114 static int __devexit omap_system_dma_remove(struct platform_device *pdev)
2115 {
2116         int dma_irq;
2117
2118         if (cpu_class_is_omap2()) {
2119                 char irq_name[4];
2120                 strcpy(irq_name, "0");
2121                 dma_irq = platform_get_irq_byname(pdev, irq_name);
2122                 remove_irq(dma_irq, &omap24xx_dma_irq);
2123         } else {
2124                 int irq_rel = 0;
2125                 for ( ; irq_rel < dma_chan_count; irq_rel++) {
2126                         dma_irq = platform_get_irq(pdev, irq_rel);
2127                         free_irq(dma_irq, (void *)(irq_rel + 1));
2128                 }
2129         }
2130         kfree(dma_chan);
2131         return 0;
2132 }
2133
2134 static struct platform_driver omap_system_dma_driver = {
2135         .probe          = omap_system_dma_probe,
2136         .remove         = omap_system_dma_remove,
2137         .driver         = {
2138                 .name   = "omap_dma_system"
2139         },
2140 };
2141
2142 static int __init omap_system_dma_init(void)
2143 {
2144         return platform_driver_register(&omap_system_dma_driver);
2145 }
2146 arch_initcall(omap_system_dma_init);
2147
2148 static void __exit omap_system_dma_exit(void)
2149 {
2150         platform_driver_unregister(&omap_system_dma_driver);
2151 }
2152
2153 MODULE_DESCRIPTION("OMAP SYSTEM DMA DRIVER");
2154 MODULE_LICENSE("GPL");
2155 MODULE_ALIAS("platform:" DRIVER_NAME);
2156 MODULE_AUTHOR("Texas Instruments Inc");
2157
2158 /*
2159  * Reserve the omap SDMA channels using cmdline bootarg
2160  * "omap_dma_reserve_ch=". The valid range is 1 to 32
2161  */
2162 static int __init omap_dma_cmdline_reserve_ch(char *str)
2163 {
2164         if (get_option(&str, &omap_dma_reserve_channels) != 1)
2165                 omap_dma_reserve_channels = 0;
2166         return 1;
2167 }
2168
2169 __setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch);
2170
2171