arch/arm/plat-omap/dma.c

   1 /*
   2  * linux/arch/arm/plat-omap/dma.c
   3  *
   4  * Copyright (C) 2003 - 2008 Nokia Corporation
   5  * Author: Juha Yrjölä <juha.yrjola@nokia.com>
   6  * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
   7  * Graphics DMA and LCD DMA graphics tranformations
   8  * by Imre Deak <imre.deak@nokia.com>
   9  * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
  10  * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
  11  * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
  12  *
  13  * Copyright (C) 2009 Texas Instruments
  14  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  15  *
  16  * Support functions for the OMAP internal DMA channels.
  17  *
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License version 2 as
  20  * published by the Free Software Foundation.
  21  *
  22  */
  23
  24 #include <linux/module.h>
  25 #include <linux/init.h>
  26 #include <linux/sched.h>
  27 #include <linux/spinlock.h>
  28 #include <linux/errno.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/irq.h>
  31 #include <linux/io.h>
  32
  33 #include <asm/system.h>
  34 #include <mach/hardware.h>
  35 #include <mach/dma.h>
  36
  37 #include <mach/tc.h>
  38
  39 #undef DEBUG
  40
  41 #ifndef CONFIG_ARCH_OMAP1
  42 enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
  43         DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
  44 };
  45
  46 enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
  47 #endif
  48
  49 #define OMAP_DMA_ACTIVE                 0x01
  50 #define OMAP_DMA_CCR_EN                 (1 << 7)
  51 #define OMAP2_DMA_CSR_CLEAR_MASK        0xffe
  52
  53 #define OMAP_FUNC_MUX_ARM_BASE          (0xfffe1000 + 0xec)
  54
  55 static int enable_1510_mode;
  56
  57 struct omap_dma_lch {
  58         int next_lch;
  59         int dev_id;
  60         u16 saved_csr;
  61         u16 enabled_irqs;
  62         const char *dev_name;
  63         void (*callback)(int lch, u16 ch_status, void *data);
  64         void *data;
  65
  66 #ifndef CONFIG_ARCH_OMAP1
  67         /* required for Dynamic chaining */
  68         int prev_linked_ch;
  69         int next_linked_ch;
  70         int state;
  71         int chain_id;
  72
  73         int status;
  74 #endif
  75         long flags;
  76 };
  77
  78 struct dma_link_info {
  79         int *linked_dmach_q;
  80         int no_of_lchs_linked;
  81
  82         int q_count;
  83         int q_tail;
  84         int q_head;
  85
  86         int chain_state;
  87         int chain_mode;
  88
  89 };
  90
  91 static struct dma_link_info *dma_linked_lch;
  92
  93 #ifndef CONFIG_ARCH_OMAP1
  94
  95 /* Chain handling macros */
  96 #define OMAP_DMA_CHAIN_QINIT(chain_id)                                  \
  97         do {                                                            \
  98                 dma_linked_lch[chain_id].q_head =                       \
  99                 dma_linked_lch[chain_id].q_tail =                       \
 100                 dma_linked_lch[chain_id].q_count = 0;                   \
 101         } while (0)
 102 #define OMAP_DMA_CHAIN_QFULL(chain_id)                                  \
 103                 (dma_linked_lch[chain_id].no_of_lchs_linked ==          \
 104                 dma_linked_lch[chain_id].q_count)
 105 #define OMAP_DMA_CHAIN_QLAST(chain_id)                                  \
 106         do {                                                            \
 107                 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) ==      \
 108                 dma_linked_lch[chain_id].q_count)                       \
 109         } while (0)
 110 #define OMAP_DMA_CHAIN_QEMPTY(chain_id)                                 \
 111                 (0 == dma_linked_lch[chain_id].q_count)
 112 #define __OMAP_DMA_CHAIN_INCQ(end)                                      \
 113         ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
 114 #define OMAP_DMA_CHAIN_INCQHEAD(chain_id)                               \
 115         do {                                                            \
 116                 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
 117                 dma_linked_lch[chain_id].q_count--;                     \
 118         } while (0)
 119
 120 #define OMAP_DMA_CHAIN_INCQTAIL(chain_id)                               \
 121         do {                                                            \
 122                 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
 123                 dma_linked_lch[chain_id].q_count++; \
 124         } while (0)
 125 #endif
 126
 127 static int dma_lch_count;
 128 static int dma_chan_count;
 129 static int omap_dma_reserve_channels;
 130
 131 static spinlock_t dma_chan_lock;
 132 static struct omap_dma_lch *dma_chan;
 133 static void __iomem *omap_dma_base;
 134
 135 static const u8 omap1_dma_irq[OMAP1_LOGICAL_DMA_CH_COUNT] = {
 136         INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3,
 137         INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7,
 138         INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10,
 139         INT_1610_DMA_CH11, INT_1610_DMA_CH12, INT_1610_DMA_CH13,
 140         INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD
 141 };
 142
 143 static inline void disable_lnk(int lch);
 144 static void omap_disable_channel_irq(int lch);
 145 static inline void omap_enable_channel_irq(int lch);
 146
 147 #define REVISIT_24XX()          printk(KERN_ERR "FIXME: no %s on 24xx\n", \
 148                                                 __func__);
 149
 150 #define dma_read(reg)                                                   \
 151 ({                                                                      \
 152         u32 __val;                                                      \
 153         if (cpu_class_is_omap1())                                       \
 154                 __val = __raw_readw(omap_dma_base + OMAP1_DMA_##reg);   \
 155         else                                                            \
 156                 __val = __raw_readl(omap_dma_base + OMAP_DMA4_##reg);   \
 157         __val;                                                          \
 158 })
 159
 160 #define dma_write(val, reg)                                             \
 161 ({                                                                      \
 162         if (cpu_class_is_omap1())                                       \
 163                 __raw_writew((u16)(val), omap_dma_base + OMAP1_DMA_##reg); \
 164         else                                                            \
 165                 __raw_writel((val), omap_dma_base + OMAP_DMA4_##reg);   \
 166 })
 167
 168 #ifdef CONFIG_ARCH_OMAP15XX
 169 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
 170 int omap_dma_in_1510_mode(void)
 171 {
 172         return enable_1510_mode;
 173 }
 174 #else
 175 #define omap_dma_in_1510_mode()         0
 176 #endif
 177
 178 #ifdef CONFIG_ARCH_OMAP1
 179 static inline int get_gdma_dev(int req)
 180 {
 181         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
 182         int shift = ((req - 1) % 5) * 6;
 183
 184         return ((omap_readl(reg) >> shift) & 0x3f) + 1;
 185 }
 186
 187 static inline void set_gdma_dev(int req, int dev)
 188 {
 189         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
 190         int shift = ((req - 1) % 5) * 6;
 191         u32 l;
 192
 193         l = omap_readl(reg);
 194         l &= ~(0x3f << shift);
 195         l |= (dev - 1) << shift;
 196         omap_writel(l, reg);
 197 }
 198 #else
 199 #define set_gdma_dev(req, dev)  do {} while (0)
 200 #endif
 201
 202 /* Omap1 only */
 203 static void clear_lch_regs(int lch)
 204 {
 205         int i;
 206         void __iomem *lch_base = omap_dma_base + OMAP1_DMA_CH_BASE(lch);
 207
 208         for (i = 0; i < 0x2c; i += 2)
 209                 __raw_writew(0, lch_base + i);
 210 }
 211
 212 void omap_set_dma_priority(int lch, int dst_port, int priority)
 213 {
 214         unsigned long reg;
 215         u32 l;
 216
 217         if (cpu_class_is_omap1()) {
 218                 switch (dst_port) {
 219                 case OMAP_DMA_PORT_OCP_T1:      /* FFFECC00 */
 220                         reg = OMAP_TC_OCPT1_PRIOR;
 221                         break;
 222                 case OMAP_DMA_PORT_OCP_T2:      /* FFFECCD0 */
 223                         reg = OMAP_TC_OCPT2_PRIOR;
 224                         break;
 225                 case OMAP_DMA_PORT_EMIFF:       /* FFFECC08 */
 226                         reg = OMAP_TC_EMIFF_PRIOR;
 227                         break;
 228                 case OMAP_DMA_PORT_EMIFS:       /* FFFECC04 */
 229                         reg = OMAP_TC_EMIFS_PRIOR;
 230                         break;
 231                 default:
 232                         BUG();
 233                         return;
 234                 }
 235                 l = omap_readl(reg);
 236                 l &= ~(0xf << 8);
 237                 l |= (priority & 0xf) << 8;
 238                 omap_writel(l, reg);
 239         }
 240
 241         if (cpu_class_is_omap2()) {
 242                 u32 ccr;
 243
 244                 ccr = dma_read(CCR(lch));
 245                 if (priority)
 246                         ccr |= (1 << 6);
 247                 else
 248                         ccr &= ~(1 << 6);
 249                 dma_write(ccr, CCR(lch));
 250         }
 251 }
 252 EXPORT_SYMBOL(omap_set_dma_priority);
 253
 254 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
 255                                   int frame_count, int sync_mode,
 256                                   int dma_trigger, int src_or_dst_synch)
 257 {
 258         u32 l;
 259
 260         l = dma_read(CSDP(lch));
 261         l &= ~0x03;
 262         l |= data_type;
 263         dma_write(l, CSDP(lch));
 264
 265         if (cpu_class_is_omap1()) {
 266                 u16 ccr;
 267
 268                 ccr = dma_read(CCR(lch));
 269                 ccr &= ~(1 << 5);
 270                 if (sync_mode == OMAP_DMA_SYNC_FRAME)
 271                         ccr |= 1 << 5;
 272                 dma_write(ccr, CCR(lch));
 273
 274                 ccr = dma_read(CCR2(lch));
 275                 ccr &= ~(1 << 2);
 276                 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
 277                         ccr |= 1 << 2;
 278                 dma_write(ccr, CCR2(lch));
 279         }
 280
 281         if (cpu_class_is_omap2() && dma_trigger) {
 282                 u32 val;
 283
 284                 val = dma_read(CCR(lch));
 285
 286                 /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
 287                 val &= ~((3 << 19) | 0x1f);
 288                 val |= (dma_trigger & ~0x1f) << 14;
 289                 val |= dma_trigger & 0x1f;
 290
 291                 if (sync_mode & OMAP_DMA_SYNC_FRAME)
 292                         val |= 1 << 5;
 293                 else
 294                         val &= ~(1 << 5);
 295
 296                 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
 297                         val |= 1 << 18;
 298                 else
 299                         val &= ~(1 << 18);
 300
 301                 if (src_or_dst_synch)
 302                         val |= 1 << 24;         /* source synch */
 303                 else
 304                         val &= ~(1 << 24);      /* dest synch */
 305
 306                 dma_write(val, CCR(lch));
 307         }
 308
 309         dma_write(elem_count, CEN(lch));
 310         dma_write(frame_count, CFN(lch));
 311 }
 312 EXPORT_SYMBOL(omap_set_dma_transfer_params);
 313
 314 void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
 315 {
 316         BUG_ON(omap_dma_in_1510_mode());
 317
 318         if (cpu_class_is_omap1()) {
 319                 u16 w;
 320
 321                 w = dma_read(CCR2(lch));
 322                 w &= ~0x03;
 323
 324                 switch (mode) {
 325                 case OMAP_DMA_CONSTANT_FILL:
 326                         w |= 0x01;
 327                         break;
 328                 case OMAP_DMA_TRANSPARENT_COPY:
 329                         w |= 0x02;
 330                         break;
 331                 case OMAP_DMA_COLOR_DIS:
 332                         break;
 333                 default:
 334                         BUG();
 335                 }
 336                 dma_write(w, CCR2(lch));
 337
 338                 w = dma_read(LCH_CTRL(lch));
 339                 w &= ~0x0f;
 340                 /* Default is channel type 2D */
 341                 if (mode) {
 342                         dma_write((u16)color, COLOR_L(lch));
 343                         dma_write((u16)(color >> 16), COLOR_U(lch));
 344                         w |= 1;         /* Channel type G */
 345                 }
 346                 dma_write(w, LCH_CTRL(lch));
 347         }
 348
 349         if (cpu_class_is_omap2()) {
 350                 u32 val;
 351
 352                 val = dma_read(CCR(lch));
 353                 val &= ~((1 << 17) | (1 << 16));
 354
 355                 switch (mode) {
 356                 case OMAP_DMA_CONSTANT_FILL:
 357                         val |= 1 << 16;
 358                         break;
 359                 case OMAP_DMA_TRANSPARENT_COPY:
 360                         val |= 1 << 17;
 361                         break;
 362                 case OMAP_DMA_COLOR_DIS:
 363                         break;
 364                 default:
 365                         BUG();
 366                 }
 367                 dma_write(val, CCR(lch));
 368
 369                 color &= 0xffffff;
 370                 dma_write(color, COLOR(lch));
 371         }
 372 }
 373 EXPORT_SYMBOL(omap_set_dma_color_mode);
 374
 375 void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
 376 {
 377         if (cpu_class_is_omap2()) {
 378                 u32 csdp;
 379
 380                 csdp = dma_read(CSDP(lch));
 381                 csdp &= ~(0x3 << 16);
 382                 csdp |= (mode << 16);
 383                 dma_write(csdp, CSDP(lch));
 384         }
 385 }
 386 EXPORT_SYMBOL(omap_set_dma_write_mode);
 387
 388 void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
 389 {
 390         if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
 391                 u32 l;
 392
 393                 l = dma_read(LCH_CTRL(lch));
 394                 l &= ~0x7;
 395                 l |= mode;
 396                 dma_write(l, LCH_CTRL(lch));
 397         }
 398 }
 399 EXPORT_SYMBOL(omap_set_dma_channel_mode);
 400
 401 /* Note that src_port is only for omap1 */
 402 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
 403                              unsigned long src_start,
 404                              int src_ei, int src_fi)
 405 {
 406         u32 l;
 407
 408         if (cpu_class_is_omap1()) {
 409                 u16 w;
 410
 411                 w = dma_read(CSDP(lch));
 412                 w &= ~(0x1f << 2);
 413                 w |= src_port << 2;
 414                 dma_write(w, CSDP(lch));
 415         }
 416
 417         l = dma_read(CCR(lch));
 418         l &= ~(0x03 << 12);
 419         l |= src_amode << 12;
 420         dma_write(l, CCR(lch));
 421
 422         if (cpu_class_is_omap1()) {
 423                 dma_write(src_start >> 16, CSSA_U(lch));
 424                 dma_write((u16)src_start, CSSA_L(lch));
 425         }
 426
 427         if (cpu_class_is_omap2())
 428                 dma_write(src_start, CSSA(lch));
 429
 430         dma_write(src_ei, CSEI(lch));
 431         dma_write(src_fi, CSFI(lch));
 432 }
 433 EXPORT_SYMBOL(omap_set_dma_src_params);
 434
 435 void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
 436 {
 437         omap_set_dma_transfer_params(lch, params->data_type,
 438                                      params->elem_count, params->frame_count,
 439                                      params->sync_mode, params->trigger,
 440                                      params->src_or_dst_synch);
 441         omap_set_dma_src_params(lch, params->src_port,
 442                                 params->src_amode, params->src_start,
 443                                 params->src_ei, params->src_fi);
 444
 445         omap_set_dma_dest_params(lch, params->dst_port,
 446                                  params->dst_amode, params->dst_start,
 447                                  params->dst_ei, params->dst_fi);
 448         if (params->read_prio || params->write_prio)
 449                 omap_dma_set_prio_lch(lch, params->read_prio,
 450                                       params->write_prio);
 451 }
 452 EXPORT_SYMBOL(omap_set_dma_params);
 453
 454 void omap_set_dma_src_index(int lch, int eidx, int fidx)
 455 {
 456         if (cpu_class_is_omap2())
 457                 return;
 458
 459         dma_write(eidx, CSEI(lch));
 460         dma_write(fidx, CSFI(lch));
 461 }
 462 EXPORT_SYMBOL(omap_set_dma_src_index);
 463
 464 void omap_set_dma_src_data_pack(int lch, int enable)
 465 {
 466         u32 l;
 467
 468         l = dma_read(CSDP(lch));
 469         l &= ~(1 << 6);
 470         if (enable)
 471                 l |= (1 << 6);
 472         dma_write(l, CSDP(lch));
 473 }
 474 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
 475
 476 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
 477 {
 478         unsigned int burst = 0;
 479         u32 l;
 480
 481         l = dma_read(CSDP(lch));
 482         l &= ~(0x03 << 7);
 483
 484         switch (burst_mode) {
 485         case OMAP_DMA_DATA_BURST_DIS:
 486                 break;
 487         case OMAP_DMA_DATA_BURST_4:
 488                 if (cpu_class_is_omap2())
 489                         burst = 0x1;
 490                 else
 491                         burst = 0x2;
 492                 break;
 493         case OMAP_DMA_DATA_BURST_8:
 494                 if (cpu_class_is_omap2()) {
 495                         burst = 0x2;
 496                         break;
 497                 }
 498                 /* not supported by current hardware on OMAP1
 499                  * w |= (0x03 << 7);
 500                  * fall through
 501                  */
 502         case OMAP_DMA_DATA_BURST_16:
 503                 if (cpu_class_is_omap2()) {
 504                         burst = 0x3;
 505                         break;
 506                 }
 507                 /* OMAP1 don't support burst 16
 508                  * fall through
 509                  */
 510         default:
 511                 BUG();
 512         }
 513
 514         l |= (burst << 7);
 515         dma_write(l, CSDP(lch));
 516 }
 517 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
 518
 519 /* Note that dest_port is only for OMAP1 */
 520 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
 521                               unsigned long dest_start,
 522                               int dst_ei, int dst_fi)
 523 {
 524         u32 l;
 525
 526         if (cpu_class_is_omap1()) {
 527                 l = dma_read(CSDP(lch));
 528                 l &= ~(0x1f << 9);
 529                 l |= dest_port << 9;
 530                 dma_write(l, CSDP(lch));
 531         }
 532
 533         l = dma_read(CCR(lch));
 534         l &= ~(0x03 << 14);
 535         l |= dest_amode << 14;
 536         dma_write(l, CCR(lch));
 537
 538         if (cpu_class_is_omap1()) {
 539                 dma_write(dest_start >> 16, CDSA_U(lch));
 540                 dma_write(dest_start, CDSA_L(lch));
 541         }
 542
 543         if (cpu_class_is_omap2())
 544                 dma_write(dest_start, CDSA(lch));
 545
 546         dma_write(dst_ei, CDEI(lch));
 547         dma_write(dst_fi, CDFI(lch));
 548 }
 549 EXPORT_SYMBOL(omap_set_dma_dest_params);
 550
 551 void omap_set_dma_dest_index(int lch, int eidx, int fidx)
 552 {
 553         if (cpu_class_is_omap2())
 554                 return;
 555
 556         dma_write(eidx, CDEI(lch));
 557         dma_write(fidx, CDFI(lch));
 558 }
 559 EXPORT_SYMBOL(omap_set_dma_dest_index);
 560
 561 void omap_set_dma_dest_data_pack(int lch, int enable)
 562 {
 563         u32 l;
 564
 565         l = dma_read(CSDP(lch));
 566         l &= ~(1 << 13);
 567         if (enable)
 568                 l |= 1 << 13;
 569         dma_write(l, CSDP(lch));
 570 }
 571 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
 572
 573 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
 574 {
 575         unsigned int burst = 0;
 576         u32 l;
 577
 578         l = dma_read(CSDP(lch));
 579         l &= ~(0x03 << 14);
 580
 581         switch (burst_mode) {
 582         case OMAP_DMA_DATA_BURST_DIS:
 583                 break;
 584         case OMAP_DMA_DATA_BURST_4:
 585                 if (cpu_class_is_omap2())
 586                         burst = 0x1;
 587                 else
 588                         burst = 0x2;
 589                 break;
 590         case OMAP_DMA_DATA_BURST_8:
 591                 if (cpu_class_is_omap2())
 592                         burst = 0x2;
 593                 else
 594                         burst = 0x3;
 595                 break;
 596         case OMAP_DMA_DATA_BURST_16:
 597                 if (cpu_class_is_omap2()) {
 598                         burst = 0x3;
 599                         break;
 600                 }
 601                 /* OMAP1 don't support burst 16
 602                  * fall through
 603                  */
 604         default:
 605                 printk(KERN_ERR "Invalid DMA burst mode\n");
 606                 BUG();
 607                 return;
 608         }
 609         l |= (burst << 14);
 610         dma_write(l, CSDP(lch));
 611 }
 612 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
 613
 614 static inline void omap_enable_channel_irq(int lch)
 615 {
 616         u32 status;
 617
 618         /* Clear CSR */
 619         if (cpu_class_is_omap1())
 620                 status = dma_read(CSR(lch));
 621         else if (cpu_class_is_omap2())
 622                 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
 623
 624         /* Enable some nice interrupts. */
 625         dma_write(dma_chan[lch].enabled_irqs, CICR(lch));
 626 }
 627
 628 static void omap_disable_channel_irq(int lch)
 629 {
 630         if (cpu_class_is_omap2())
 631                 dma_write(0, CICR(lch));
 632 }
 633
 634 void omap_enable_dma_irq(int lch, u16 bits)
 635 {
 636         dma_chan[lch].enabled_irqs |= bits;
 637 }
 638 EXPORT_SYMBOL(omap_enable_dma_irq);
 639
 640 void omap_disable_dma_irq(int lch, u16 bits)
 641 {
 642         dma_chan[lch].enabled_irqs &= ~bits;
 643 }
 644 EXPORT_SYMBOL(omap_disable_dma_irq);
 645
 646 static inline void enable_lnk(int lch)
 647 {
 648         u32 l;
 649
 650         l = dma_read(CLNK_CTRL(lch));
 651
 652         if (cpu_class_is_omap1())
 653                 l &= ~(1 << 14);
 654
 655         /* Set the ENABLE_LNK bits */
 656         if (dma_chan[lch].next_lch != -1)
 657                 l = dma_chan[lch].next_lch | (1 << 15);
 658
 659 #ifndef CONFIG_ARCH_OMAP1
 660         if (cpu_class_is_omap2())
 661                 if (dma_chan[lch].next_linked_ch != -1)
 662                         l = dma_chan[lch].next_linked_ch | (1 << 15);
 663 #endif
 664
 665         dma_write(l, CLNK_CTRL(lch));
 666 }
 667
 668 static inline void disable_lnk(int lch)
 669 {
 670         u32 l;
 671
 672         l = dma_read(CLNK_CTRL(lch));
 673
 674         /* Disable interrupts */
 675         if (cpu_class_is_omap1()) {
 676                 dma_write(0, CICR(lch));
 677                 /* Set the STOP_LNK bit */
 678                 l |= 1 << 14;
 679         }
 680
 681         if (cpu_class_is_omap2()) {
 682                 omap_disable_channel_irq(lch);
 683                 /* Clear the ENABLE_LNK bit */
 684                 l &= ~(1 << 15);
 685         }
 686
 687         dma_write(l, CLNK_CTRL(lch));
 688         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
 689 }
 690
 691 static inline void omap2_enable_irq_lch(int lch)
 692 {
 693         u32 val;
 694
 695         if (!cpu_class_is_omap2())
 696                 return;
 697
 698         val = dma_read(IRQENABLE_L0);
 699         val |= 1 << lch;
 700         dma_write(val, IRQENABLE_L0);
 701 }
 702
 703 int omap_request_dma(int dev_id, const char *dev_name,
 704                      void (*callback)(int lch, u16 ch_status, void *data),
 705                      void *data, int *dma_ch_out)
 706 {
 707         int ch, free_ch = -1;
 708         unsigned long flags;
 709         struct omap_dma_lch *chan;
 710
 711         spin_lock_irqsave(&dma_chan_lock, flags);
 712         for (ch = 0; ch < dma_chan_count; ch++) {
 713                 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
 714                         free_ch = ch;
 715                         if (dev_id == 0)
 716                                 break;
 717                 }
 718         }
 719         if (free_ch == -1) {
 720                 spin_unlock_irqrestore(&dma_chan_lock, flags);
 721                 return -EBUSY;
 722         }
 723         chan = dma_chan + free_ch;
 724         chan->dev_id = dev_id;
 725
 726         if (cpu_class_is_omap1())
 727                 clear_lch_regs(free_ch);
 728
 729         if (cpu_class_is_omap2())
 730                 omap_clear_dma(free_ch);
 731
 732         spin_unlock_irqrestore(&dma_chan_lock, flags);
 733
 734         chan->dev_name = dev_name;
 735         chan->callback = callback;
 736         chan->data = data;
 737         chan->flags = 0;
 738
 739 #ifndef CONFIG_ARCH_OMAP1
 740         if (cpu_class_is_omap2()) {
 741                 chan->chain_id = -1;
 742                 chan->next_linked_ch = -1;
 743         }
 744 #endif
 745
 746         chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
 747
 748         if (cpu_class_is_omap1())
 749                 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
 750         else if (cpu_class_is_omap2())
 751                 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
 752                         OMAP2_DMA_TRANS_ERR_IRQ;
 753
 754         if (cpu_is_omap16xx()) {
 755                 /* If the sync device is set, configure it dynamically. */
 756                 if (dev_id != 0) {
 757                         set_gdma_dev(free_ch + 1, dev_id);
 758                         dev_id = free_ch + 1;
 759                 }
 760                 /*
 761                  * Disable the 1510 compatibility mode and set the sync device
 762                  * id.
 763                  */
 764                 dma_write(dev_id | (1 << 10), CCR(free_ch));
 765         } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) {
 766                 dma_write(dev_id, CCR(free_ch));
 767         }
 768
 769         if (cpu_class_is_omap2()) {
 770                 omap2_enable_irq_lch(free_ch);
 771                 omap_enable_channel_irq(free_ch);
 772                 /* Clear the CSR register and IRQ status register */
 773                 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(free_ch));
 774                 dma_write(1 << free_ch, IRQSTATUS_L0);
 775         }
 776
 777         *dma_ch_out = free_ch;
 778
 779         return 0;
 780 }
 781 EXPORT_SYMBOL(omap_request_dma);
 782
 783 void omap_free_dma(int lch)
 784 {
 785         unsigned long flags;
 786
 787         if (dma_chan[lch].dev_id == -1) {
 788                 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
 789                        lch);
 790                 return;
 791         }
 792
 793         if (cpu_class_is_omap1()) {
 794                 /* Disable all DMA interrupts for the channel. */
 795                 dma_write(0, CICR(lch));
 796                 /* Make sure the DMA transfer is stopped. */
 797                 dma_write(0, CCR(lch));
 798         }
 799
 800         if (cpu_class_is_omap2()) {
 801                 u32 val;
 802                 /* Disable interrupts */
 803                 val = dma_read(IRQENABLE_L0);
 804                 val &= ~(1 << lch);
 805                 dma_write(val, IRQENABLE_L0);
 806
 807                 /* Clear the CSR register and IRQ status register */
 808                 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
 809                 dma_write(1 << lch, IRQSTATUS_L0);
 810
 811                 /* Disable all DMA interrupts for the channel. */
 812                 dma_write(0, CICR(lch));
 813
 814                 /* Make sure the DMA transfer is stopped. */
 815                 dma_write(0, CCR(lch));
 816                 omap_clear_dma(lch);
 817         }
 818
 819         spin_lock_irqsave(&dma_chan_lock, flags);
 820         dma_chan[lch].dev_id = -1;
 821         dma_chan[lch].next_lch = -1;
 822         dma_chan[lch].callback = NULL;
 823         spin_unlock_irqrestore(&dma_chan_lock, flags);
 824 }
 825 EXPORT_SYMBOL(omap_free_dma);
 826
 827 /**
 828  * @brief omap_dma_set_global_params : Set global priority settings for dma
 829  *
 830  * @param arb_rate
 831  * @param max_fifo_depth
 832  * @param tparams - Number of thereads to reserve : DMA_THREAD_RESERVE_NORM
 833  *                                                  DMA_THREAD_RESERVE_ONET
 834  *                                                  DMA_THREAD_RESERVE_TWOT
 835  *                                                  DMA_THREAD_RESERVE_THREET
 836  */
 837 void
 838 omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
 839 {
 840         u32 reg;
 841
 842         if (!cpu_class_is_omap2()) {
 843                 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
 844                 return;
 845         }
 846
 847         if (arb_rate == 0)
 848                 arb_rate = 1;
 849
 850         reg = (arb_rate & 0xff) << 16;
 851         reg |= (0xff & max_fifo_depth);
 852
 853         dma_write(reg, GCR);
 854 }
 855 EXPORT_SYMBOL(omap_dma_set_global_params);
 856
 857 /**
 858  * @brief omap_dma_set_prio_lch : Set channel wise priority settings
 859  *
 860  * @param lch
 861  * @param read_prio - Read priority
 862  * @param write_prio - Write priority
 863  * Both of the above can be set with one of the following values :
 864  *      DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
 865  */
 866 int
 867 omap_dma_set_prio_lch(int lch, unsigned char read_prio,
 868                       unsigned char write_prio)
 869 {
 870         u32 l;
 871
 872         if (unlikely((lch < 0 || lch >= dma_lch_count))) {
 873                 printk(KERN_ERR "Invalid channel id\n");
 874                 return -EINVAL;
 875         }
 876         l = dma_read(CCR(lch));
 877         l &= ~((1 << 6) | (1 << 26));
 878         if (cpu_is_omap2430() || cpu_is_omap34xx() ||  cpu_is_omap44xx())
 879                 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
 880         else
 881                 l |= ((read_prio & 0x1) << 6);
 882
 883         dma_write(l, CCR(lch));
 884
 885         return 0;
 886 }
 887 EXPORT_SYMBOL(omap_dma_set_prio_lch);
 888
 889 /*
 890  * Clears any DMA state so the DMA engine is ready to restart with new buffers
 891  * through omap_start_dma(). Any buffers in flight are discarded.
 892  */
 893 void omap_clear_dma(int lch)
 894 {
 895         unsigned long flags;
 896
 897         local_irq_save(flags);
 898
 899         if (cpu_class_is_omap1()) {
 900                 u32 l;
 901
 902                 l = dma_read(CCR(lch));
 903                 l &= ~OMAP_DMA_CCR_EN;
 904                 dma_write(l, CCR(lch));
 905
 906                 /* Clear pending interrupts */
 907                 l = dma_read(CSR(lch));
 908         }
 909
 910         if (cpu_class_is_omap2()) {
 911                 int i;
 912                 void __iomem *lch_base = omap_dma_base + OMAP_DMA4_CH_BASE(lch);
 913                 for (i = 0; i < 0x44; i += 4)
 914                         __raw_writel(0, lch_base + i);
 915         }
 916
 917         local_irq_restore(flags);
 918 }
 919 EXPORT_SYMBOL(omap_clear_dma);
 920
 921 void omap_start_dma(int lch)
 922 {
 923         u32 l;
 924
 925         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
 926                 int next_lch, cur_lch;
 927                 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
 928
 929                 dma_chan_link_map[lch] = 1;
 930                 /* Set the link register of the first channel */
 931                 enable_lnk(lch);
 932
 933                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
 934                 cur_lch = dma_chan[lch].next_lch;
 935                 do {
 936                         next_lch = dma_chan[cur_lch].next_lch;
 937
 938                         /* The loop case: we've been here already */
 939                         if (dma_chan_link_map[cur_lch])
 940                                 break;
 941                         /* Mark the current channel */
 942                         dma_chan_link_map[cur_lch] = 1;
 943
 944                         enable_lnk(cur_lch);
 945                         omap_enable_channel_irq(cur_lch);
 946
 947                         cur_lch = next_lch;
 948                 } while (next_lch != -1);
 949         } else if (cpu_is_omap242x() ||
 950                 (cpu_is_omap243x() &&  omap_type() <= OMAP2430_REV_ES1_0)) {
 951
 952                 /* Errata: Need to write lch even if not using chaining */
 953                 dma_write(lch, CLNK_CTRL(lch));
 954         }
 955
 956         omap_enable_channel_irq(lch);
 957
 958         l = dma_read(CCR(lch));
 959
 960         /*
 961          * Errata: On ES2.0 BUFFERING disable must be set.
 962          * This will always fail on ES1.0
 963          */
 964         if (cpu_is_omap24xx())
 965                 l |= OMAP_DMA_CCR_EN;
 966
 967         l |= OMAP_DMA_CCR_EN;
 968         dma_write(l, CCR(lch));
 969
 970         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
 971 }
 972 EXPORT_SYMBOL(omap_start_dma);
 973
 974 void omap_stop_dma(int lch)
 975 {
 976         u32 l;
 977
 978         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
 979                 int next_lch, cur_lch = lch;
 980                 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
 981
 982                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
 983                 do {
 984                         /* The loop case: we've been here already */
 985                         if (dma_chan_link_map[cur_lch])
 986                                 break;
 987                         /* Mark the current channel */
 988                         dma_chan_link_map[cur_lch] = 1;
 989
 990                         disable_lnk(cur_lch);
 991
 992                         next_lch = dma_chan[cur_lch].next_lch;
 993                         cur_lch = next_lch;
 994                 } while (next_lch != -1);
 995
 996                 return;
 997         }
 998
 999         /* Disable all interrupts on the channel */
1000         if (cpu_class_is_omap1())
1001                 dma_write(0, CICR(lch));
1002
1003         l = dma_read(CCR(lch));
1004         l &= ~OMAP_DMA_CCR_EN;
1005         dma_write(l, CCR(lch));
1006
1007         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
1008 }
1009 EXPORT_SYMBOL(omap_stop_dma);
1010
1011 /*
1012  * Allows changing the DMA callback function or data. This may be needed if
1013  * the driver shares a single DMA channel for multiple dma triggers.
1014  */
1015 int omap_set_dma_callback(int lch,
1016                           void (*callback)(int lch, u16 ch_status, void *data),
1017                           void *data)
1018 {
1019         unsigned long flags;
1020
1021         if (lch < 0)
1022                 return -ENODEV;
1023
1024         spin_lock_irqsave(&dma_chan_lock, flags);
1025         if (dma_chan[lch].dev_id == -1) {
1026                 printk(KERN_ERR "DMA callback for not set for free channel\n");
1027                 spin_unlock_irqrestore(&dma_chan_lock, flags);
1028                 return -EINVAL;
1029         }
1030         dma_chan[lch].callback = callback;
1031         dma_chan[lch].data = data;
1032         spin_unlock_irqrestore(&dma_chan_lock, flags);
1033
1034         return 0;
1035 }
1036 EXPORT_SYMBOL(omap_set_dma_callback);
1037
1038 /*
1039  * Returns current physical source address for the given DMA channel.
1040  * If the channel is running the caller must disable interrupts prior calling
1041  * this function and process the returned value before re-enabling interrupt to
1042  * prevent races with the interrupt handler. Note that in continuous mode there
1043  * is a chance for CSSA_L register overflow inbetween the two reads resulting
1044  * in incorrect return value.
1045  */
1046 dma_addr_t omap_get_dma_src_pos(int lch)
1047 {
1048         dma_addr_t offset = 0;
1049
1050         if (cpu_is_omap15xx())
1051                 offset = dma_read(CPC(lch));
1052         else
1053                 offset = dma_read(CSAC(lch));
1054
1055         /*
1056          * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1057          * read before the DMA controller finished disabling the channel.
1058          */
1059         if (!cpu_is_omap15xx() && offset == 0)
1060                 offset = dma_read(CSAC(lch));
1061
1062         if (cpu_class_is_omap1())
1063                 offset |= (dma_read(CSSA_U(lch)) << 16);
1064
1065         return offset;
1066 }
1067 EXPORT_SYMBOL(omap_get_dma_src_pos);
1068
1069 /*
1070  * Returns current physical destination address for the given DMA channel.
1071  * If the channel is running the caller must disable interrupts prior calling
1072  * this function and process the returned value before re-enabling interrupt to
1073  * prevent races with the interrupt handler. Note that in continuous mode there
1074  * is a chance for CDSA_L register overflow inbetween the two reads resulting
1075  * in incorrect return value.
1076  */
1077 dma_addr_t omap_get_dma_dst_pos(int lch)
1078 {
1079         dma_addr_t offset = 0;
1080
1081         if (cpu_is_omap15xx())
1082                 offset = dma_read(CPC(lch));
1083         else
1084                 offset = dma_read(CDAC(lch));
1085
1086         /*
1087          * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1088          * read before the DMA controller finished disabling the channel.
1089          */
1090         if (!cpu_is_omap15xx() && offset == 0)
1091                 offset = dma_read(CDAC(lch));
1092
1093         if (cpu_class_is_omap1())
1094                 offset |= (dma_read(CDSA_U(lch)) << 16);
1095
1096         return offset;
1097 }
1098 EXPORT_SYMBOL(omap_get_dma_dst_pos);
1099
1100 int omap_get_dma_active_status(int lch)
1101 {
1102         return (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN) != 0;
1103 }
1104 EXPORT_SYMBOL(omap_get_dma_active_status);
1105
1106 int omap_dma_running(void)
1107 {
1108         int lch;
1109
1110         /* Check if LCD DMA is running */
1111         if (cpu_is_omap16xx())
1112                 if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN)
1113                         return 1;
1114
1115         for (lch = 0; lch < dma_chan_count; lch++)
1116                 if (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN)
1117                         return 1;
1118
1119         return 0;
1120 }
1121
1122 /*
1123  * lch_queue DMA will start right after lch_head one is finished.
1124  * For this DMA link to start, you still need to start (see omap_start_dma)
1125  * the first one. That will fire up the entire queue.
1126  */
1127 void omap_dma_link_lch(int lch_head, int lch_queue)
1128 {
1129         if (omap_dma_in_1510_mode()) {
1130                 if (lch_head == lch_queue) {
1131                         dma_write(dma_read(CCR(lch_head)) | (3 << 8),
1132                                                                 CCR(lch_head));
1133                         return;
1134                 }
1135                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1136                 BUG();
1137                 return;
1138         }
1139
1140         if ((dma_chan[lch_head].dev_id == -1) ||
1141             (dma_chan[lch_queue].dev_id == -1)) {
1142                 printk(KERN_ERR "omap_dma: trying to link "
1143                        "non requested channels\n");
1144                 dump_stack();
1145         }
1146
1147         dma_chan[lch_head].next_lch = lch_queue;
1148 }
1149 EXPORT_SYMBOL(omap_dma_link_lch);
1150
1151 /*
1152  * Once the DMA queue is stopped, we can destroy it.
1153  */
1154 void omap_dma_unlink_lch(int lch_head, int lch_queue)
1155 {
1156         if (omap_dma_in_1510_mode()) {
1157                 if (lch_head == lch_queue) {
1158                         dma_write(dma_read(CCR(lch_head)) & ~(3 << 8),
1159                                                                 CCR(lch_head));
1160                         return;
1161                 }
1162                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1163                 BUG();
1164                 return;
1165         }
1166
1167         if (dma_chan[lch_head].next_lch != lch_queue ||
1168             dma_chan[lch_head].next_lch == -1) {
1169                 printk(KERN_ERR "omap_dma: trying to unlink "
1170                        "non linked channels\n");
1171                 dump_stack();
1172         }
1173
1174         if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
1175             (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) {
1176                 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
1177                        "before unlinking\n");
1178                 dump_stack();
1179         }
1180
1181         dma_chan[lch_head].next_lch = -1;
1182 }
1183 EXPORT_SYMBOL(omap_dma_unlink_lch);
1184
1185 /*----------------------------------------------------------------------------*/
1186
1187 #ifndef CONFIG_ARCH_OMAP1
1188 /* Create chain of DMA channesls */
1189 static void create_dma_lch_chain(int lch_head, int lch_queue)
1190 {
1191         u32 l;
1192
1193         /* Check if this is the first link in chain */
1194         if (dma_chan[lch_head].next_linked_ch == -1) {
1195                 dma_chan[lch_head].next_linked_ch = lch_queue;
1196                 dma_chan[lch_head].prev_linked_ch = lch_queue;
1197                 dma_chan[lch_queue].next_linked_ch = lch_head;
1198                 dma_chan[lch_queue].prev_linked_ch = lch_head;
1199         }
1200
1201         /* a link exists, link the new channel in circular chain */
1202         else {
1203                 dma_chan[lch_queue].next_linked_ch =
1204                                         dma_chan[lch_head].next_linked_ch;
1205                 dma_chan[lch_queue].prev_linked_ch = lch_head;
1206                 dma_chan[lch_head].next_linked_ch = lch_queue;
1207                 dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
1208                                         lch_queue;
1209         }
1210
1211         l = dma_read(CLNK_CTRL(lch_head));
1212         l &= ~(0x1f);
1213         l |= lch_queue;
1214         dma_write(l, CLNK_CTRL(lch_head));
1215
1216         l = dma_read(CLNK_CTRL(lch_queue));
1217         l &= ~(0x1f);
1218         l |= (dma_chan[lch_queue].next_linked_ch);
1219         dma_write(l, CLNK_CTRL(lch_queue));
1220 }
1221
1222 /**
1223  * @brief omap_request_dma_chain : Request a chain of DMA channels
1224  *
1225  * @param dev_id - Device id using the dma channel
1226  * @param dev_name - Device name
1227  * @param callback - Call back function
1228  * @chain_id -
1229  * @no_of_chans - Number of channels requested
1230  * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1231  *                                            OMAP_DMA_DYNAMIC_CHAIN
1232  * @params - Channel parameters
1233  *
1234  * @return - Succes : 0
1235  *           Failure: -EINVAL/-ENOMEM
1236  */
1237 int omap_request_dma_chain(int dev_id, const char *dev_name,
1238                            void (*callback) (int lch, u16 ch_status,
1239                                              void *data),
1240                            int *chain_id, int no_of_chans, int chain_mode,
1241                            struct omap_dma_channel_params params)
1242 {
1243         int *channels;
1244         int i, err;
1245
1246         /* Is the chain mode valid ? */
1247         if (chain_mode != OMAP_DMA_STATIC_CHAIN
1248                         && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
1249                 printk(KERN_ERR "Invalid chain mode requested\n");
1250                 return -EINVAL;
1251         }
1252
1253         if (unlikely((no_of_chans < 1
1254                         || no_of_chans > dma_lch_count))) {
1255                 printk(KERN_ERR "Invalid Number of channels requested\n");
1256                 return -EINVAL;
1257         }
1258
1259         /* Allocate a queue to maintain the status of the channels
1260          * in the chain */
1261         channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
1262         if (channels == NULL) {
1263                 printk(KERN_ERR "omap_dma: No memory for channel queue\n");
1264                 return -ENOMEM;
1265         }
1266
1267         /* request and reserve DMA channels for the chain */
1268         for (i = 0; i < no_of_chans; i++) {
1269                 err = omap_request_dma(dev_id, dev_name,
1270                                         callback, NULL, &channels[i]);
1271                 if (err < 0) {
1272                         int j;
1273                         for (j = 0; j < i; j++)
1274                                 omap_free_dma(channels[j]);
1275                         kfree(channels);
1276                         printk(KERN_ERR "omap_dma: Request failed %d\n", err);
1277                         return err;
1278                 }
1279                 dma_chan[channels[i]].prev_linked_ch = -1;
1280                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1281
1282                 /*
1283                  * Allowing client drivers to set common parameters now,
1284                  * so that later only relevant (src_start, dest_start
1285                  * and element count) can be set
1286                  */
1287                 omap_set_dma_params(channels[i], &params);
1288         }
1289
1290         *chain_id = channels[0];
1291         dma_linked_lch[*chain_id].linked_dmach_q = channels;
1292         dma_linked_lch[*chain_id].chain_mode = chain_mode;
1293         dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1294         dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;
1295
1296         for (i = 0; i < no_of_chans; i++)
1297                 dma_chan[channels[i]].chain_id = *chain_id;
1298
1299         /* Reset the Queue pointers */
1300         OMAP_DMA_CHAIN_QINIT(*chain_id);
1301
1302         /* Set up the chain */
1303         if (no_of_chans == 1)
1304                 create_dma_lch_chain(channels[0], channels[0]);
1305         else {
1306                 for (i = 0; i < (no_of_chans - 1); i++)
1307                         create_dma_lch_chain(channels[i], channels[i + 1]);
1308         }
1309
1310         return 0;
1311 }
1312 EXPORT_SYMBOL(omap_request_dma_chain);
1313
1314 /**
1315  * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1316  * params after setting it. Dont do this while dma is running!!
1317  *
1318  * @param chain_id - Chained logical channel id.
1319  * @param params
1320  *
1321  * @return - Success : 0
1322  *           Failure : -EINVAL
1323  */
1324 int omap_modify_dma_chain_params(int chain_id,
1325                                 struct omap_dma_channel_params params)
1326 {
1327         int *channels;
1328         u32 i;
1329
1330         /* Check for input params */
1331         if (unlikely((chain_id < 0
1332                         || chain_id >= dma_lch_count))) {
1333                 printk(KERN_ERR "Invalid chain id\n");
1334                 return -EINVAL;
1335         }
1336
1337         /* Check if the chain exists */
1338         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1339                 printk(KERN_ERR "Chain doesn't exists\n");
1340                 return -EINVAL;
1341         }
1342         channels = dma_linked_lch[chain_id].linked_dmach_q;
1343
1344         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1345                 /*
1346                  * Allowing client drivers to set common parameters now,
1347                  * so that later only relevant (src_start, dest_start
1348                  * and element count) can be set
1349                  */
1350                 omap_set_dma_params(channels[i], &params);
1351         }
1352
1353         return 0;
1354 }
1355 EXPORT_SYMBOL(omap_modify_dma_chain_params);
1356
1357 /**
1358  * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1359  *
1360  * @param chain_id
1361  *
1362  * @return - Success : 0
1363  *           Failure : -EINVAL
1364  */
1365 int omap_free_dma_chain(int chain_id)
1366 {
1367         int *channels;
1368         u32 i;
1369
1370         /* Check for input params */
1371         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1372                 printk(KERN_ERR "Invalid chain id\n");
1373                 return -EINVAL;
1374         }
1375
1376         /* Check if the chain exists */
1377         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1378                 printk(KERN_ERR "Chain doesn't exists\n");
1379                 return -EINVAL;
1380         }
1381
1382         channels = dma_linked_lch[chain_id].linked_dmach_q;
1383         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1384                 dma_chan[channels[i]].next_linked_ch = -1;
1385                 dma_chan[channels[i]].prev_linked_ch = -1;
1386                 dma_chan[channels[i]].chain_id = -1;
1387                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1388                 omap_free_dma(channels[i]);
1389         }
1390
1391         kfree(channels);
1392
1393         dma_linked_lch[chain_id].linked_dmach_q = NULL;
1394         dma_linked_lch[chain_id].chain_mode = -1;
1395         dma_linked_lch[chain_id].chain_state = -1;
1396
1397         return (0);
1398 }
1399 EXPORT_SYMBOL(omap_free_dma_chain);
1400
1401 /**
1402  * @brief omap_dma_chain_status - Check if the chain is in
1403  * active / inactive state.
1404  * @param chain_id
1405  *
1406  * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1407  *           Failure : -EINVAL
1408  */
1409 int omap_dma_chain_status(int chain_id)
1410 {
1411         /* Check for input params */
1412         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1413                 printk(KERN_ERR "Invalid chain id\n");
1414                 return -EINVAL;
1415         }
1416
1417         /* Check if the chain exists */
1418         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1419                 printk(KERN_ERR "Chain doesn't exists\n");
1420                 return -EINVAL;
1421         }
1422         pr_debug("CHAINID=%d, qcnt=%d\n", chain_id,
1423                         dma_linked_lch[chain_id].q_count);
1424
1425         if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
1426                 return OMAP_DMA_CHAIN_INACTIVE;
1427
1428         return OMAP_DMA_CHAIN_ACTIVE;
1429 }
1430 EXPORT_SYMBOL(omap_dma_chain_status);
1431
1432 /**
1433  * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1434  * set the params and start the transfer.
1435  *
1436  * @param chain_id
1437  * @param src_start - buffer start address
1438  * @param dest_start - Dest address
1439  * @param elem_count
1440  * @param frame_count
1441  * @param callbk_data - channel callback parameter data.
1442  *
1443  * @return  - Success : 0
1444  *            Failure: -EINVAL/-EBUSY
1445  */
1446 int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1447                         int elem_count, int frame_count, void *callbk_data)
1448 {
1449         int *channels;
1450         u32 l, lch;
1451         int start_dma = 0;
1452
1453         /*
1454          * if buffer size is less than 1 then there is
1455          * no use of starting the chain
1456          */
1457         if (elem_count < 1) {
1458                 printk(KERN_ERR "Invalid buffer size\n");
1459                 return -EINVAL;
1460         }
1461
1462         /* Check for input params */
1463         if (unlikely((chain_id < 0
1464                         || chain_id >= dma_lch_count))) {
1465                 printk(KERN_ERR "Invalid chain id\n");
1466                 return -EINVAL;
1467         }
1468
1469         /* Check if the chain exists */
1470         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1471                 printk(KERN_ERR "Chain doesn't exist\n");
1472                 return -EINVAL;
1473         }
1474
1475         /* Check if all the channels in chain are in use */
1476         if (OMAP_DMA_CHAIN_QFULL(chain_id))
1477                 return -EBUSY;
1478
1479         /* Frame count may be negative in case of indexed transfers */
1480         channels = dma_linked_lch[chain_id].linked_dmach_q;
1481
1482         /* Get a free channel */
1483         lch = channels[dma_linked_lch[chain_id].q_tail];
1484
1485         /* Store the callback data */
1486         dma_chan[lch].data = callbk_data;
1487
1488         /* Increment the q_tail */
1489         OMAP_DMA_CHAIN_INCQTAIL(chain_id);
1490
1491         /* Set the params to the free channel */
1492         if (src_start != 0)
1493                 dma_write(src_start, CSSA(lch));
1494         if (dest_start != 0)
1495                 dma_write(dest_start, CDSA(lch));
1496
1497         /* Write the buffer size */
1498         dma_write(elem_count, CEN(lch));
1499         dma_write(frame_count, CFN(lch));
1500
1501         /*
1502          * If the chain is dynamically linked,
1503          * then we may have to start the chain if its not active
1504          */
1505         if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
1506
1507                 /*
1508                  * In Dynamic chain, if the chain is not started,
1509                  * queue the channel
1510                  */
1511                 if (dma_linked_lch[chain_id].chain_state ==
1512                                                 DMA_CHAIN_NOTSTARTED) {
1513                         /* Enable the link in previous channel */
1514                         if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1515                                                                 DMA_CH_QUEUED)
1516                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1517                         dma_chan[lch].state = DMA_CH_QUEUED;
1518                 }
1519
1520                 /*
1521                  * Chain is already started, make sure its active,
1522                  * if not then start the chain
1523                  */
1524                 else {
1525                         start_dma = 1;
1526
1527                         if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1528                                                         DMA_CH_STARTED) {
1529                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1530                                 dma_chan[lch].state = DMA_CH_QUEUED;
1531                                 start_dma = 0;
1532                                 if (0 == ((1 << 7) & dma_read(
1533                                         CCR(dma_chan[lch].prev_linked_ch)))) {
1534                                         disable_lnk(dma_chan[lch].
1535                                                     prev_linked_ch);
1536                                         pr_debug("\n prev ch is stopped\n");
1537                                         start_dma = 1;
1538                                 }
1539                         }
1540
1541                         else if (dma_chan[dma_chan[lch].prev_linked_ch].state
1542                                                         == DMA_CH_QUEUED) {
1543                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1544                                 dma_chan[lch].state = DMA_CH_QUEUED;
1545                                 start_dma = 0;
1546                         }
1547                         omap_enable_channel_irq(lch);
1548
1549                         l = dma_read(CCR(lch));
1550
1551                         if ((0 == (l & (1 << 24))))
1552                                 l &= ~(1 << 25);
1553                         else
1554                                 l |= (1 << 25);
1555                         if (start_dma == 1) {
1556                                 if (0 == (l & (1 << 7))) {
1557                                         l |= (1 << 7);
1558                                         dma_chan[lch].state = DMA_CH_STARTED;
1559                                         pr_debug("starting %d\n", lch);
1560                                         dma_write(l, CCR(lch));
1561                                 } else
1562                                         start_dma = 0;
1563                         } else {
1564                                 if (0 == (l & (1 << 7)))
1565                                         dma_write(l, CCR(lch));
1566                         }
1567                         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1568                 }
1569         }
1570
1571         return 0;
1572 }
1573 EXPORT_SYMBOL(omap_dma_chain_a_transfer);
1574
1575 /**
1576  * @brief omap_start_dma_chain_transfers - Start the chain
1577  *
1578  * @param chain_id
1579  *
1580  * @return - Success : 0
1581  *           Failure : -EINVAL/-EBUSY
1582  */
1583 int omap_start_dma_chain_transfers(int chain_id)
1584 {
1585         int *channels;
1586         u32 l, i;
1587
1588         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1589                 printk(KERN_ERR "Invalid chain id\n");
1590                 return -EINVAL;
1591         }
1592
1593         channels = dma_linked_lch[chain_id].linked_dmach_q;
1594
1595         if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
1596                 printk(KERN_ERR "Chain is already started\n");
1597                 return -EBUSY;
1598         }
1599
1600         if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
1601                 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
1602                                                                         i++) {
1603                         enable_lnk(channels[i]);
1604                         omap_enable_channel_irq(channels[i]);
1605                 }
1606         } else {
1607                 omap_enable_channel_irq(channels[0]);
1608         }
1609
1610         l = dma_read(CCR(channels[0]));
1611         l |= (1 << 7);
1612         dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
1613         dma_chan[channels[0]].state = DMA_CH_STARTED;
1614
1615         if ((0 == (l & (1 << 24))))
1616                 l &= ~(1 << 25);
1617         else
1618                 l |= (1 << 25);
1619         dma_write(l, CCR(channels[0]));
1620
1621         dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
1622
1623         return 0;
1624 }
1625 EXPORT_SYMBOL(omap_start_dma_chain_transfers);
1626
1627 /**
1628  * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1629  *
1630  * @param chain_id
1631  *
1632  * @return - Success : 0
1633  *           Failure : EINVAL
1634  */
1635 int omap_stop_dma_chain_transfers(int chain_id)
1636 {
1637         int *channels;
1638         u32 l, i;
1639         u32 sys_cf;
1640
1641         /* Check for input params */
1642         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1643                 printk(KERN_ERR "Invalid chain id\n");
1644                 return -EINVAL;
1645         }
1646
1647         /* Check if the chain exists */
1648         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1649                 printk(KERN_ERR "Chain doesn't exists\n");
1650                 return -EINVAL;
1651         }
1652         channels = dma_linked_lch[chain_id].linked_dmach_q;
1653
1654         /*
1655          * DMA Errata:
1656          * Special programming model needed to disable DMA before end of block
1657          */
1658         sys_cf = dma_read(OCP_SYSCONFIG);
1659         l = sys_cf;
1660         /* Middle mode reg set no Standby */
1661         l &= ~((1 << 12)|(1 << 13));
1662         dma_write(l, OCP_SYSCONFIG);
1663
1664         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1665
1666                 /* Stop the Channel transmission */
1667                 l = dma_read(CCR(channels[i]));
1668                 l &= ~(1 << 7);
1669                 dma_write(l, CCR(channels[i]));
1670
1671                 /* Disable the link in all the channels */
1672                 disable_lnk(channels[i]);
1673                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1674
1675         }
1676         dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1677
1678         /* Reset the Queue pointers */
1679         OMAP_DMA_CHAIN_QINIT(chain_id);
1680
1681         /* Errata - put in the old value */
1682         dma_write(sys_cf, OCP_SYSCONFIG);
1683
1684         return 0;
1685 }
1686 EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
1687
1688 /* Get the index of the ongoing DMA in chain */
1689 /**
1690  * @brief omap_get_dma_chain_index - Get the element and frame index
1691  * of the ongoing DMA in chain
1692  *
1693  * @param chain_id
1694  * @param ei - Element index
1695  * @param fi - Frame index
1696  *
1697  * @return - Success : 0
1698  *           Failure : -EINVAL
1699  */
1700 int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1701 {
1702         int lch;
1703         int *channels;
1704
1705         /* Check for input params */
1706         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1707                 printk(KERN_ERR "Invalid chain id\n");
1708                 return -EINVAL;
1709         }
1710
1711         /* Check if the chain exists */
1712         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1713                 printk(KERN_ERR "Chain doesn't exists\n");
1714                 return -EINVAL;
1715         }
1716         if ((!ei) || (!fi))
1717                 return -EINVAL;
1718
1719         channels = dma_linked_lch[chain_id].linked_dmach_q;
1720
1721         /* Get the current channel */
1722         lch = channels[dma_linked_lch[chain_id].q_head];
1723
1724         *ei = dma_read(CCEN(lch));
1725         *fi = dma_read(CCFN(lch));
1726
1727         return 0;
1728 }
1729 EXPORT_SYMBOL(omap_get_dma_chain_index);
1730
1731 /**
1732  * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1733  * ongoing DMA in chain
1734  *
1735  * @param chain_id
1736  *
1737  * @return - Success : Destination position
1738  *           Failure : -EINVAL
1739  */
1740 int omap_get_dma_chain_dst_pos(int chain_id)
1741 {
1742         int lch;
1743         int *channels;
1744
1745         /* Check for input params */
1746         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1747                 printk(KERN_ERR "Invalid chain id\n");
1748                 return -EINVAL;
1749         }
1750
1751         /* Check if the chain exists */
1752         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1753                 printk(KERN_ERR "Chain doesn't exists\n");
1754                 return -EINVAL;
1755         }
1756
1757         channels = dma_linked_lch[chain_id].linked_dmach_q;
1758
1759         /* Get the current channel */
1760         lch = channels[dma_linked_lch[chain_id].q_head];
1761
1762         return dma_read(CDAC(lch));
1763 }
1764 EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
1765
1766 /**
1767  * @brief omap_get_dma_chain_src_pos - Get the source position
1768  * of the ongoing DMA in chain
1769  * @param chain_id
1770  *
1771  * @return - Success : Destination position
1772  *           Failure : -EINVAL
1773  */
1774 int omap_get_dma_chain_src_pos(int chain_id)
1775 {
1776         int lch;
1777         int *channels;
1778
1779         /* Check for input params */
1780         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1781                 printk(KERN_ERR "Invalid chain id\n");
1782                 return -EINVAL;
1783         }
1784
1785         /* Check if the chain exists */
1786         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1787                 printk(KERN_ERR "Chain doesn't exists\n");
1788                 return -EINVAL;
1789         }
1790
1791         channels = dma_linked_lch[chain_id].linked_dmach_q;
1792
1793         /* Get the current channel */
1794         lch = channels[dma_linked_lch[chain_id].q_head];
1795
1796         return dma_read(CSAC(lch));
1797 }
1798 EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
1799 #endif  /* ifndef CONFIG_ARCH_OMAP1 */
1800
1801 /*----------------------------------------------------------------------------*/
1802
1803 #ifdef CONFIG_ARCH_OMAP1
1804
1805 static int omap1_dma_handle_ch(int ch)
1806 {
1807         u32 csr;
1808
1809         if (enable_1510_mode && ch >= 6) {
1810                 csr = dma_chan[ch].saved_csr;
1811                 dma_chan[ch].saved_csr = 0;
1812         } else
1813                 csr = dma_read(CSR(ch));
1814         if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1815                 dma_chan[ch + 6].saved_csr = csr >> 7;
1816                 csr &= 0x7f;
1817         }
1818         if ((csr & 0x3f) == 0)
1819                 return 0;
1820         if (unlikely(dma_chan[ch].dev_id == -1)) {
1821                 printk(KERN_WARNING "Spurious interrupt from DMA channel "
1822                        "%d (CSR %04x)\n", ch, csr);
1823                 return 0;
1824         }
1825         if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
1826                 printk(KERN_WARNING "DMA timeout with device %d\n",
1827                        dma_chan[ch].dev_id);
1828         if (unlikely(csr & OMAP_DMA_DROP_IRQ))
1829                 printk(KERN_WARNING "DMA synchronization event drop occurred "
1830                        "with device %d\n", dma_chan[ch].dev_id);
1831         if (likely(csr & OMAP_DMA_BLOCK_IRQ))
1832                 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1833         if (likely(dma_chan[ch].callback != NULL))
1834                 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
1835
1836         return 1;
1837 }
1838
1839 static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1840 {
1841         int ch = ((int) dev_id) - 1;
1842         int handled = 0;
1843
1844         for (;;) {
1845                 int handled_now = 0;
1846
1847                 handled_now += omap1_dma_handle_ch(ch);
1848                 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
1849                         handled_now += omap1_dma_handle_ch(ch + 6);
1850                 if (!handled_now)
1851                         break;
1852                 handled += handled_now;
1853         }
1854
1855         return handled ? IRQ_HANDLED : IRQ_NONE;
1856 }
1857
1858 #else
1859 #define omap1_dma_irq_handler   NULL
1860 #endif
1861
1862 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
1863                         defined(CONFIG_ARCH_OMAP4)
1864
1865 static int omap2_dma_handle_ch(int ch)
1866 {
1867         u32 status = dma_read(CSR(ch));
1868
1869         if (!status) {
1870                 if (printk_ratelimit())
1871                         printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
1872                                 ch);
1873                 dma_write(1 << ch, IRQSTATUS_L0);
1874                 return 0;
1875         }
1876         if (unlikely(dma_chan[ch].dev_id == -1)) {
1877                 if (printk_ratelimit())
1878                         printk(KERN_WARNING "IRQ %04x for non-allocated DMA"
1879                                         "channel %d\n", status, ch);
1880                 return 0;
1881         }
1882         if (unlikely(status & OMAP_DMA_DROP_IRQ))
1883                 printk(KERN_INFO
1884                        "DMA synchronization event drop occurred with device "
1885                        "%d\n", dma_chan[ch].dev_id);
1886         if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
1887                 printk(KERN_INFO "DMA transaction error with device %d\n",
1888                        dma_chan[ch].dev_id);
1889                 if (cpu_class_is_omap2()) {
1890                         /* Errata: sDMA Channel is not disabled
1891                          * after a transaction error. So we explicitely
1892                          * disable the channel
1893                          */
1894                         u32 ccr;
1895
1896                         ccr = dma_read(CCR(ch));
1897                         ccr &= ~OMAP_DMA_CCR_EN;
1898                         dma_write(ccr, CCR(ch));
1899                         dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1900                 }
1901         }
1902         if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
1903                 printk(KERN_INFO "DMA secure error with device %d\n",
1904                        dma_chan[ch].dev_id);
1905         if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
1906                 printk(KERN_INFO "DMA misaligned error with device %d\n",
1907                        dma_chan[ch].dev_id);
1908
1909         dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(ch));
1910         dma_write(1 << ch, IRQSTATUS_L0);
1911
1912         /* If the ch is not chained then chain_id will be -1 */
1913         if (dma_chan[ch].chain_id != -1) {
1914                 int chain_id = dma_chan[ch].chain_id;
1915                 dma_chan[ch].state = DMA_CH_NOTSTARTED;
1916                 if (dma_read(CLNK_CTRL(ch)) & (1 << 15))
1917                         dma_chan[dma_chan[ch].next_linked_ch].state =
1918                                                         DMA_CH_STARTED;
1919                 if (dma_linked_lch[chain_id].chain_mode ==
1920                                                 OMAP_DMA_DYNAMIC_CHAIN)
1921                         disable_lnk(ch);
1922
1923                 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1924                         OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1925
1926                 status = dma_read(CSR(ch));
1927         }
1928
1929         dma_write(status, CSR(ch));
1930
1931         if (likely(dma_chan[ch].callback != NULL))
1932                 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1933
1934         return 0;
1935 }
1936
1937 /* STATUS register count is from 1-32 while our is 0-31 */
1938 static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1939 {
1940         u32 val, enable_reg;
1941         int i;
1942
1943         val = dma_read(IRQSTATUS_L0);
1944         if (val == 0) {
1945                 if (printk_ratelimit())
1946                         printk(KERN_WARNING "Spurious DMA IRQ\n");
1947                 return IRQ_HANDLED;
1948         }
1949         enable_reg = dma_read(IRQENABLE_L0);
1950         val &= enable_reg; /* Dispatch only relevant interrupts */
1951         for (i = 0; i < dma_lch_count && val != 0; i++) {
1952                 if (val & 1)
1953                         omap2_dma_handle_ch(i);
1954                 val >>= 1;
1955         }
1956
1957         return IRQ_HANDLED;
1958 }
1959
1960 static struct irqaction omap24xx_dma_irq = {
1961         .name = "DMA",
1962         .handler = omap2_dma_irq_handler,
1963         .flags = IRQF_DISABLED
1964 };
1965
1966 #else
1967 static struct irqaction omap24xx_dma_irq;
1968 #endif
1969
1970 /*----------------------------------------------------------------------------*/
1971
1972 static struct lcd_dma_info {
1973         spinlock_t lock;
1974         int reserved;
1975         void (*callback)(u16 status, void *data);
1976         void *cb_data;
1977
1978         int active;
1979         unsigned long addr, size;
1980         int rotate, data_type, xres, yres;
1981         int vxres;
1982         int mirror;
1983         int xscale, yscale;
1984         int ext_ctrl;
1985         int src_port;
1986         int single_transfer;
1987 } lcd_dma;
1988
1989 void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
1990                          int data_type)
1991 {
1992         lcd_dma.addr = addr;
1993         lcd_dma.data_type = data_type;
1994         lcd_dma.xres = fb_xres;
1995         lcd_dma.yres = fb_yres;
1996 }
1997 EXPORT_SYMBOL(omap_set_lcd_dma_b1);
1998
1999 void omap_set_lcd_dma_src_port(int port)
2000 {
2001         lcd_dma.src_port = port;
2002 }
2003
2004 void omap_set_lcd_dma_ext_controller(int external)
2005 {
2006         lcd_dma.ext_ctrl = external;
2007 }
2008 EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
2009
2010 void omap_set_lcd_dma_single_transfer(int single)
2011 {
2012         lcd_dma.single_transfer = single;
2013 }
2014 EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
2015
2016 void omap_set_lcd_dma_b1_rotation(int rotate)
2017 {
2018         if (omap_dma_in_1510_mode()) {
2019                 printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n");
2020                 BUG();
2021                 return;
2022         }
2023         lcd_dma.rotate = rotate;
2024 }
2025 EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
2026
2027 void omap_set_lcd_dma_b1_mirror(int mirror)
2028 {
2029         if (omap_dma_in_1510_mode()) {
2030                 printk(KERN_ERR "DMA mirror is not supported in 1510 mode\n");
2031                 BUG();
2032         }
2033         lcd_dma.mirror = mirror;
2034 }
2035 EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
2036
2037 void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
2038 {
2039         if (omap_dma_in_1510_mode()) {
2040                 printk(KERN_ERR "DMA virtual resulotion is not supported "
2041                                 "in 1510 mode\n");
2042                 BUG();
2043         }
2044         lcd_dma.vxres = vxres;
2045 }
2046 EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
2047
2048 void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
2049 {
2050         if (omap_dma_in_1510_mode()) {
2051                 printk(KERN_ERR "DMA scale is not supported in 1510 mode\n");
2052                 BUG();
2053         }
2054         lcd_dma.xscale = xscale;
2055         lcd_dma.yscale = yscale;
2056 }
2057 EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
2058
2059 static void set_b1_regs(void)
2060 {
2061         unsigned long top, bottom;
2062         int es;
2063         u16 w;
2064         unsigned long en, fn;
2065         long ei, fi;
2066         unsigned long vxres;
2067         unsigned int xscale, yscale;
2068
2069         switch (lcd_dma.data_type) {
2070         case OMAP_DMA_DATA_TYPE_S8:
2071                 es = 1;
2072                 break;
2073         case OMAP_DMA_DATA_TYPE_S16:
2074                 es = 2;
2075                 break;
2076         case OMAP_DMA_DATA_TYPE_S32:
2077                 es = 4;
2078                 break;
2079         default:
2080                 BUG();
2081                 return;
2082         }
2083
2084         vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres;
2085         xscale = lcd_dma.xscale ? lcd_dma.xscale : 1;
2086         yscale = lcd_dma.yscale ? lcd_dma.yscale : 1;
2087         BUG_ON(vxres < lcd_dma.xres);
2088
2089 #define PIXADDR(x, y) (lcd_dma.addr +                                   \
2090                 ((y) * vxres * yscale + (x) * xscale) * es)
2091 #define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
2092
2093         switch (lcd_dma.rotate) {
2094         case 0:
2095                 if (!lcd_dma.mirror) {
2096                         top = PIXADDR(0, 0);
2097                         bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2098                         /* 1510 DMA requires the bottom address to be 2 more
2099                          * than the actual last memory access location. */
2100                         if (omap_dma_in_1510_mode() &&
2101                                 lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
2102                                         bottom += 2;
2103                         ei = PIXSTEP(0, 0, 1, 0);
2104                         fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1);
2105                 } else {
2106                         top = PIXADDR(lcd_dma.xres - 1, 0);
2107                         bottom = PIXADDR(0, lcd_dma.yres - 1);
2108                         ei = PIXSTEP(1, 0, 0, 0);
2109                         fi = PIXSTEP(0, 0, lcd_dma.xres - 1, 1);
2110                 }
2111                 en = lcd_dma.xres;
2112                 fn = lcd_dma.yres;
2113                 break;
2114         case 90:
2115                 if (!lcd_dma.mirror) {
2116                         top = PIXADDR(0, lcd_dma.yres - 1);
2117                         bottom = PIXADDR(lcd_dma.xres - 1, 0);
2118                         ei = PIXSTEP(0, 1, 0, 0);
2119                         fi = PIXSTEP(0, 0, 1, lcd_dma.yres - 1);
2120                 } else {
2121                         top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2122                         bottom = PIXADDR(0, 0);
2123                         ei = PIXSTEP(0, 1, 0, 0);
2124                         fi = PIXSTEP(1, 0, 0, lcd_dma.yres - 1);
2125                 }
2126                 en = lcd_dma.yres;
2127                 fn = lcd_dma.xres;
2128                 break;
2129         case 180:
2130                 if (!lcd_dma.mirror) {
2131                         top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2132                         bottom = PIXADDR(0, 0);
2133                         ei = PIXSTEP(1, 0, 0, 0);
2134                         fi = PIXSTEP(0, 1, lcd_dma.xres - 1, 0);
2135                 } else {
2136                         top = PIXADDR(0, lcd_dma.yres - 1);
2137                         bottom = PIXADDR(lcd_dma.xres - 1, 0);
2138                         ei = PIXSTEP(0, 0, 1, 0);
2139                         fi = PIXSTEP(lcd_dma.xres - 1, 1, 0, 0);
2140                 }
2141                 en = lcd_dma.xres;
2142                 fn = lcd_dma.yres;
2143                 break;
2144         case 270:
2145                 if (!lcd_dma.mirror) {
2146                         top = PIXADDR(lcd_dma.xres - 1, 0);
2147                         bottom = PIXADDR(0, lcd_dma.yres - 1);
2148                         ei = PIXSTEP(0, 0, 0, 1);
2149                         fi = PIXSTEP(1, lcd_dma.yres - 1, 0, 0);
2150                 } else {
2151                         top = PIXADDR(0, 0);
2152                         bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2153                         ei = PIXSTEP(0, 0, 0, 1);
2154                         fi = PIXSTEP(0, lcd_dma.yres - 1, 1, 0);
2155                 }
2156                 en = lcd_dma.yres;
2157                 fn = lcd_dma.xres;
2158                 break;
2159         default:
2160                 BUG();
2161                 return; /* Suppress warning about uninitialized vars */
2162         }
2163
2164         if (omap_dma_in_1510_mode()) {
2165                 omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U);
2166                 omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L);
2167                 omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U);
2168                 omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L);
2169
2170                 return;
2171         }
2172
2173         /* 1610 regs */
2174         omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U);
2175         omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L);
2176         omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U);
2177         omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L);
2178
2179         omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1);
2180         omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1);
2181
2182         w = omap_readw(OMAP1610_DMA_LCD_CSDP);
2183         w &= ~0x03;
2184         w |= lcd_dma.data_type;
2185         omap_writew(w, OMAP1610_DMA_LCD_CSDP);
2186
2187         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2188         /* Always set the source port as SDRAM for now*/
2189         w &= ~(0x03 << 6);
2190         if (lcd_dma.callback != NULL)
2191                 w |= 1 << 1;            /* Block interrupt enable */
2192         else
2193                 w &= ~(1 << 1);
2194         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2195
2196         if (!(lcd_dma.rotate || lcd_dma.mirror ||
2197               lcd_dma.vxres || lcd_dma.xscale || lcd_dma.yscale))
2198                 return;
2199
2200         w = omap_readw(OMAP1610_DMA_LCD_CCR);
2201         /* Set the double-indexed addressing mode */
2202         w |= (0x03 << 12);
2203         omap_writew(w, OMAP1610_DMA_LCD_CCR);
2204
2205         omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1);
2206         omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U);
2207         omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
2208 }
2209
2210 static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id)
2211 {
2212         u16 w;
2213
2214         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2215         if (unlikely(!(w & (1 << 3)))) {
2216                 printk(KERN_WARNING "Spurious LCD DMA IRQ\n");
2217                 return IRQ_NONE;
2218         }
2219         /* Ack the IRQ */
2220         w |= (1 << 3);
2221         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2222         lcd_dma.active = 0;
2223         if (lcd_dma.callback != NULL)
2224                 lcd_dma.callback(w, lcd_dma.cb_data);
2225
2226         return IRQ_HANDLED;
2227 }
2228
2229 int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
2230                          void *data)
2231 {
2232         spin_lock_irq(&lcd_dma.lock);
2233         if (lcd_dma.reserved) {
2234                 spin_unlock_irq(&lcd_dma.lock);
2235                 printk(KERN_ERR "LCD DMA channel already reserved\n");
2236                 BUG();
2237                 return -EBUSY;
2238         }
2239         lcd_dma.reserved = 1;
2240         spin_unlock_irq(&lcd_dma.lock);
2241         lcd_dma.callback = callback;
2242         lcd_dma.cb_data = data;
2243         lcd_dma.active = 0;
2244         lcd_dma.single_transfer = 0;
2245         lcd_dma.rotate = 0;
2246         lcd_dma.vxres = 0;
2247         lcd_dma.mirror = 0;
2248         lcd_dma.xscale = 0;
2249         lcd_dma.yscale = 0;
2250         lcd_dma.ext_ctrl = 0;
2251         lcd_dma.src_port = 0;
2252
2253         return 0;
2254 }
2255 EXPORT_SYMBOL(omap_request_lcd_dma);
2256
2257 void omap_free_lcd_dma(void)
2258 {
2259         spin_lock(&lcd_dma.lock);
2260         if (!lcd_dma.reserved) {
2261                 spin_unlock(&lcd_dma.lock);
2262                 printk(KERN_ERR "LCD DMA is not reserved\n");
2263                 BUG();
2264                 return;
2265         }
2266         if (!enable_1510_mode)
2267                 omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1,
2268                             OMAP1610_DMA_LCD_CCR);
2269         lcd_dma.reserved = 0;
2270         spin_unlock(&lcd_dma.lock);
2271 }
2272 EXPORT_SYMBOL(omap_free_lcd_dma);
2273
2274 void omap_enable_lcd_dma(void)
2275 {
2276         u16 w;
2277
2278         /*
2279          * Set the Enable bit only if an external controller is
2280          * connected. Otherwise the OMAP internal controller will
2281          * start the transfer when it gets enabled.
2282          */
2283         if (enable_1510_mode || !lcd_dma.ext_ctrl)
2284                 return;
2285
2286         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2287         w |= 1 << 8;
2288         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2289
2290         lcd_dma.active = 1;
2291
2292         w = omap_readw(OMAP1610_DMA_LCD_CCR);
2293         w |= 1 << 7;
2294         omap_writew(w, OMAP1610_DMA_LCD_CCR);
2295 }
2296 EXPORT_SYMBOL(omap_enable_lcd_dma);
2297
2298 void omap_setup_lcd_dma(void)
2299 {
2300         BUG_ON(lcd_dma.active);
2301         if (!enable_1510_mode) {
2302                 /* Set some reasonable defaults */
2303                 omap_writew(0x5440, OMAP1610_DMA_LCD_CCR);
2304                 omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP);
2305                 omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL);
2306         }
2307         set_b1_regs();
2308         if (!enable_1510_mode) {
2309                 u16 w;
2310
2311                 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2312                 /*
2313                  * If DMA was already active set the end_prog bit to have
2314                  * the programmed register set loaded into the active
2315                  * register set.
2316                  */
2317                 w |= 1 << 11;           /* End_prog */
2318                 if (!lcd_dma.single_transfer)
2319                         w |= (3 << 8);  /* Auto_init, repeat */
2320                 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2321         }
2322 }
2323 EXPORT_SYMBOL(omap_setup_lcd_dma);
2324
2325 void omap_stop_lcd_dma(void)
2326 {
2327         u16 w;
2328
2329         lcd_dma.active = 0;
2330         if (enable_1510_mode || !lcd_dma.ext_ctrl)
2331                 return;
2332
2333         w = omap_readw(OMAP1610_DMA_LCD_CCR);
2334         w &= ~(1 << 7);
2335         omap_writew(w, OMAP1610_DMA_LCD_CCR);
2336
2337         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2338         w &= ~(1 << 8);
2339         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2340 }
2341 EXPORT_SYMBOL(omap_stop_lcd_dma);
2342
2343 /*----------------------------------------------------------------------------*/
2344
2345 static int __init omap_init_dma(void)
2346 {
2347         int ch, r;
2348
2349         if (cpu_class_is_omap1()) {
2350                 omap_dma_base = IO_ADDRESS(OMAP1_DMA_BASE);
2351                 dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
2352         } else if (cpu_is_omap24xx()) {
2353                 omap_dma_base = IO_ADDRESS(OMAP24XX_DMA4_BASE);
2354                 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2355         } else if (cpu_is_omap34xx()) {
2356                 omap_dma_base = IO_ADDRESS(OMAP34XX_DMA4_BASE);
2357                 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2358         } else if (cpu_is_omap44xx()) {
2359                 omap_dma_base = IO_ADDRESS(OMAP44XX_DMA4_BASE);
2360                 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2361         } else {
2362                 pr_err("DMA init failed for unsupported omap\n");
2363                 return -ENODEV;
2364         }
2365
2366         if (cpu_class_is_omap2() && omap_dma_reserve_channels
2367                         && (omap_dma_reserve_channels <= dma_lch_count))
2368                 dma_lch_count = omap_dma_reserve_channels;
2369
2370         dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count,
2371                                 GFP_KERNEL);
2372         if (!dma_chan)
2373                 return -ENOMEM;
2374
2375         if (cpu_class_is_omap2()) {
2376                 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
2377                                                 dma_lch_count, GFP_KERNEL);
2378                 if (!dma_linked_lch) {
2379                         kfree(dma_chan);
2380                         return -ENOMEM;
2381                 }
2382         }
2383
2384         if (cpu_is_omap15xx()) {
2385                 printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
2386                 dma_chan_count = 9;
2387                 enable_1510_mode = 1;
2388         } else if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
2389                 printk(KERN_INFO "OMAP DMA hardware version %d\n",
2390                        dma_read(HW_ID));
2391                 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
2392                        (dma_read(CAPS_0_U) << 16) |
2393                        dma_read(CAPS_0_L),
2394                        (dma_read(CAPS_1_U) << 16) |
2395                        dma_read(CAPS_1_L),
2396                        dma_read(CAPS_2), dma_read(CAPS_3),
2397                        dma_read(CAPS_4));
2398                 if (!enable_1510_mode) {
2399                         u16 w;
2400
2401                         /* Disable OMAP 3.0/3.1 compatibility mode. */
2402                         w = dma_read(GSCR);
2403                         w |= 1 << 3;
2404                         dma_write(w, GSCR);
2405                         dma_chan_count = 16;
2406                 } else
2407                         dma_chan_count = 9;
2408                 if (cpu_is_omap16xx()) {
2409                         u16 w;
2410
2411                         /* this would prevent OMAP sleep */
2412                         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2413                         w &= ~(1 << 8);
2414                         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2415                 }
2416         } else if (cpu_class_is_omap2()) {
2417                 u8 revision = dma_read(REVISION) & 0xff;
2418                 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
2419                        revision >> 4, revision & 0xf);
2420                 dma_chan_count = dma_lch_count;
2421         } else {
2422                 dma_chan_count = 0;
2423                 return 0;
2424         }
2425
2426         spin_lock_init(&lcd_dma.lock);
2427         spin_lock_init(&dma_chan_lock);
2428
2429         for (ch = 0; ch < dma_chan_count; ch++) {
2430                 omap_clear_dma(ch);
2431                 dma_chan[ch].dev_id = -1;
2432                 dma_chan[ch].next_lch = -1;
2433
2434                 if (ch >= 6 && enable_1510_mode)
2435                         continue;
2436
2437                 if (cpu_class_is_omap1()) {
2438                         /*
2439                          * request_irq() doesn't like dev_id (ie. ch) being
2440                          * zero, so we have to kludge around this.
2441                          */
2442                         r = request_irq(omap1_dma_irq[ch],
2443                                         omap1_dma_irq_handler, 0, "DMA",
2444                                         (void *) (ch + 1));
2445                         if (r != 0) {
2446                                 int i;
2447
2448                                 printk(KERN_ERR "unable to request IRQ %d "
2449                                        "for DMA (error %d)\n",
2450                                        omap1_dma_irq[ch], r);
2451                                 for (i = 0; i < ch; i++)
2452                                         free_irq(omap1_dma_irq[i],
2453                                                  (void *) (i + 1));
2454                                 return r;
2455                         }
2456                 }
2457         }
2458
2459         if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx())
2460                 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
2461                                 DMA_DEFAULT_FIFO_DEPTH, 0);
2462
2463         if (cpu_class_is_omap2()) {
2464                 int irq;
2465                 if (cpu_is_omap44xx())
2466                         irq = INT_44XX_SDMA_IRQ0;
2467                 else
2468                         irq = INT_24XX_SDMA_IRQ0;
2469                 setup_irq(irq, &omap24xx_dma_irq);
2470         }
2471
2472         /* Enable smartidle idlemodes and autoidle */
2473         if (cpu_is_omap34xx()) {
2474                 u32 v = dma_read(OCP_SYSCONFIG);
2475                 v &= ~(DMA_SYSCONFIG_MIDLEMODE_MASK |
2476                                 DMA_SYSCONFIG_SIDLEMODE_MASK |
2477                                 DMA_SYSCONFIG_AUTOIDLE);
2478                 v |= (DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
2479                         DMA_SYSCONFIG_SIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
2480                         DMA_SYSCONFIG_AUTOIDLE);
2481                 dma_write(v , OCP_SYSCONFIG);
2482         }
2483
2484
2485         /* FIXME: Update LCD DMA to work on 24xx */
2486         if (cpu_class_is_omap1()) {
2487                 r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
2488                                 "LCD DMA", NULL);
2489                 if (r != 0) {
2490                         int i;
2491
2492                         printk(KERN_ERR "unable to request IRQ for LCD DMA "
2493                                "(error %d)\n", r);
2494                         for (i = 0; i < dma_chan_count; i++)
2495                                 free_irq(omap1_dma_irq[i], (void *) (i + 1));
2496                         return r;
2497                 }
2498         }
2499
2500         return 0;
2501 }
2502
2503 arch_initcall(omap_init_dma);
2504
2505 /*
2506  * Reserve the omap SDMA channels using cmdline bootarg
2507  * "omap_dma_reserve_ch=". The valid range is 1 to 32
2508  */
2509 static int __init omap_dma_cmdline_reserve_ch(char *str)
2510 {
2511         if (get_option(&str, &omap_dma_reserve_channels) != 1)
2512                 omap_dma_reserve_channels = 0;
2513         return 1;
2514 }
2515
2516 __setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch);
2517
2518