arch/arm/plat-omap/dma.c

   1 /*
   2  * linux/arch/arm/plat-omap/dma.c
   3  *
   4  * Copyright (C) 2003 - 2008 Nokia Corporation
   5  * Author: Juha Yrjölä <juha.yrjola@nokia.com>
   6  * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
   7  * Graphics DMA and LCD DMA graphics tranformations
   8  * by Imre Deak <imre.deak@nokia.com>
   9  * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
  10  * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
  11  * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
  12  *
  13  * Support functions for the OMAP internal DMA channels.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18  *
  19  */
  20
  21 #include <linux/module.h>
  22 #include <linux/init.h>
  23 #include <linux/sched.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/errno.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/irq.h>
  28 #include <linux/io.h>
  29
  30 #include <asm/system.h>
  31 #include <mach/hardware.h>
  32 #include <mach/dma.h>
  33
  34 #include <mach/tc.h>
  35
  36 #undef DEBUG
  37
  38 #ifndef CONFIG_ARCH_OMAP1
  39 enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
  40         DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
  41 };
  42
  43 enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
  44 #endif
  45
  46 #define OMAP_DMA_ACTIVE                 0x01
  47 #define OMAP_DMA_CCR_EN                 (1 << 7)
  48 #define OMAP2_DMA_CSR_CLEAR_MASK        0xffe
  49
  50 #define OMAP_FUNC_MUX_ARM_BASE          (0xfffe1000 + 0xec)
  51
  52 static int enable_1510_mode;
  53
  54 struct omap_dma_lch {
  55         int next_lch;
  56         int dev_id;
  57         u16 saved_csr;
  58         u16 enabled_irqs;
  59         const char *dev_name;
  60         void (*callback)(int lch, u16 ch_status, void *data);
  61         void *data;
  62
  63 #ifndef CONFIG_ARCH_OMAP1
  64         /* required for Dynamic chaining */
  65         int prev_linked_ch;
  66         int next_linked_ch;
  67         int state;
  68         int chain_id;
  69
  70         int status;
  71 #endif
  72         long flags;
  73 };
  74
  75 struct dma_link_info {
  76         int *linked_dmach_q;
  77         int no_of_lchs_linked;
  78
  79         int q_count;
  80         int q_tail;
  81         int q_head;
  82
  83         int chain_state;
  84         int chain_mode;
  85
  86 };
  87
  88 static struct dma_link_info *dma_linked_lch;
  89
  90 #ifndef CONFIG_ARCH_OMAP1
  91
  92 /* Chain handling macros */
  93 #define OMAP_DMA_CHAIN_QINIT(chain_id)                                  \
  94         do {                                                            \
  95                 dma_linked_lch[chain_id].q_head =                       \
  96                 dma_linked_lch[chain_id].q_tail =                       \
  97                 dma_linked_lch[chain_id].q_count = 0;                   \
  98         } while (0)
  99 #define OMAP_DMA_CHAIN_QFULL(chain_id)                                  \
 100                 (dma_linked_lch[chain_id].no_of_lchs_linked ==          \
 101                 dma_linked_lch[chain_id].q_count)
 102 #define OMAP_DMA_CHAIN_QLAST(chain_id)                                  \
 103         do {                                                            \
 104                 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) ==      \
 105                 dma_linked_lch[chain_id].q_count)                       \
 106         } while (0)
 107 #define OMAP_DMA_CHAIN_QEMPTY(chain_id)                                 \
 108                 (0 == dma_linked_lch[chain_id].q_count)
 109 #define __OMAP_DMA_CHAIN_INCQ(end)                                      \
 110         ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
 111 #define OMAP_DMA_CHAIN_INCQHEAD(chain_id)                               \
 112         do {                                                            \
 113                 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
 114                 dma_linked_lch[chain_id].q_count--;                     \
 115         } while (0)
 116
 117 #define OMAP_DMA_CHAIN_INCQTAIL(chain_id)                               \
 118         do {                                                            \
 119                 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
 120                 dma_linked_lch[chain_id].q_count++; \
 121         } while (0)
 122 #endif
 123
 124 static int dma_lch_count;
 125 static int dma_chan_count;
 126 static int omap_dma_reserve_channels;
 127
 128 static spinlock_t dma_chan_lock;
 129 static struct omap_dma_lch *dma_chan;
 130 static void __iomem *omap_dma_base;
 131
 132 static const u8 omap1_dma_irq[OMAP1_LOGICAL_DMA_CH_COUNT] = {
 133         INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3,
 134         INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7,
 135         INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10,
 136         INT_1610_DMA_CH11, INT_1610_DMA_CH12, INT_1610_DMA_CH13,
 137         INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD
 138 };
 139
 140 static inline void disable_lnk(int lch);
 141 static void omap_disable_channel_irq(int lch);
 142 static inline void omap_enable_channel_irq(int lch);
 143
 144 #define REVISIT_24XX()          printk(KERN_ERR "FIXME: no %s on 24xx\n", \
 145                                                 __func__);
 146
 147 #define dma_read(reg)                                                   \
 148 ({                                                                      \
 149         u32 __val;                                                      \
 150         if (cpu_class_is_omap1())                                       \
 151                 __val = __raw_readw(omap_dma_base + OMAP1_DMA_##reg);   \
 152         else                                                            \
 153                 __val = __raw_readl(omap_dma_base + OMAP_DMA4_##reg);   \
 154         __val;                                                          \
 155 })
 156
 157 #define dma_write(val, reg)                                             \
 158 ({                                                                      \
 159         if (cpu_class_is_omap1())                                       \
 160                 __raw_writew((u16)(val), omap_dma_base + OMAP1_DMA_##reg); \
 161         else                                                            \
 162                 __raw_writel((val), omap_dma_base + OMAP_DMA4_##reg);   \
 163 })
 164
 165 #ifdef CONFIG_ARCH_OMAP15XX
 166 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
 167 int omap_dma_in_1510_mode(void)
 168 {
 169         return enable_1510_mode;
 170 }
 171 #else
 172 #define omap_dma_in_1510_mode()         0
 173 #endif
 174
 175 #ifdef CONFIG_ARCH_OMAP1
 176 static inline int get_gdma_dev(int req)
 177 {
 178         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
 179         int shift = ((req - 1) % 5) * 6;
 180
 181         return ((omap_readl(reg) >> shift) & 0x3f) + 1;
 182 }
 183
 184 static inline void set_gdma_dev(int req, int dev)
 185 {
 186         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
 187         int shift = ((req - 1) % 5) * 6;
 188         u32 l;
 189
 190         l = omap_readl(reg);
 191         l &= ~(0x3f << shift);
 192         l |= (dev - 1) << shift;
 193         omap_writel(l, reg);
 194 }
 195 #else
 196 #define set_gdma_dev(req, dev)  do {} while (0)
 197 #endif
 198
 199 /* Omap1 only */
 200 static void clear_lch_regs(int lch)
 201 {
 202         int i;
 203         void __iomem *lch_base = omap_dma_base + OMAP1_DMA_CH_BASE(lch);
 204
 205         for (i = 0; i < 0x2c; i += 2)
 206                 __raw_writew(0, lch_base + i);
 207 }
 208
 209 void omap_set_dma_priority(int lch, int dst_port, int priority)
 210 {
 211         unsigned long reg;
 212         u32 l;
 213
 214         if (cpu_class_is_omap1()) {
 215                 switch (dst_port) {
 216                 case OMAP_DMA_PORT_OCP_T1:      /* FFFECC00 */
 217                         reg = OMAP_TC_OCPT1_PRIOR;
 218                         break;
 219                 case OMAP_DMA_PORT_OCP_T2:      /* FFFECCD0 */
 220                         reg = OMAP_TC_OCPT2_PRIOR;
 221                         break;
 222                 case OMAP_DMA_PORT_EMIFF:       /* FFFECC08 */
 223                         reg = OMAP_TC_EMIFF_PRIOR;
 224                         break;
 225                 case OMAP_DMA_PORT_EMIFS:       /* FFFECC04 */
 226                         reg = OMAP_TC_EMIFS_PRIOR;
 227                         break;
 228                 default:
 229                         BUG();
 230                         return;
 231                 }
 232                 l = omap_readl(reg);
 233                 l &= ~(0xf << 8);
 234                 l |= (priority & 0xf) << 8;
 235                 omap_writel(l, reg);
 236         }
 237
 238         if (cpu_class_is_omap2()) {
 239                 u32 ccr;
 240
 241                 ccr = dma_read(CCR(lch));
 242                 if (priority)
 243                         ccr |= (1 << 6);
 244                 else
 245                         ccr &= ~(1 << 6);
 246                 dma_write(ccr, CCR(lch));
 247         }
 248 }
 249 EXPORT_SYMBOL(omap_set_dma_priority);
 250
 251 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
 252                                   int frame_count, int sync_mode,
 253                                   int dma_trigger, int src_or_dst_synch)
 254 {
 255         u32 l;
 256
 257         l = dma_read(CSDP(lch));
 258         l &= ~0x03;
 259         l |= data_type;
 260         dma_write(l, CSDP(lch));
 261
 262         if (cpu_class_is_omap1()) {
 263                 u16 ccr;
 264
 265                 ccr = dma_read(CCR(lch));
 266                 ccr &= ~(1 << 5);
 267                 if (sync_mode == OMAP_DMA_SYNC_FRAME)
 268                         ccr |= 1 << 5;
 269                 dma_write(ccr, CCR(lch));
 270
 271                 ccr = dma_read(CCR2(lch));
 272                 ccr &= ~(1 << 2);
 273                 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
 274                         ccr |= 1 << 2;
 275                 dma_write(ccr, CCR2(lch));
 276         }
 277
 278         if (cpu_class_is_omap2() && dma_trigger) {
 279                 u32 val;
 280
 281                 val = dma_read(CCR(lch));
 282
 283                 /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
 284                 val &= ~((3 << 19) | 0x1f);
 285                 val |= (dma_trigger & ~0x1f) << 14;
 286                 val |= dma_trigger & 0x1f;
 287
 288                 if (sync_mode & OMAP_DMA_SYNC_FRAME)
 289                         val |= 1 << 5;
 290                 else
 291                         val &= ~(1 << 5);
 292
 293                 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
 294                         val |= 1 << 18;
 295                 else
 296                         val &= ~(1 << 18);
 297
 298                 if (src_or_dst_synch)
 299                         val |= 1 << 24;         /* source synch */
 300                 else
 301                         val &= ~(1 << 24);      /* dest synch */
 302
 303                 dma_write(val, CCR(lch));
 304         }
 305
 306         dma_write(elem_count, CEN(lch));
 307         dma_write(frame_count, CFN(lch));
 308 }
 309 EXPORT_SYMBOL(omap_set_dma_transfer_params);
 310
 311 void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
 312 {
 313         u16 w;
 314
 315         BUG_ON(omap_dma_in_1510_mode());
 316
 317         if (cpu_class_is_omap2()) {
 318                 REVISIT_24XX();
 319                 return;
 320         }
 321
 322         w = dma_read(CCR2(lch));
 323         w &= ~0x03;
 324
 325         switch (mode) {
 326         case OMAP_DMA_CONSTANT_FILL:
 327                 w |= 0x01;
 328                 break;
 329         case OMAP_DMA_TRANSPARENT_COPY:
 330                 w |= 0x02;
 331                 break;
 332         case OMAP_DMA_COLOR_DIS:
 333                 break;
 334         default:
 335                 BUG();
 336         }
 337         dma_write(w, CCR2(lch));
 338
 339         w = dma_read(LCH_CTRL(lch));
 340         w &= ~0x0f;
 341         /* Default is channel type 2D */
 342         if (mode) {
 343                 dma_write((u16)color, COLOR_L(lch));
 344                 dma_write((u16)(color >> 16), COLOR_U(lch));
 345                 w |= 1;         /* Channel type G */
 346         }
 347         dma_write(w, LCH_CTRL(lch));
 348 }
 349 EXPORT_SYMBOL(omap_set_dma_color_mode);
 350
 351 void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
 352 {
 353         if (cpu_class_is_omap2()) {
 354                 u32 csdp;
 355
 356                 csdp = dma_read(CSDP(lch));
 357                 csdp &= ~(0x3 << 16);
 358                 csdp |= (mode << 16);
 359                 dma_write(csdp, CSDP(lch));
 360         }
 361 }
 362 EXPORT_SYMBOL(omap_set_dma_write_mode);
 363
 364 void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
 365 {
 366         if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
 367                 u32 l;
 368
 369                 l = dma_read(LCH_CTRL(lch));
 370                 l &= ~0x7;
 371                 l |= mode;
 372                 dma_write(l, LCH_CTRL(lch));
 373         }
 374 }
 375 EXPORT_SYMBOL(omap_set_dma_channel_mode);
 376
 377 /* Note that src_port is only for omap1 */
 378 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
 379                              unsigned long src_start,
 380                              int src_ei, int src_fi)
 381 {
 382         u32 l;
 383
 384         if (cpu_class_is_omap1()) {
 385                 u16 w;
 386
 387                 w = dma_read(CSDP(lch));
 388                 w &= ~(0x1f << 2);
 389                 w |= src_port << 2;
 390                 dma_write(w, CSDP(lch));
 391         }
 392
 393         l = dma_read(CCR(lch));
 394         l &= ~(0x03 << 12);
 395         l |= src_amode << 12;
 396         dma_write(l, CCR(lch));
 397
 398         if (cpu_class_is_omap1()) {
 399                 dma_write(src_start >> 16, CSSA_U(lch));
 400                 dma_write((u16)src_start, CSSA_L(lch));
 401         }
 402
 403         if (cpu_class_is_omap2())
 404                 dma_write(src_start, CSSA(lch));
 405
 406         dma_write(src_ei, CSEI(lch));
 407         dma_write(src_fi, CSFI(lch));
 408 }
 409 EXPORT_SYMBOL(omap_set_dma_src_params);
 410
 411 void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
 412 {
 413         omap_set_dma_transfer_params(lch, params->data_type,
 414                                      params->elem_count, params->frame_count,
 415                                      params->sync_mode, params->trigger,
 416                                      params->src_or_dst_synch);
 417         omap_set_dma_src_params(lch, params->src_port,
 418                                 params->src_amode, params->src_start,
 419                                 params->src_ei, params->src_fi);
 420
 421         omap_set_dma_dest_params(lch, params->dst_port,
 422                                  params->dst_amode, params->dst_start,
 423                                  params->dst_ei, params->dst_fi);
 424         if (params->read_prio || params->write_prio)
 425                 omap_dma_set_prio_lch(lch, params->read_prio,
 426                                       params->write_prio);
 427 }
 428 EXPORT_SYMBOL(omap_set_dma_params);
 429
 430 void omap_set_dma_src_index(int lch, int eidx, int fidx)
 431 {
 432         if (cpu_class_is_omap2())
 433                 return;
 434
 435         dma_write(eidx, CSEI(lch));
 436         dma_write(fidx, CSFI(lch));
 437 }
 438 EXPORT_SYMBOL(omap_set_dma_src_index);
 439
 440 void omap_set_dma_src_data_pack(int lch, int enable)
 441 {
 442         u32 l;
 443
 444         l = dma_read(CSDP(lch));
 445         l &= ~(1 << 6);
 446         if (enable)
 447                 l |= (1 << 6);
 448         dma_write(l, CSDP(lch));
 449 }
 450 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
 451
 452 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
 453 {
 454         unsigned int burst = 0;
 455         u32 l;
 456
 457         l = dma_read(CSDP(lch));
 458         l &= ~(0x03 << 7);
 459
 460         switch (burst_mode) {
 461         case OMAP_DMA_DATA_BURST_DIS:
 462                 break;
 463         case OMAP_DMA_DATA_BURST_4:
 464                 if (cpu_class_is_omap2())
 465                         burst = 0x1;
 466                 else
 467                         burst = 0x2;
 468                 break;
 469         case OMAP_DMA_DATA_BURST_8:
 470                 if (cpu_class_is_omap2()) {
 471                         burst = 0x2;
 472                         break;
 473                 }
 474                 /* not supported by current hardware on OMAP1
 475                  * w |= (0x03 << 7);
 476                  * fall through
 477                  */
 478         case OMAP_DMA_DATA_BURST_16:
 479                 if (cpu_class_is_omap2()) {
 480                         burst = 0x3;
 481                         break;
 482                 }
 483                 /* OMAP1 don't support burst 16
 484                  * fall through
 485                  */
 486         default:
 487                 BUG();
 488         }
 489
 490         l |= (burst << 7);
 491         dma_write(l, CSDP(lch));
 492 }
 493 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
 494
 495 /* Note that dest_port is only for OMAP1 */
 496 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
 497                               unsigned long dest_start,
 498                               int dst_ei, int dst_fi)
 499 {
 500         u32 l;
 501
 502         if (cpu_class_is_omap1()) {
 503                 l = dma_read(CSDP(lch));
 504                 l &= ~(0x1f << 9);
 505                 l |= dest_port << 9;
 506                 dma_write(l, CSDP(lch));
 507         }
 508
 509         l = dma_read(CCR(lch));
 510         l &= ~(0x03 << 14);
 511         l |= dest_amode << 14;
 512         dma_write(l, CCR(lch));
 513
 514         if (cpu_class_is_omap1()) {
 515                 dma_write(dest_start >> 16, CDSA_U(lch));
 516                 dma_write(dest_start, CDSA_L(lch));
 517         }
 518
 519         if (cpu_class_is_omap2())
 520                 dma_write(dest_start, CDSA(lch));
 521
 522         dma_write(dst_ei, CDEI(lch));
 523         dma_write(dst_fi, CDFI(lch));
 524 }
 525 EXPORT_SYMBOL(omap_set_dma_dest_params);
 526
 527 void omap_set_dma_dest_index(int lch, int eidx, int fidx)
 528 {
 529         if (cpu_class_is_omap2())
 530                 return;
 531
 532         dma_write(eidx, CDEI(lch));
 533         dma_write(fidx, CDFI(lch));
 534 }
 535 EXPORT_SYMBOL(omap_set_dma_dest_index);
 536
 537 void omap_set_dma_dest_data_pack(int lch, int enable)
 538 {
 539         u32 l;
 540
 541         l = dma_read(CSDP(lch));
 542         l &= ~(1 << 13);
 543         if (enable)
 544                 l |= 1 << 13;
 545         dma_write(l, CSDP(lch));
 546 }
 547 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
 548
 549 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
 550 {
 551         unsigned int burst = 0;
 552         u32 l;
 553
 554         l = dma_read(CSDP(lch));
 555         l &= ~(0x03 << 14);
 556
 557         switch (burst_mode) {
 558         case OMAP_DMA_DATA_BURST_DIS:
 559                 break;
 560         case OMAP_DMA_DATA_BURST_4:
 561                 if (cpu_class_is_omap2())
 562                         burst = 0x1;
 563                 else
 564                         burst = 0x2;
 565                 break;
 566         case OMAP_DMA_DATA_BURST_8:
 567                 if (cpu_class_is_omap2())
 568                         burst = 0x2;
 569                 else
 570                         burst = 0x3;
 571                 break;
 572         case OMAP_DMA_DATA_BURST_16:
 573                 if (cpu_class_is_omap2()) {
 574                         burst = 0x3;
 575                         break;
 576                 }
 577                 /* OMAP1 don't support burst 16
 578                  * fall through
 579                  */
 580         default:
 581                 printk(KERN_ERR "Invalid DMA burst mode\n");
 582                 BUG();
 583                 return;
 584         }
 585         l |= (burst << 14);
 586         dma_write(l, CSDP(lch));
 587 }
 588 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
 589
 590 static inline void omap_enable_channel_irq(int lch)
 591 {
 592         u32 status;
 593
 594         /* Clear CSR */
 595         if (cpu_class_is_omap1())
 596                 status = dma_read(CSR(lch));
 597         else if (cpu_class_is_omap2())
 598                 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
 599
 600         /* Enable some nice interrupts. */
 601         dma_write(dma_chan[lch].enabled_irqs, CICR(lch));
 602 }
 603
 604 static void omap_disable_channel_irq(int lch)
 605 {
 606         if (cpu_class_is_omap2())
 607                 dma_write(0, CICR(lch));
 608 }
 609
 610 void omap_enable_dma_irq(int lch, u16 bits)
 611 {
 612         dma_chan[lch].enabled_irqs |= bits;
 613 }
 614 EXPORT_SYMBOL(omap_enable_dma_irq);
 615
 616 void omap_disable_dma_irq(int lch, u16 bits)
 617 {
 618         dma_chan[lch].enabled_irqs &= ~bits;
 619 }
 620 EXPORT_SYMBOL(omap_disable_dma_irq);
 621
 622 static inline void enable_lnk(int lch)
 623 {
 624         u32 l;
 625
 626         l = dma_read(CLNK_CTRL(lch));
 627
 628         if (cpu_class_is_omap1())
 629                 l &= ~(1 << 14);
 630
 631         /* Set the ENABLE_LNK bits */
 632         if (dma_chan[lch].next_lch != -1)
 633                 l = dma_chan[lch].next_lch | (1 << 15);
 634
 635 #ifndef CONFIG_ARCH_OMAP1
 636         if (cpu_class_is_omap2())
 637                 if (dma_chan[lch].next_linked_ch != -1)
 638                         l = dma_chan[lch].next_linked_ch | (1 << 15);
 639 #endif
 640
 641         dma_write(l, CLNK_CTRL(lch));
 642 }
 643
 644 static inline void disable_lnk(int lch)
 645 {
 646         u32 l;
 647
 648         l = dma_read(CLNK_CTRL(lch));
 649
 650         /* Disable interrupts */
 651         if (cpu_class_is_omap1()) {
 652                 dma_write(0, CICR(lch));
 653                 /* Set the STOP_LNK bit */
 654                 l |= 1 << 14;
 655         }
 656
 657         if (cpu_class_is_omap2()) {
 658                 omap_disable_channel_irq(lch);
 659                 /* Clear the ENABLE_LNK bit */
 660                 l &= ~(1 << 15);
 661         }
 662
 663         dma_write(l, CLNK_CTRL(lch));
 664         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
 665 }
 666
 667 static inline void omap2_enable_irq_lch(int lch)
 668 {
 669         u32 val;
 670
 671         if (!cpu_class_is_omap2())
 672                 return;
 673
 674         val = dma_read(IRQENABLE_L0);
 675         val |= 1 << lch;
 676         dma_write(val, IRQENABLE_L0);
 677 }
 678
 679 int omap_request_dma(int dev_id, const char *dev_name,
 680                      void (*callback)(int lch, u16 ch_status, void *data),
 681                      void *data, int *dma_ch_out)
 682 {
 683         int ch, free_ch = -1;
 684         unsigned long flags;
 685         struct omap_dma_lch *chan;
 686
 687         spin_lock_irqsave(&dma_chan_lock, flags);
 688         for (ch = 0; ch < dma_chan_count; ch++) {
 689                 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
 690                         free_ch = ch;
 691                         if (dev_id == 0)
 692                                 break;
 693                 }
 694         }
 695         if (free_ch == -1) {
 696                 spin_unlock_irqrestore(&dma_chan_lock, flags);
 697                 return -EBUSY;
 698         }
 699         chan = dma_chan + free_ch;
 700         chan->dev_id = dev_id;
 701
 702         if (cpu_class_is_omap1())
 703                 clear_lch_regs(free_ch);
 704
 705         if (cpu_class_is_omap2())
 706                 omap_clear_dma(free_ch);
 707
 708         spin_unlock_irqrestore(&dma_chan_lock, flags);
 709
 710         chan->dev_name = dev_name;
 711         chan->callback = callback;
 712         chan->data = data;
 713         chan->flags = 0;
 714
 715 #ifndef CONFIG_ARCH_OMAP1
 716         if (cpu_class_is_omap2()) {
 717                 chan->chain_id = -1;
 718                 chan->next_linked_ch = -1;
 719         }
 720 #endif
 721
 722         chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
 723
 724         if (cpu_class_is_omap1())
 725                 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
 726         else if (cpu_class_is_omap2())
 727                 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
 728                         OMAP2_DMA_TRANS_ERR_IRQ;
 729
 730         if (cpu_is_omap16xx()) {
 731                 /* If the sync device is set, configure it dynamically. */
 732                 if (dev_id != 0) {
 733                         set_gdma_dev(free_ch + 1, dev_id);
 734                         dev_id = free_ch + 1;
 735                 }
 736                 /*
 737                  * Disable the 1510 compatibility mode and set the sync device
 738                  * id.
 739                  */
 740                 dma_write(dev_id | (1 << 10), CCR(free_ch));
 741         } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) {
 742                 dma_write(dev_id, CCR(free_ch));
 743         }
 744
 745         if (cpu_class_is_omap2()) {
 746                 omap2_enable_irq_lch(free_ch);
 747                 omap_enable_channel_irq(free_ch);
 748                 /* Clear the CSR register and IRQ status register */
 749                 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(free_ch));
 750                 dma_write(1 << free_ch, IRQSTATUS_L0);
 751         }
 752
 753         *dma_ch_out = free_ch;
 754
 755         return 0;
 756 }
 757 EXPORT_SYMBOL(omap_request_dma);
 758
 759 void omap_free_dma(int lch)
 760 {
 761         unsigned long flags;
 762
 763         spin_lock_irqsave(&dma_chan_lock, flags);
 764         if (dma_chan[lch].dev_id == -1) {
 765                 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
 766                        lch);
 767                 spin_unlock_irqrestore(&dma_chan_lock, flags);
 768                 return;
 769         }
 770
 771         dma_chan[lch].dev_id = -1;
 772         dma_chan[lch].next_lch = -1;
 773         dma_chan[lch].callback = NULL;
 774         spin_unlock_irqrestore(&dma_chan_lock, flags);
 775
 776         if (cpu_class_is_omap1()) {
 777                 /* Disable all DMA interrupts for the channel. */
 778                 dma_write(0, CICR(lch));
 779                 /* Make sure the DMA transfer is stopped. */
 780                 dma_write(0, CCR(lch));
 781         }
 782
 783         if (cpu_class_is_omap2()) {
 784                 u32 val;
 785                 /* Disable interrupts */
 786                 val = dma_read(IRQENABLE_L0);
 787                 val &= ~(1 << lch);
 788                 dma_write(val, IRQENABLE_L0);
 789
 790                 /* Clear the CSR register and IRQ status register */
 791                 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
 792                 dma_write(1 << lch, IRQSTATUS_L0);
 793
 794                 /* Disable all DMA interrupts for the channel. */
 795                 dma_write(0, CICR(lch));
 796
 797                 /* Make sure the DMA transfer is stopped. */
 798                 dma_write(0, CCR(lch));
 799                 omap_clear_dma(lch);
 800         }
 801 }
 802 EXPORT_SYMBOL(omap_free_dma);
 803
 804 /**
 805  * @brief omap_dma_set_global_params : Set global priority settings for dma
 806  *
 807  * @param arb_rate
 808  * @param max_fifo_depth
 809  * @param tparams - Number of thereads to reserve : DMA_THREAD_RESERVE_NORM
 810  *                                                  DMA_THREAD_RESERVE_ONET
 811  *                                                  DMA_THREAD_RESERVE_TWOT
 812  *                                                  DMA_THREAD_RESERVE_THREET
 813  */
 814 void
 815 omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
 816 {
 817         u32 reg;
 818
 819         if (!cpu_class_is_omap2()) {
 820                 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
 821                 return;
 822         }
 823
 824         if (arb_rate == 0)
 825                 arb_rate = 1;
 826
 827         reg = (arb_rate & 0xff) << 16;
 828         reg |= (0xff & max_fifo_depth);
 829
 830         dma_write(reg, GCR);
 831 }
 832 EXPORT_SYMBOL(omap_dma_set_global_params);
 833
 834 /**
 835  * @brief omap_dma_set_prio_lch : Set channel wise priority settings
 836  *
 837  * @param lch
 838  * @param read_prio - Read priority
 839  * @param write_prio - Write priority
 840  * Both of the above can be set with one of the following values :
 841  *      DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
 842  */
 843 int
 844 omap_dma_set_prio_lch(int lch, unsigned char read_prio,
 845                       unsigned char write_prio)
 846 {
 847         u32 l;
 848
 849         if (unlikely((lch < 0 || lch >= dma_lch_count))) {
 850                 printk(KERN_ERR "Invalid channel id\n");
 851                 return -EINVAL;
 852         }
 853         l = dma_read(CCR(lch));
 854         l &= ~((1 << 6) | (1 << 26));
 855         if (cpu_is_omap2430() || cpu_is_omap34xx())
 856                 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
 857         else
 858                 l |= ((read_prio & 0x1) << 6);
 859
 860         dma_write(l, CCR(lch));
 861
 862         return 0;
 863 }
 864 EXPORT_SYMBOL(omap_dma_set_prio_lch);
 865
 866 /*
 867  * Clears any DMA state so the DMA engine is ready to restart with new buffers
 868  * through omap_start_dma(). Any buffers in flight are discarded.
 869  */
 870 void omap_clear_dma(int lch)
 871 {
 872         unsigned long flags;
 873
 874         local_irq_save(flags);
 875
 876         if (cpu_class_is_omap1()) {
 877                 u32 l;
 878
 879                 l = dma_read(CCR(lch));
 880                 l &= ~OMAP_DMA_CCR_EN;
 881                 dma_write(l, CCR(lch));
 882
 883                 /* Clear pending interrupts */
 884                 l = dma_read(CSR(lch));
 885         }
 886
 887         if (cpu_class_is_omap2()) {
 888                 int i;
 889                 void __iomem *lch_base = omap_dma_base + OMAP_DMA4_CH_BASE(lch);
 890                 for (i = 0; i < 0x44; i += 4)
 891                         __raw_writel(0, lch_base + i);
 892         }
 893
 894         local_irq_restore(flags);
 895 }
 896 EXPORT_SYMBOL(omap_clear_dma);
 897
 898 void omap_start_dma(int lch)
 899 {
 900         u32 l;
 901
 902         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
 903                 int next_lch, cur_lch;
 904                 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
 905
 906                 dma_chan_link_map[lch] = 1;
 907                 /* Set the link register of the first channel */
 908                 enable_lnk(lch);
 909
 910                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
 911                 cur_lch = dma_chan[lch].next_lch;
 912                 do {
 913                         next_lch = dma_chan[cur_lch].next_lch;
 914
 915                         /* The loop case: we've been here already */
 916                         if (dma_chan_link_map[cur_lch])
 917                                 break;
 918                         /* Mark the current channel */
 919                         dma_chan_link_map[cur_lch] = 1;
 920
 921                         enable_lnk(cur_lch);
 922                         omap_enable_channel_irq(cur_lch);
 923
 924                         cur_lch = next_lch;
 925                 } while (next_lch != -1);
 926         } else if (cpu_class_is_omap2()) {
 927                 /* Errata: Need to write lch even if not using chaining */
 928                 dma_write(lch, CLNK_CTRL(lch));
 929         }
 930
 931         omap_enable_channel_irq(lch);
 932
 933         l = dma_read(CCR(lch));
 934
 935         /*
 936          * Errata: On ES2.0 BUFFERING disable must be set.
 937          * This will always fail on ES1.0
 938          */
 939         if (cpu_is_omap24xx())
 940                 l |= OMAP_DMA_CCR_EN;
 941
 942         l |= OMAP_DMA_CCR_EN;
 943         dma_write(l, CCR(lch));
 944
 945         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
 946 }
 947 EXPORT_SYMBOL(omap_start_dma);
 948
 949 void omap_stop_dma(int lch)
 950 {
 951         u32 l;
 952
 953         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
 954                 int next_lch, cur_lch = lch;
 955                 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
 956
 957                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
 958                 do {
 959                         /* The loop case: we've been here already */
 960                         if (dma_chan_link_map[cur_lch])
 961                                 break;
 962                         /* Mark the current channel */
 963                         dma_chan_link_map[cur_lch] = 1;
 964
 965                         disable_lnk(cur_lch);
 966
 967                         next_lch = dma_chan[cur_lch].next_lch;
 968                         cur_lch = next_lch;
 969                 } while (next_lch != -1);
 970
 971                 return;
 972         }
 973
 974         /* Disable all interrupts on the channel */
 975         if (cpu_class_is_omap1())
 976                 dma_write(0, CICR(lch));
 977
 978         l = dma_read(CCR(lch));
 979         l &= ~OMAP_DMA_CCR_EN;
 980         dma_write(l, CCR(lch));
 981
 982         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
 983 }
 984 EXPORT_SYMBOL(omap_stop_dma);
 985
 986 /*
 987  * Allows changing the DMA callback function or data. This may be needed if
 988  * the driver shares a single DMA channel for multiple dma triggers.
 989  */
 990 int omap_set_dma_callback(int lch,
 991                           void (*callback)(int lch, u16 ch_status, void *data),
 992                           void *data)
 993 {
 994         unsigned long flags;
 995
 996         if (lch < 0)
 997                 return -ENODEV;
 998
 999         spin_lock_irqsave(&dma_chan_lock, flags);
1000         if (dma_chan[lch].dev_id == -1) {
1001                 printk(KERN_ERR "DMA callback for not set for free channel\n");
1002                 spin_unlock_irqrestore(&dma_chan_lock, flags);
1003                 return -EINVAL;
1004         }
1005         dma_chan[lch].callback = callback;
1006         dma_chan[lch].data = data;
1007         spin_unlock_irqrestore(&dma_chan_lock, flags);
1008
1009         return 0;
1010 }
1011 EXPORT_SYMBOL(omap_set_dma_callback);
1012
1013 /*
1014  * Returns current physical source address for the given DMA channel.
1015  * If the channel is running the caller must disable interrupts prior calling
1016  * this function and process the returned value before re-enabling interrupt to
1017  * prevent races with the interrupt handler. Note that in continuous mode there
1018  * is a chance for CSSA_L register overflow inbetween the two reads resulting
1019  * in incorrect return value.
1020  */
1021 dma_addr_t omap_get_dma_src_pos(int lch)
1022 {
1023         dma_addr_t offset = 0;
1024
1025         if (cpu_is_omap15xx())
1026                 offset = dma_read(CPC(lch));
1027         else
1028                 offset = dma_read(CSAC(lch));
1029
1030         /*
1031          * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1032          * read before the DMA controller finished disabling the channel.
1033          */
1034         if (!cpu_is_omap15xx() && offset == 0)
1035                 offset = dma_read(CSAC(lch));
1036
1037         if (cpu_class_is_omap1())
1038                 offset |= (dma_read(CSSA_U(lch)) << 16);
1039
1040         return offset;
1041 }
1042 EXPORT_SYMBOL(omap_get_dma_src_pos);
1043
1044 /*
1045  * Returns current physical destination address for the given DMA channel.
1046  * If the channel is running the caller must disable interrupts prior calling
1047  * this function and process the returned value before re-enabling interrupt to
1048  * prevent races with the interrupt handler. Note that in continuous mode there
1049  * is a chance for CDSA_L register overflow inbetween the two reads resulting
1050  * in incorrect return value.
1051  */
1052 dma_addr_t omap_get_dma_dst_pos(int lch)
1053 {
1054         dma_addr_t offset = 0;
1055
1056         if (cpu_is_omap15xx())
1057                 offset = dma_read(CPC(lch));
1058         else
1059                 offset = dma_read(CDAC(lch));
1060
1061         /*
1062          * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1063          * read before the DMA controller finished disabling the channel.
1064          */
1065         if (!cpu_is_omap15xx() && offset == 0)
1066                 offset = dma_read(CDAC(lch));
1067
1068         if (cpu_class_is_omap1())
1069                 offset |= (dma_read(CDSA_U(lch)) << 16);
1070
1071         return offset;
1072 }
1073 EXPORT_SYMBOL(omap_get_dma_dst_pos);
1074
1075 int omap_get_dma_active_status(int lch)
1076 {
1077         return (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN) != 0;
1078 }
1079 EXPORT_SYMBOL(omap_get_dma_active_status);
1080
1081 int omap_dma_running(void)
1082 {
1083         int lch;
1084
1085         /* Check if LCD DMA is running */
1086         if (cpu_is_omap16xx())
1087                 if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN)
1088                         return 1;
1089
1090         for (lch = 0; lch < dma_chan_count; lch++)
1091                 if (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN)
1092                         return 1;
1093
1094         return 0;
1095 }
1096
1097 /*
1098  * lch_queue DMA will start right after lch_head one is finished.
1099  * For this DMA link to start, you still need to start (see omap_start_dma)
1100  * the first one. That will fire up the entire queue.
1101  */
1102 void omap_dma_link_lch(int lch_head, int lch_queue)
1103 {
1104         if (omap_dma_in_1510_mode()) {
1105                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1106                 BUG();
1107                 return;
1108         }
1109
1110         if ((dma_chan[lch_head].dev_id == -1) ||
1111             (dma_chan[lch_queue].dev_id == -1)) {
1112                 printk(KERN_ERR "omap_dma: trying to link "
1113                        "non requested channels\n");
1114                 dump_stack();
1115         }
1116
1117         dma_chan[lch_head].next_lch = lch_queue;
1118 }
1119 EXPORT_SYMBOL(omap_dma_link_lch);
1120
1121 /*
1122  * Once the DMA queue is stopped, we can destroy it.
1123  */
1124 void omap_dma_unlink_lch(int lch_head, int lch_queue)
1125 {
1126         if (omap_dma_in_1510_mode()) {
1127                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1128                 BUG();
1129                 return;
1130         }
1131
1132         if (dma_chan[lch_head].next_lch != lch_queue ||
1133             dma_chan[lch_head].next_lch == -1) {
1134                 printk(KERN_ERR "omap_dma: trying to unlink "
1135                        "non linked channels\n");
1136                 dump_stack();
1137         }
1138
1139         if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
1140             (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) {
1141                 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
1142                        "before unlinking\n");
1143                 dump_stack();
1144         }
1145
1146         dma_chan[lch_head].next_lch = -1;
1147 }
1148 EXPORT_SYMBOL(omap_dma_unlink_lch);
1149
1150 /*----------------------------------------------------------------------------*/
1151
1152 #ifndef CONFIG_ARCH_OMAP1
1153 /* Create chain of DMA channesls */
1154 static void create_dma_lch_chain(int lch_head, int lch_queue)
1155 {
1156         u32 l;
1157
1158         /* Check if this is the first link in chain */
1159         if (dma_chan[lch_head].next_linked_ch == -1) {
1160                 dma_chan[lch_head].next_linked_ch = lch_queue;
1161                 dma_chan[lch_head].prev_linked_ch = lch_queue;
1162                 dma_chan[lch_queue].next_linked_ch = lch_head;
1163                 dma_chan[lch_queue].prev_linked_ch = lch_head;
1164         }
1165
1166         /* a link exists, link the new channel in circular chain */
1167         else {
1168                 dma_chan[lch_queue].next_linked_ch =
1169                                         dma_chan[lch_head].next_linked_ch;
1170                 dma_chan[lch_queue].prev_linked_ch = lch_head;
1171                 dma_chan[lch_head].next_linked_ch = lch_queue;
1172                 dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
1173                                         lch_queue;
1174         }
1175
1176         l = dma_read(CLNK_CTRL(lch_head));
1177         l &= ~(0x1f);
1178         l |= lch_queue;
1179         dma_write(l, CLNK_CTRL(lch_head));
1180
1181         l = dma_read(CLNK_CTRL(lch_queue));
1182         l &= ~(0x1f);
1183         l |= (dma_chan[lch_queue].next_linked_ch);
1184         dma_write(l, CLNK_CTRL(lch_queue));
1185 }
1186
1187 /**
1188  * @brief omap_request_dma_chain : Request a chain of DMA channels
1189  *
1190  * @param dev_id - Device id using the dma channel
1191  * @param dev_name - Device name
1192  * @param callback - Call back function
1193  * @chain_id -
1194  * @no_of_chans - Number of channels requested
1195  * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1196  *                                            OMAP_DMA_DYNAMIC_CHAIN
1197  * @params - Channel parameters
1198  *
1199  * @return - Succes : 0
1200  *           Failure: -EINVAL/-ENOMEM
1201  */
1202 int omap_request_dma_chain(int dev_id, const char *dev_name,
1203                            void (*callback) (int chain_id, u16 ch_status,
1204                                              void *data),
1205                            int *chain_id, int no_of_chans, int chain_mode,
1206                            struct omap_dma_channel_params params)
1207 {
1208         int *channels;
1209         int i, err;
1210
1211         /* Is the chain mode valid ? */
1212         if (chain_mode != OMAP_DMA_STATIC_CHAIN
1213                         && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
1214                 printk(KERN_ERR "Invalid chain mode requested\n");
1215                 return -EINVAL;
1216         }
1217
1218         if (unlikely((no_of_chans < 1
1219                         || no_of_chans > dma_lch_count))) {
1220                 printk(KERN_ERR "Invalid Number of channels requested\n");
1221                 return -EINVAL;
1222         }
1223
1224         /* Allocate a queue to maintain the status of the channels
1225          * in the chain */
1226         channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
1227         if (channels == NULL) {
1228                 printk(KERN_ERR "omap_dma: No memory for channel queue\n");
1229                 return -ENOMEM;
1230         }
1231
1232         /* request and reserve DMA channels for the chain */
1233         for (i = 0; i < no_of_chans; i++) {
1234                 err = omap_request_dma(dev_id, dev_name,
1235                                         callback, NULL, &channels[i]);
1236                 if (err < 0) {
1237                         int j;
1238                         for (j = 0; j < i; j++)
1239                                 omap_free_dma(channels[j]);
1240                         kfree(channels);
1241                         printk(KERN_ERR "omap_dma: Request failed %d\n", err);
1242                         return err;
1243                 }
1244                 dma_chan[channels[i]].prev_linked_ch = -1;
1245                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1246
1247                 /*
1248                  * Allowing client drivers to set common parameters now,
1249                  * so that later only relevant (src_start, dest_start
1250                  * and element count) can be set
1251                  */
1252                 omap_set_dma_params(channels[i], &params);
1253         }
1254
1255         *chain_id = channels[0];
1256         dma_linked_lch[*chain_id].linked_dmach_q = channels;
1257         dma_linked_lch[*chain_id].chain_mode = chain_mode;
1258         dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1259         dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;
1260
1261         for (i = 0; i < no_of_chans; i++)
1262                 dma_chan[channels[i]].chain_id = *chain_id;
1263
1264         /* Reset the Queue pointers */
1265         OMAP_DMA_CHAIN_QINIT(*chain_id);
1266
1267         /* Set up the chain */
1268         if (no_of_chans == 1)
1269                 create_dma_lch_chain(channels[0], channels[0]);
1270         else {
1271                 for (i = 0; i < (no_of_chans - 1); i++)
1272                         create_dma_lch_chain(channels[i], channels[i + 1]);
1273         }
1274
1275         return 0;
1276 }
1277 EXPORT_SYMBOL(omap_request_dma_chain);
1278
1279 /**
1280  * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1281  * params after setting it. Dont do this while dma is running!!
1282  *
1283  * @param chain_id - Chained logical channel id.
1284  * @param params
1285  *
1286  * @return - Success : 0
1287  *           Failure : -EINVAL
1288  */
1289 int omap_modify_dma_chain_params(int chain_id,
1290                                 struct omap_dma_channel_params params)
1291 {
1292         int *channels;
1293         u32 i;
1294
1295         /* Check for input params */
1296         if (unlikely((chain_id < 0
1297                         || chain_id >= dma_lch_count))) {
1298                 printk(KERN_ERR "Invalid chain id\n");
1299                 return -EINVAL;
1300         }
1301
1302         /* Check if the chain exists */
1303         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1304                 printk(KERN_ERR "Chain doesn't exists\n");
1305                 return -EINVAL;
1306         }
1307         channels = dma_linked_lch[chain_id].linked_dmach_q;
1308
1309         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1310                 /*
1311                  * Allowing client drivers to set common parameters now,
1312                  * so that later only relevant (src_start, dest_start
1313                  * and element count) can be set
1314                  */
1315                 omap_set_dma_params(channels[i], &params);
1316         }
1317
1318         return 0;
1319 }
1320 EXPORT_SYMBOL(omap_modify_dma_chain_params);
1321
1322 /**
1323  * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1324  *
1325  * @param chain_id
1326  *
1327  * @return - Success : 0
1328  *           Failure : -EINVAL
1329  */
1330 int omap_free_dma_chain(int chain_id)
1331 {
1332         int *channels;
1333         u32 i;
1334
1335         /* Check for input params */
1336         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1337                 printk(KERN_ERR "Invalid chain id\n");
1338                 return -EINVAL;
1339         }
1340
1341         /* Check if the chain exists */
1342         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1343                 printk(KERN_ERR "Chain doesn't exists\n");
1344                 return -EINVAL;
1345         }
1346
1347         channels = dma_linked_lch[chain_id].linked_dmach_q;
1348         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1349                 dma_chan[channels[i]].next_linked_ch = -1;
1350                 dma_chan[channels[i]].prev_linked_ch = -1;
1351                 dma_chan[channels[i]].chain_id = -1;
1352                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1353                 omap_free_dma(channels[i]);
1354         }
1355
1356         kfree(channels);
1357
1358         dma_linked_lch[chain_id].linked_dmach_q = NULL;
1359         dma_linked_lch[chain_id].chain_mode = -1;
1360         dma_linked_lch[chain_id].chain_state = -1;
1361
1362         return (0);
1363 }
1364 EXPORT_SYMBOL(omap_free_dma_chain);
1365
1366 /**
1367  * @brief omap_dma_chain_status - Check if the chain is in
1368  * active / inactive state.
1369  * @param chain_id
1370  *
1371  * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1372  *           Failure : -EINVAL
1373  */
1374 int omap_dma_chain_status(int chain_id)
1375 {
1376         /* Check for input params */
1377         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1378                 printk(KERN_ERR "Invalid chain id\n");
1379                 return -EINVAL;
1380         }
1381
1382         /* Check if the chain exists */
1383         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1384                 printk(KERN_ERR "Chain doesn't exists\n");
1385                 return -EINVAL;
1386         }
1387         pr_debug("CHAINID=%d, qcnt=%d\n", chain_id,
1388                         dma_linked_lch[chain_id].q_count);
1389
1390         if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
1391                 return OMAP_DMA_CHAIN_INACTIVE;
1392
1393         return OMAP_DMA_CHAIN_ACTIVE;
1394 }
1395 EXPORT_SYMBOL(omap_dma_chain_status);
1396
1397 /**
1398  * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1399  * set the params and start the transfer.
1400  *
1401  * @param chain_id
1402  * @param src_start - buffer start address
1403  * @param dest_start - Dest address
1404  * @param elem_count
1405  * @param frame_count
1406  * @param callbk_data - channel callback parameter data.
1407  *
1408  * @return  - Success : 0
1409  *            Failure: -EINVAL/-EBUSY
1410  */
1411 int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1412                         int elem_count, int frame_count, void *callbk_data)
1413 {
1414         int *channels;
1415         u32 l, lch;
1416         int start_dma = 0;
1417
1418         /*
1419          * if buffer size is less than 1 then there is
1420          * no use of starting the chain
1421          */
1422         if (elem_count < 1) {
1423                 printk(KERN_ERR "Invalid buffer size\n");
1424                 return -EINVAL;
1425         }
1426
1427         /* Check for input params */
1428         if (unlikely((chain_id < 0
1429                         || chain_id >= dma_lch_count))) {
1430                 printk(KERN_ERR "Invalid chain id\n");
1431                 return -EINVAL;
1432         }
1433
1434         /* Check if the chain exists */
1435         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1436                 printk(KERN_ERR "Chain doesn't exist\n");
1437                 return -EINVAL;
1438         }
1439
1440         /* Check if all the channels in chain are in use */
1441         if (OMAP_DMA_CHAIN_QFULL(chain_id))
1442                 return -EBUSY;
1443
1444         /* Frame count may be negative in case of indexed transfers */
1445         channels = dma_linked_lch[chain_id].linked_dmach_q;
1446
1447         /* Get a free channel */
1448         lch = channels[dma_linked_lch[chain_id].q_tail];
1449
1450         /* Store the callback data */
1451         dma_chan[lch].data = callbk_data;
1452
1453         /* Increment the q_tail */
1454         OMAP_DMA_CHAIN_INCQTAIL(chain_id);
1455
1456         /* Set the params to the free channel */
1457         if (src_start != 0)
1458                 dma_write(src_start, CSSA(lch));
1459         if (dest_start != 0)
1460                 dma_write(dest_start, CDSA(lch));
1461
1462         /* Write the buffer size */
1463         dma_write(elem_count, CEN(lch));
1464         dma_write(frame_count, CFN(lch));
1465
1466         /*
1467          * If the chain is dynamically linked,
1468          * then we may have to start the chain if its not active
1469          */
1470         if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
1471
1472                 /*
1473                  * In Dynamic chain, if the chain is not started,
1474                  * queue the channel
1475                  */
1476                 if (dma_linked_lch[chain_id].chain_state ==
1477                                                 DMA_CHAIN_NOTSTARTED) {
1478                         /* Enable the link in previous channel */
1479                         if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1480                                                                 DMA_CH_QUEUED)
1481                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1482                         dma_chan[lch].state = DMA_CH_QUEUED;
1483                 }
1484
1485                 /*
1486                  * Chain is already started, make sure its active,
1487                  * if not then start the chain
1488                  */
1489                 else {
1490                         start_dma = 1;
1491
1492                         if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1493                                                         DMA_CH_STARTED) {
1494                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1495                                 dma_chan[lch].state = DMA_CH_QUEUED;
1496                                 start_dma = 0;
1497                                 if (0 == ((1 << 7) & dma_read(
1498                                         CCR(dma_chan[lch].prev_linked_ch)))) {
1499                                         disable_lnk(dma_chan[lch].
1500                                                     prev_linked_ch);
1501                                         pr_debug("\n prev ch is stopped\n");
1502                                         start_dma = 1;
1503                                 }
1504                         }
1505
1506                         else if (dma_chan[dma_chan[lch].prev_linked_ch].state
1507                                                         == DMA_CH_QUEUED) {
1508                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1509                                 dma_chan[lch].state = DMA_CH_QUEUED;
1510                                 start_dma = 0;
1511                         }
1512                         omap_enable_channel_irq(lch);
1513
1514                         l = dma_read(CCR(lch));
1515
1516                         if ((0 == (l & (1 << 24))))
1517                                 l &= ~(1 << 25);
1518                         else
1519                                 l |= (1 << 25);
1520                         if (start_dma == 1) {
1521                                 if (0 == (l & (1 << 7))) {
1522                                         l |= (1 << 7);
1523                                         dma_chan[lch].state = DMA_CH_STARTED;
1524                                         pr_debug("starting %d\n", lch);
1525                                         dma_write(l, CCR(lch));
1526                                 } else
1527                                         start_dma = 0;
1528                         } else {
1529                                 if (0 == (l & (1 << 7)))
1530                                         dma_write(l, CCR(lch));
1531                         }
1532                         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1533                 }
1534         }
1535
1536         return 0;
1537 }
1538 EXPORT_SYMBOL(omap_dma_chain_a_transfer);
1539
1540 /**
1541  * @brief omap_start_dma_chain_transfers - Start the chain
1542  *
1543  * @param chain_id
1544  *
1545  * @return - Success : 0
1546  *           Failure : -EINVAL/-EBUSY
1547  */
1548 int omap_start_dma_chain_transfers(int chain_id)
1549 {
1550         int *channels;
1551         u32 l, i;
1552
1553         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1554                 printk(KERN_ERR "Invalid chain id\n");
1555                 return -EINVAL;
1556         }
1557
1558         channels = dma_linked_lch[chain_id].linked_dmach_q;
1559
1560         if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
1561                 printk(KERN_ERR "Chain is already started\n");
1562                 return -EBUSY;
1563         }
1564
1565         if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
1566                 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
1567                                                                         i++) {
1568                         enable_lnk(channels[i]);
1569                         omap_enable_channel_irq(channels[i]);
1570                 }
1571         } else {
1572                 omap_enable_channel_irq(channels[0]);
1573         }
1574
1575         l = dma_read(CCR(channels[0]));
1576         l |= (1 << 7);
1577         dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
1578         dma_chan[channels[0]].state = DMA_CH_STARTED;
1579
1580         if ((0 == (l & (1 << 24))))
1581                 l &= ~(1 << 25);
1582         else
1583                 l |= (1 << 25);
1584         dma_write(l, CCR(channels[0]));
1585
1586         dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
1587
1588         return 0;
1589 }
1590 EXPORT_SYMBOL(omap_start_dma_chain_transfers);
1591
1592 /**
1593  * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1594  *
1595  * @param chain_id
1596  *
1597  * @return - Success : 0
1598  *           Failure : EINVAL
1599  */
1600 int omap_stop_dma_chain_transfers(int chain_id)
1601 {
1602         int *channels;
1603         u32 l, i;
1604         u32 sys_cf;
1605
1606         /* Check for input params */
1607         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1608                 printk(KERN_ERR "Invalid chain id\n");
1609                 return -EINVAL;
1610         }
1611
1612         /* Check if the chain exists */
1613         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1614                 printk(KERN_ERR "Chain doesn't exists\n");
1615                 return -EINVAL;
1616         }
1617         channels = dma_linked_lch[chain_id].linked_dmach_q;
1618
1619         /*
1620          * DMA Errata:
1621          * Special programming model needed to disable DMA before end of block
1622          */
1623         sys_cf = dma_read(OCP_SYSCONFIG);
1624         l = sys_cf;
1625         /* Middle mode reg set no Standby */
1626         l &= ~((1 << 12)|(1 << 13));
1627         dma_write(l, OCP_SYSCONFIG);
1628
1629         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1630
1631                 /* Stop the Channel transmission */
1632                 l = dma_read(CCR(channels[i]));
1633                 l &= ~(1 << 7);
1634                 dma_write(l, CCR(channels[i]));
1635
1636                 /* Disable the link in all the channels */
1637                 disable_lnk(channels[i]);
1638                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1639
1640         }
1641         dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1642
1643         /* Reset the Queue pointers */
1644         OMAP_DMA_CHAIN_QINIT(chain_id);
1645
1646         /* Errata - put in the old value */
1647         dma_write(sys_cf, OCP_SYSCONFIG);
1648
1649         return 0;
1650 }
1651 EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
1652
1653 /* Get the index of the ongoing DMA in chain */
1654 /**
1655  * @brief omap_get_dma_chain_index - Get the element and frame index
1656  * of the ongoing DMA in chain
1657  *
1658  * @param chain_id
1659  * @param ei - Element index
1660  * @param fi - Frame index
1661  *
1662  * @return - Success : 0
1663  *           Failure : -EINVAL
1664  */
1665 int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1666 {
1667         int lch;
1668         int *channels;
1669
1670         /* Check for input params */
1671         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1672                 printk(KERN_ERR "Invalid chain id\n");
1673                 return -EINVAL;
1674         }
1675
1676         /* Check if the chain exists */
1677         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1678                 printk(KERN_ERR "Chain doesn't exists\n");
1679                 return -EINVAL;
1680         }
1681         if ((!ei) || (!fi))
1682                 return -EINVAL;
1683
1684         channels = dma_linked_lch[chain_id].linked_dmach_q;
1685
1686         /* Get the current channel */
1687         lch = channels[dma_linked_lch[chain_id].q_head];
1688
1689         *ei = dma_read(CCEN(lch));
1690         *fi = dma_read(CCFN(lch));
1691
1692         return 0;
1693 }
1694 EXPORT_SYMBOL(omap_get_dma_chain_index);
1695
1696 /**
1697  * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1698  * ongoing DMA in chain
1699  *
1700  * @param chain_id
1701  *
1702  * @return - Success : Destination position
1703  *           Failure : -EINVAL
1704  */
1705 int omap_get_dma_chain_dst_pos(int chain_id)
1706 {
1707         int lch;
1708         int *channels;
1709
1710         /* Check for input params */
1711         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1712                 printk(KERN_ERR "Invalid chain id\n");
1713                 return -EINVAL;
1714         }
1715
1716         /* Check if the chain exists */
1717         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1718                 printk(KERN_ERR "Chain doesn't exists\n");
1719                 return -EINVAL;
1720         }
1721
1722         channels = dma_linked_lch[chain_id].linked_dmach_q;
1723
1724         /* Get the current channel */
1725         lch = channels[dma_linked_lch[chain_id].q_head];
1726
1727         return dma_read(CDAC(lch));
1728 }
1729 EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
1730
1731 /**
1732  * @brief omap_get_dma_chain_src_pos - Get the source position
1733  * of the ongoing DMA in chain
1734  * @param chain_id
1735  *
1736  * @return - Success : Destination position
1737  *           Failure : -EINVAL
1738  */
1739 int omap_get_dma_chain_src_pos(int chain_id)
1740 {
1741         int lch;
1742         int *channels;
1743
1744         /* Check for input params */
1745         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1746                 printk(KERN_ERR "Invalid chain id\n");
1747                 return -EINVAL;
1748         }
1749
1750         /* Check if the chain exists */
1751         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1752                 printk(KERN_ERR "Chain doesn't exists\n");
1753                 return -EINVAL;
1754         }
1755
1756         channels = dma_linked_lch[chain_id].linked_dmach_q;
1757
1758         /* Get the current channel */
1759         lch = channels[dma_linked_lch[chain_id].q_head];
1760
1761         return dma_read(CSAC(lch));
1762 }
1763 EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
1764 #endif  /* ifndef CONFIG_ARCH_OMAP1 */
1765
1766 /*----------------------------------------------------------------------------*/
1767
1768 #ifdef CONFIG_ARCH_OMAP1
1769
1770 static int omap1_dma_handle_ch(int ch)
1771 {
1772         u32 csr;
1773
1774         if (enable_1510_mode && ch >= 6) {
1775                 csr = dma_chan[ch].saved_csr;
1776                 dma_chan[ch].saved_csr = 0;
1777         } else
1778                 csr = dma_read(CSR(ch));
1779         if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1780                 dma_chan[ch + 6].saved_csr = csr >> 7;
1781                 csr &= 0x7f;
1782         }
1783         if ((csr & 0x3f) == 0)
1784                 return 0;
1785         if (unlikely(dma_chan[ch].dev_id == -1)) {
1786                 printk(KERN_WARNING "Spurious interrupt from DMA channel "
1787                        "%d (CSR %04x)\n", ch, csr);
1788                 return 0;
1789         }
1790         if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
1791                 printk(KERN_WARNING "DMA timeout with device %d\n",
1792                        dma_chan[ch].dev_id);
1793         if (unlikely(csr & OMAP_DMA_DROP_IRQ))
1794                 printk(KERN_WARNING "DMA synchronization event drop occurred "
1795                        "with device %d\n", dma_chan[ch].dev_id);
1796         if (likely(csr & OMAP_DMA_BLOCK_IRQ))
1797                 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1798         if (likely(dma_chan[ch].callback != NULL))
1799                 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
1800
1801         return 1;
1802 }
1803
1804 static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1805 {
1806         int ch = ((int) dev_id) - 1;
1807         int handled = 0;
1808
1809         for (;;) {
1810                 int handled_now = 0;
1811
1812                 handled_now += omap1_dma_handle_ch(ch);
1813                 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
1814                         handled_now += omap1_dma_handle_ch(ch + 6);
1815                 if (!handled_now)
1816                         break;
1817                 handled += handled_now;
1818         }
1819
1820         return handled ? IRQ_HANDLED : IRQ_NONE;
1821 }
1822
1823 #else
1824 #define omap1_dma_irq_handler   NULL
1825 #endif
1826
1827 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1828
1829 static int omap2_dma_handle_ch(int ch)
1830 {
1831         u32 status = dma_read(CSR(ch));
1832
1833         if (!status) {
1834                 if (printk_ratelimit())
1835                         printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
1836                                 ch);
1837                 dma_write(1 << ch, IRQSTATUS_L0);
1838                 return 0;
1839         }
1840         if (unlikely(dma_chan[ch].dev_id == -1)) {
1841                 if (printk_ratelimit())
1842                         printk(KERN_WARNING "IRQ %04x for non-allocated DMA"
1843                                         "channel %d\n", status, ch);
1844                 return 0;
1845         }
1846         if (unlikely(status & OMAP_DMA_DROP_IRQ))
1847                 printk(KERN_INFO
1848                        "DMA synchronization event drop occurred with device "
1849                        "%d\n", dma_chan[ch].dev_id);
1850         if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
1851                 printk(KERN_INFO "DMA transaction error with device %d\n",
1852                        dma_chan[ch].dev_id);
1853                 if (cpu_class_is_omap2()) {
1854                         /* Errata: sDMA Channel is not disabled
1855                          * after a transaction error. So we explicitely
1856                          * disable the channel
1857                          */
1858                         u32 ccr;
1859
1860                         ccr = dma_read(CCR(ch));
1861                         ccr &= ~OMAP_DMA_CCR_EN;
1862                         dma_write(ccr, CCR(ch));
1863                         dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1864                 }
1865         }
1866         if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
1867                 printk(KERN_INFO "DMA secure error with device %d\n",
1868                        dma_chan[ch].dev_id);
1869         if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
1870                 printk(KERN_INFO "DMA misaligned error with device %d\n",
1871                        dma_chan[ch].dev_id);
1872
1873         dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(ch));
1874         dma_write(1 << ch, IRQSTATUS_L0);
1875
1876         /* If the ch is not chained then chain_id will be -1 */
1877         if (dma_chan[ch].chain_id != -1) {
1878                 int chain_id = dma_chan[ch].chain_id;
1879                 dma_chan[ch].state = DMA_CH_NOTSTARTED;
1880                 if (dma_read(CLNK_CTRL(ch)) & (1 << 15))
1881                         dma_chan[dma_chan[ch].next_linked_ch].state =
1882                                                         DMA_CH_STARTED;
1883                 if (dma_linked_lch[chain_id].chain_mode ==
1884                                                 OMAP_DMA_DYNAMIC_CHAIN)
1885                         disable_lnk(ch);
1886
1887                 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1888                         OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1889
1890                 status = dma_read(CSR(ch));
1891         }
1892
1893         dma_write(status, CSR(ch));
1894
1895         if (likely(dma_chan[ch].callback != NULL))
1896                 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1897
1898         return 0;
1899 }
1900
1901 /* STATUS register count is from 1-32 while our is 0-31 */
1902 static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1903 {
1904         u32 val, enable_reg;
1905         int i;
1906
1907         val = dma_read(IRQSTATUS_L0);
1908         if (val == 0) {
1909                 if (printk_ratelimit())
1910                         printk(KERN_WARNING "Spurious DMA IRQ\n");
1911                 return IRQ_HANDLED;
1912         }
1913         enable_reg = dma_read(IRQENABLE_L0);
1914         val &= enable_reg; /* Dispatch only relevant interrupts */
1915         for (i = 0; i < dma_lch_count && val != 0; i++) {
1916                 if (val & 1)
1917                         omap2_dma_handle_ch(i);
1918                 val >>= 1;
1919         }
1920
1921         return IRQ_HANDLED;
1922 }
1923
1924 static struct irqaction omap24xx_dma_irq = {
1925         .name = "DMA",
1926         .handler = omap2_dma_irq_handler,
1927         .flags = IRQF_DISABLED
1928 };
1929
1930 #else
1931 static struct irqaction omap24xx_dma_irq;
1932 #endif
1933
1934 /*----------------------------------------------------------------------------*/
1935
1936 static struct lcd_dma_info {
1937         spinlock_t lock;
1938         int reserved;
1939         void (*callback)(u16 status, void *data);
1940         void *cb_data;
1941
1942         int active;
1943         unsigned long addr, size;
1944         int rotate, data_type, xres, yres;
1945         int vxres;
1946         int mirror;
1947         int xscale, yscale;
1948         int ext_ctrl;
1949         int src_port;
1950         int single_transfer;
1951 } lcd_dma;
1952
1953 void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
1954                          int data_type)
1955 {
1956         lcd_dma.addr = addr;
1957         lcd_dma.data_type = data_type;
1958         lcd_dma.xres = fb_xres;
1959         lcd_dma.yres = fb_yres;
1960 }
1961 EXPORT_SYMBOL(omap_set_lcd_dma_b1);
1962
1963 void omap_set_lcd_dma_src_port(int port)
1964 {
1965         lcd_dma.src_port = port;
1966 }
1967
1968 void omap_set_lcd_dma_ext_controller(int external)
1969 {
1970         lcd_dma.ext_ctrl = external;
1971 }
1972 EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
1973
1974 void omap_set_lcd_dma_single_transfer(int single)
1975 {
1976         lcd_dma.single_transfer = single;
1977 }
1978 EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
1979
1980 void omap_set_lcd_dma_b1_rotation(int rotate)
1981 {
1982         if (omap_dma_in_1510_mode()) {
1983                 printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n");
1984                 BUG();
1985                 return;
1986         }
1987         lcd_dma.rotate = rotate;
1988 }
1989 EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
1990
1991 void omap_set_lcd_dma_b1_mirror(int mirror)
1992 {
1993         if (omap_dma_in_1510_mode()) {
1994                 printk(KERN_ERR "DMA mirror is not supported in 1510 mode\n");
1995                 BUG();
1996         }
1997         lcd_dma.mirror = mirror;
1998 }
1999 EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
2000
2001 void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
2002 {
2003         if (omap_dma_in_1510_mode()) {
2004                 printk(KERN_ERR "DMA virtual resulotion is not supported "
2005                                 "in 1510 mode\n");
2006                 BUG();
2007         }
2008         lcd_dma.vxres = vxres;
2009 }
2010 EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
2011
2012 void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
2013 {
2014         if (omap_dma_in_1510_mode()) {
2015                 printk(KERN_ERR "DMA scale is not supported in 1510 mode\n");
2016                 BUG();
2017         }
2018         lcd_dma.xscale = xscale;
2019         lcd_dma.yscale = yscale;
2020 }
2021 EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
2022
2023 static void set_b1_regs(void)
2024 {
2025         unsigned long top, bottom;
2026         int es;
2027         u16 w;
2028         unsigned long en, fn;
2029         long ei, fi;
2030         unsigned long vxres;
2031         unsigned int xscale, yscale;
2032
2033         switch (lcd_dma.data_type) {
2034         case OMAP_DMA_DATA_TYPE_S8:
2035                 es = 1;
2036                 break;
2037         case OMAP_DMA_DATA_TYPE_S16:
2038                 es = 2;
2039                 break;
2040         case OMAP_DMA_DATA_TYPE_S32:
2041                 es = 4;
2042                 break;
2043         default:
2044                 BUG();
2045                 return;
2046         }
2047
2048         vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres;
2049         xscale = lcd_dma.xscale ? lcd_dma.xscale : 1;
2050         yscale = lcd_dma.yscale ? lcd_dma.yscale : 1;
2051         BUG_ON(vxres < lcd_dma.xres);
2052
2053 #define PIXADDR(x, y) (lcd_dma.addr +                                   \
2054                 ((y) * vxres * yscale + (x) * xscale) * es)
2055 #define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
2056
2057         switch (lcd_dma.rotate) {
2058         case 0:
2059                 if (!lcd_dma.mirror) {
2060                         top = PIXADDR(0, 0);
2061                         bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2062                         /* 1510 DMA requires the bottom address to be 2 more
2063                          * than the actual last memory access location. */
2064                         if (omap_dma_in_1510_mode() &&
2065                                 lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
2066                                         bottom += 2;
2067                         ei = PIXSTEP(0, 0, 1, 0);
2068                         fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1);
2069                 } else {
2070                         top = PIXADDR(lcd_dma.xres - 1, 0);
2071                         bottom = PIXADDR(0, lcd_dma.yres - 1);
2072                         ei = PIXSTEP(1, 0, 0, 0);
2073                         fi = PIXSTEP(0, 0, lcd_dma.xres - 1, 1);
2074                 }
2075                 en = lcd_dma.xres;
2076                 fn = lcd_dma.yres;
2077                 break;
2078         case 90:
2079                 if (!lcd_dma.mirror) {
2080                         top = PIXADDR(0, lcd_dma.yres - 1);
2081                         bottom = PIXADDR(lcd_dma.xres - 1, 0);
2082                         ei = PIXSTEP(0, 1, 0, 0);
2083                         fi = PIXSTEP(0, 0, 1, lcd_dma.yres - 1);
2084                 } else {
2085                         top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2086                         bottom = PIXADDR(0, 0);
2087                         ei = PIXSTEP(0, 1, 0, 0);
2088                         fi = PIXSTEP(1, 0, 0, lcd_dma.yres - 1);
2089                 }
2090                 en = lcd_dma.yres;
2091                 fn = lcd_dma.xres;
2092                 break;
2093         case 180:
2094                 if (!lcd_dma.mirror) {
2095                         top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2096                         bottom = PIXADDR(0, 0);
2097                         ei = PIXSTEP(1, 0, 0, 0);
2098                         fi = PIXSTEP(0, 1, lcd_dma.xres - 1, 0);
2099                 } else {
2100                         top = PIXADDR(0, lcd_dma.yres - 1);
2101                         bottom = PIXADDR(lcd_dma.xres - 1, 0);
2102                         ei = PIXSTEP(0, 0, 1, 0);
2103                         fi = PIXSTEP(lcd_dma.xres - 1, 1, 0, 0);
2104                 }
2105                 en = lcd_dma.xres;
2106                 fn = lcd_dma.yres;
2107                 break;
2108         case 270:
2109                 if (!lcd_dma.mirror) {
2110                         top = PIXADDR(lcd_dma.xres - 1, 0);
2111                         bottom = PIXADDR(0, lcd_dma.yres - 1);
2112                         ei = PIXSTEP(0, 0, 0, 1);
2113                         fi = PIXSTEP(1, lcd_dma.yres - 1, 0, 0);
2114                 } else {
2115                         top = PIXADDR(0, 0);
2116                         bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2117                         ei = PIXSTEP(0, 0, 0, 1);
2118                         fi = PIXSTEP(0, lcd_dma.yres - 1, 1, 0);
2119                 }
2120                 en = lcd_dma.yres;
2121                 fn = lcd_dma.xres;
2122                 break;
2123         default:
2124                 BUG();
2125                 return; /* Suppress warning about uninitialized vars */
2126         }
2127
2128         if (omap_dma_in_1510_mode()) {
2129                 omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U);
2130                 omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L);
2131                 omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U);
2132                 omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L);
2133
2134                 return;
2135         }
2136
2137         /* 1610 regs */
2138         omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U);
2139         omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L);
2140         omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U);
2141         omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L);
2142
2143         omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1);
2144         omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1);
2145
2146         w = omap_readw(OMAP1610_DMA_LCD_CSDP);
2147         w &= ~0x03;
2148         w |= lcd_dma.data_type;
2149         omap_writew(w, OMAP1610_DMA_LCD_CSDP);
2150
2151         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2152         /* Always set the source port as SDRAM for now*/
2153         w &= ~(0x03 << 6);
2154         if (lcd_dma.callback != NULL)
2155                 w |= 1 << 1;            /* Block interrupt enable */
2156         else
2157                 w &= ~(1 << 1);
2158         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2159
2160         if (!(lcd_dma.rotate || lcd_dma.mirror ||
2161               lcd_dma.vxres || lcd_dma.xscale || lcd_dma.yscale))
2162                 return;
2163
2164         w = omap_readw(OMAP1610_DMA_LCD_CCR);
2165         /* Set the double-indexed addressing mode */
2166         w |= (0x03 << 12);
2167         omap_writew(w, OMAP1610_DMA_LCD_CCR);
2168
2169         omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1);
2170         omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U);
2171         omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
2172 }
2173
2174 static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id)
2175 {
2176         u16 w;
2177
2178         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2179         if (unlikely(!(w & (1 << 3)))) {
2180                 printk(KERN_WARNING "Spurious LCD DMA IRQ\n");
2181                 return IRQ_NONE;
2182         }
2183         /* Ack the IRQ */
2184         w |= (1 << 3);
2185         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2186         lcd_dma.active = 0;
2187         if (lcd_dma.callback != NULL)
2188                 lcd_dma.callback(w, lcd_dma.cb_data);
2189
2190         return IRQ_HANDLED;
2191 }
2192
2193 int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
2194                          void *data)
2195 {
2196         spin_lock_irq(&lcd_dma.lock);
2197         if (lcd_dma.reserved) {
2198                 spin_unlock_irq(&lcd_dma.lock);
2199                 printk(KERN_ERR "LCD DMA channel already reserved\n");
2200                 BUG();
2201                 return -EBUSY;
2202         }
2203         lcd_dma.reserved = 1;
2204         spin_unlock_irq(&lcd_dma.lock);
2205         lcd_dma.callback = callback;
2206         lcd_dma.cb_data = data;
2207         lcd_dma.active = 0;
2208         lcd_dma.single_transfer = 0;
2209         lcd_dma.rotate = 0;
2210         lcd_dma.vxres = 0;
2211         lcd_dma.mirror = 0;
2212         lcd_dma.xscale = 0;
2213         lcd_dma.yscale = 0;
2214         lcd_dma.ext_ctrl = 0;
2215         lcd_dma.src_port = 0;
2216
2217         return 0;
2218 }
2219 EXPORT_SYMBOL(omap_request_lcd_dma);
2220
2221 void omap_free_lcd_dma(void)
2222 {
2223         spin_lock(&lcd_dma.lock);
2224         if (!lcd_dma.reserved) {
2225                 spin_unlock(&lcd_dma.lock);
2226                 printk(KERN_ERR "LCD DMA is not reserved\n");
2227                 BUG();
2228                 return;
2229         }
2230         if (!enable_1510_mode)
2231                 omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1,
2232                             OMAP1610_DMA_LCD_CCR);
2233         lcd_dma.reserved = 0;
2234         spin_unlock(&lcd_dma.lock);
2235 }
2236 EXPORT_SYMBOL(omap_free_lcd_dma);
2237
2238 void omap_enable_lcd_dma(void)
2239 {
2240         u16 w;
2241
2242         /*
2243          * Set the Enable bit only if an external controller is
2244          * connected. Otherwise the OMAP internal controller will
2245          * start the transfer when it gets enabled.
2246          */
2247         if (enable_1510_mode || !lcd_dma.ext_ctrl)
2248                 return;
2249
2250         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2251         w |= 1 << 8;
2252         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2253
2254         lcd_dma.active = 1;
2255
2256         w = omap_readw(OMAP1610_DMA_LCD_CCR);
2257         w |= 1 << 7;
2258         omap_writew(w, OMAP1610_DMA_LCD_CCR);
2259 }
2260 EXPORT_SYMBOL(omap_enable_lcd_dma);
2261
2262 void omap_setup_lcd_dma(void)
2263 {
2264         BUG_ON(lcd_dma.active);
2265         if (!enable_1510_mode) {
2266                 /* Set some reasonable defaults */
2267                 omap_writew(0x5440, OMAP1610_DMA_LCD_CCR);
2268                 omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP);
2269                 omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL);
2270         }
2271         set_b1_regs();
2272         if (!enable_1510_mode) {
2273                 u16 w;
2274
2275                 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2276                 /*
2277                  * If DMA was already active set the end_prog bit to have
2278                  * the programmed register set loaded into the active
2279                  * register set.
2280                  */
2281                 w |= 1 << 11;           /* End_prog */
2282                 if (!lcd_dma.single_transfer)
2283                         w |= (3 << 8);  /* Auto_init, repeat */
2284                 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2285         }
2286 }
2287 EXPORT_SYMBOL(omap_setup_lcd_dma);
2288
2289 void omap_stop_lcd_dma(void)
2290 {
2291         u16 w;
2292
2293         lcd_dma.active = 0;
2294         if (enable_1510_mode || !lcd_dma.ext_ctrl)
2295                 return;
2296
2297         w = omap_readw(OMAP1610_DMA_LCD_CCR);
2298         w &= ~(1 << 7);
2299         omap_writew(w, OMAP1610_DMA_LCD_CCR);
2300
2301         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2302         w &= ~(1 << 8);
2303         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2304 }
2305 EXPORT_SYMBOL(omap_stop_lcd_dma);
2306
2307 /*----------------------------------------------------------------------------*/
2308
2309 static int __init omap_init_dma(void)
2310 {
2311         int ch, r;
2312
2313         if (cpu_class_is_omap1()) {
2314                 omap_dma_base = IO_ADDRESS(OMAP1_DMA_BASE);
2315                 dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
2316         } else if (cpu_is_omap24xx()) {
2317                 omap_dma_base = IO_ADDRESS(OMAP24XX_DMA4_BASE);
2318                 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2319         } else if (cpu_is_omap34xx()) {
2320                 omap_dma_base = IO_ADDRESS(OMAP34XX_DMA4_BASE);
2321                 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2322         } else {
2323                 pr_err("DMA init failed for unsupported omap\n");
2324                 return -ENODEV;
2325         }
2326
2327         if (cpu_class_is_omap2() && omap_dma_reserve_channels
2328                         && (omap_dma_reserve_channels <= dma_lch_count))
2329                 dma_lch_count = omap_dma_reserve_channels;
2330
2331         dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count,
2332                                 GFP_KERNEL);
2333         if (!dma_chan)
2334                 return -ENOMEM;
2335
2336         if (cpu_class_is_omap2()) {
2337                 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
2338                                                 dma_lch_count, GFP_KERNEL);
2339                 if (!dma_linked_lch) {
2340                         kfree(dma_chan);
2341                         return -ENOMEM;
2342                 }
2343         }
2344
2345         if (cpu_is_omap15xx()) {
2346                 printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
2347                 dma_chan_count = 9;
2348                 enable_1510_mode = 1;
2349         } else if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
2350                 printk(KERN_INFO "OMAP DMA hardware version %d\n",
2351                        dma_read(HW_ID));
2352                 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
2353                        (dma_read(CAPS_0_U) << 16) |
2354                        dma_read(CAPS_0_L),
2355                        (dma_read(CAPS_1_U) << 16) |
2356                        dma_read(CAPS_1_L),
2357                        dma_read(CAPS_2), dma_read(CAPS_3),
2358                        dma_read(CAPS_4));
2359                 if (!enable_1510_mode) {
2360                         u16 w;
2361
2362                         /* Disable OMAP 3.0/3.1 compatibility mode. */
2363                         w = dma_read(GSCR);
2364                         w |= 1 << 3;
2365                         dma_write(w, GSCR);
2366                         dma_chan_count = 16;
2367                 } else
2368                         dma_chan_count = 9;
2369                 if (cpu_is_omap16xx()) {
2370                         u16 w;
2371
2372                         /* this would prevent OMAP sleep */
2373                         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2374                         w &= ~(1 << 8);
2375                         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2376                 }
2377         } else if (cpu_class_is_omap2()) {
2378                 u8 revision = dma_read(REVISION) & 0xff;
2379                 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
2380                        revision >> 4, revision & 0xf);
2381                 dma_chan_count = dma_lch_count;
2382         } else {
2383                 dma_chan_count = 0;
2384                 return 0;
2385         }
2386
2387         spin_lock_init(&lcd_dma.lock);
2388         spin_lock_init(&dma_chan_lock);
2389
2390         for (ch = 0; ch < dma_chan_count; ch++) {
2391                 omap_clear_dma(ch);
2392                 dma_chan[ch].dev_id = -1;
2393                 dma_chan[ch].next_lch = -1;
2394
2395                 if (ch >= 6 && enable_1510_mode)
2396                         continue;
2397
2398                 if (cpu_class_is_omap1()) {
2399                         /*
2400                          * request_irq() doesn't like dev_id (ie. ch) being
2401                          * zero, so we have to kludge around this.
2402                          */
2403                         r = request_irq(omap1_dma_irq[ch],
2404                                         omap1_dma_irq_handler, 0, "DMA",
2405                                         (void *) (ch + 1));
2406                         if (r != 0) {
2407                                 int i;
2408
2409                                 printk(KERN_ERR "unable to request IRQ %d "
2410                                        "for DMA (error %d)\n",
2411                                        omap1_dma_irq[ch], r);
2412                                 for (i = 0; i < ch; i++)
2413                                         free_irq(omap1_dma_irq[i],
2414                                                  (void *) (i + 1));
2415                                 return r;
2416                         }
2417                 }
2418         }
2419
2420         if (cpu_is_omap2430() || cpu_is_omap34xx())
2421                 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
2422                                 DMA_DEFAULT_FIFO_DEPTH, 0);
2423
2424         if (cpu_class_is_omap2())
2425                 setup_irq(INT_24XX_SDMA_IRQ0, &omap24xx_dma_irq);
2426
2427         /* FIXME: Update LCD DMA to work on 24xx */
2428         if (cpu_class_is_omap1()) {
2429                 r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
2430                                 "LCD DMA", NULL);
2431                 if (r != 0) {
2432                         int i;
2433
2434                         printk(KERN_ERR "unable to request IRQ for LCD DMA "
2435                                "(error %d)\n", r);
2436                         for (i = 0; i < dma_chan_count; i++)
2437                                 free_irq(omap1_dma_irq[i], (void *) (i + 1));
2438                         return r;
2439                 }
2440         }
2441
2442         return 0;
2443 }
2444
2445 arch_initcall(omap_init_dma);
2446
2447 /*
2448  * Reserve the omap SDMA channels using cmdline bootarg
2449  * "omap_dma_reserve_ch=". The valid range is 1 to 32
2450  */
2451 static int __init omap_dma_cmdline_reserve_ch(char *str)
2452 {
2453         if (get_option(&str, &omap_dma_reserve_channels) != 1)
2454                 omap_dma_reserve_channels = 0;
2455         return 1;
2456 }
2457
2458 __setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch);
2459
2460