2 * linux/arch/arm/mm/mmu.c
4 * Copyright (C) 1995-2005 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #include <linux/module.h>
11 #include <linux/kernel.h>
12 #include <linux/errno.h>
13 #include <linux/init.h>
14 #include <linux/mman.h>
15 #include <linux/nodemask.h>
16 #include <linux/memblock.h>
18 #include <linux/vmalloc.h>
20 #include <asm/cputype.h>
21 #include <asm/sections.h>
22 #include <asm/cachetype.h>
23 #include <asm/setup.h>
24 #include <asm/sizes.h>
25 #include <asm/smp_plat.h>
27 #include <asm/highmem.h>
28 #include <asm/traps.h>
30 #include <asm/mach/arch.h>
31 #include <asm/mach/map.h>
36 * empty_zero_page is a special page that is used for
37 * zero-initialized data and COW.
39 struct page *empty_zero_page;
40 EXPORT_SYMBOL(empty_zero_page);
43 * The pmd table for the upper-most set of pages.
47 #define CPOLICY_UNCACHED 0
48 #define CPOLICY_BUFFERED 1
49 #define CPOLICY_WRITETHROUGH 2
50 #define CPOLICY_WRITEBACK 3
51 #define CPOLICY_WRITEALLOC 4
53 static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
54 static unsigned int ecc_mask __initdata = 0;
56 pgprot_t pgprot_kernel;
58 EXPORT_SYMBOL(pgprot_user);
59 EXPORT_SYMBOL(pgprot_kernel);
62 const char policy[16];
68 static struct cachepolicy cache_policies[] __initdata = {
72 .pmd = PMD_SECT_UNCACHED,
73 .pte = L_PTE_MT_UNCACHED,
77 .pmd = PMD_SECT_BUFFERED,
78 .pte = L_PTE_MT_BUFFERABLE,
80 .policy = "writethrough",
83 .pte = L_PTE_MT_WRITETHROUGH,
85 .policy = "writeback",
88 .pte = L_PTE_MT_WRITEBACK,
90 .policy = "writealloc",
93 .pte = L_PTE_MT_WRITEALLOC,
98 * These are useful for identifying cache coherency
99 * problems by allowing the cache or the cache and
100 * writebuffer to be turned off. (Note: the write
101 * buffer should not be on and the cache off).
103 static int __init early_cachepolicy(char *p)
107 for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
108 int len = strlen(cache_policies[i].policy);
110 if (memcmp(p, cache_policies[i].policy, len) == 0) {
112 cr_alignment &= ~cache_policies[i].cr_mask;
113 cr_no_alignment &= ~cache_policies[i].cr_mask;
117 if (i == ARRAY_SIZE(cache_policies))
118 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
120 * This restriction is partly to do with the way we boot; it is
121 * unpredictable to have memory mapped using two different sets of
122 * memory attributes (shared, type, and cache attribs). We can not
123 * change these attributes once the initial assembly has setup the
126 if (cpu_architecture() >= CPU_ARCH_ARMv6) {
127 printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
128 cachepolicy = CPOLICY_WRITEBACK;
131 set_cr(cr_alignment);
134 early_param("cachepolicy", early_cachepolicy);
136 static int __init early_nocache(char *__unused)
138 char *p = "buffered";
139 printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
140 early_cachepolicy(p);
143 early_param("nocache", early_nocache);
145 static int __init early_nowrite(char *__unused)
147 char *p = "uncached";
148 printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
149 early_cachepolicy(p);
152 early_param("nowb", early_nowrite);
154 #ifndef CONFIG_ARM_LPAE
155 static int __init early_ecc(char *p)
157 if (memcmp(p, "on", 2) == 0)
158 ecc_mask = PMD_PROTECTION;
159 else if (memcmp(p, "off", 3) == 0)
163 early_param("ecc", early_ecc);
166 static int __init noalign_setup(char *__unused)
168 cr_alignment &= ~CR_A;
169 cr_no_alignment &= ~CR_A;
170 set_cr(cr_alignment);
173 __setup("noalign", noalign_setup);
176 void adjust_cr(unsigned long mask, unsigned long set)
184 local_irq_save(flags);
186 cr_no_alignment = (cr_no_alignment & ~mask) | set;
187 cr_alignment = (cr_alignment & ~mask) | set;
189 set_cr((get_cr() & ~mask) | set);
191 local_irq_restore(flags);
195 #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
196 #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE
198 static struct mem_type mem_types[] = {
199 [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */
200 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
202 .prot_l1 = PMD_TYPE_TABLE,
203 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S,
206 [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
207 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
208 .prot_l1 = PMD_TYPE_TABLE,
209 .prot_sect = PROT_SECT_DEVICE,
212 [MT_DEVICE_CACHED] = { /* ioremap_cached */
213 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
214 .prot_l1 = PMD_TYPE_TABLE,
215 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB,
218 [MT_DEVICE_WC] = { /* ioremap_wc */
219 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
220 .prot_l1 = PMD_TYPE_TABLE,
221 .prot_sect = PROT_SECT_DEVICE,
225 .prot_pte = PROT_PTE_DEVICE,
226 .prot_l1 = PMD_TYPE_TABLE,
227 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
231 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
232 .domain = DOMAIN_KERNEL,
234 #ifndef CONFIG_ARM_LPAE
236 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
237 .domain = DOMAIN_KERNEL,
241 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
243 .prot_l1 = PMD_TYPE_TABLE,
244 .domain = DOMAIN_USER,
246 [MT_HIGH_VECTORS] = {
247 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
248 L_PTE_USER | L_PTE_RDONLY,
249 .prot_l1 = PMD_TYPE_TABLE,
250 .domain = DOMAIN_USER,
253 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
254 .prot_l1 = PMD_TYPE_TABLE,
255 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
256 .domain = DOMAIN_KERNEL,
259 .prot_sect = PMD_TYPE_SECT,
260 .domain = DOMAIN_KERNEL,
262 [MT_MEMORY_NONCACHED] = {
263 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
265 .prot_l1 = PMD_TYPE_TABLE,
266 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
267 .domain = DOMAIN_KERNEL,
270 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
272 .prot_l1 = PMD_TYPE_TABLE,
273 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
274 .domain = DOMAIN_KERNEL,
277 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
278 .prot_l1 = PMD_TYPE_TABLE,
279 .domain = DOMAIN_KERNEL,
282 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
284 .prot_l1 = PMD_TYPE_TABLE,
285 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S |
286 PMD_SECT_UNCACHED | PMD_SECT_XN,
287 .domain = DOMAIN_KERNEL,
289 [MT_MEMORY_DMA_READY] = {
290 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
291 .prot_l1 = PMD_TYPE_TABLE,
292 .domain = DOMAIN_KERNEL,
296 const struct mem_type *get_mem_type(unsigned int type)
298 return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
300 EXPORT_SYMBOL(get_mem_type);
303 * If the system supports huge pages and we are running with short descriptors,
304 * then compute the pmd and linux pte prot values for a huge page.
306 * These values are used by both the HugeTLB and THP code.
308 #if defined(CONFIG_SYS_SUPPORTS_HUGETLBFS) && !defined(CONFIG_ARM_LPAE)
309 pmdval_t arm_hugepmdprotval;
310 EXPORT_SYMBOL(arm_hugepmdprotval);
312 pteval_t arm_hugepteprotval;
313 EXPORT_SYMBOL(arm_hugepteprotval);
318 * Adjust the PMD section entries according to the CPU in use.
320 static void __init build_mem_type_table(void)
322 struct cachepolicy *cp;
323 unsigned int cr = get_cr();
324 pteval_t user_pgprot, kern_pgprot, vecs_pgprot;
325 int cpu_arch = cpu_architecture();
328 if (cpu_arch < CPU_ARCH_ARMv6) {
329 #if defined(CONFIG_CPU_DCACHE_DISABLE)
330 if (cachepolicy > CPOLICY_BUFFERED)
331 cachepolicy = CPOLICY_BUFFERED;
332 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
333 if (cachepolicy > CPOLICY_WRITETHROUGH)
334 cachepolicy = CPOLICY_WRITETHROUGH;
337 if (cpu_arch < CPU_ARCH_ARMv5) {
338 if (cachepolicy >= CPOLICY_WRITEALLOC)
339 cachepolicy = CPOLICY_WRITEBACK;
343 cachepolicy = CPOLICY_WRITEALLOC;
346 * Strip out features not present on earlier architectures.
347 * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those
348 * without extended page tables don't have the 'Shared' bit.
350 if (cpu_arch < CPU_ARCH_ARMv5)
351 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
352 mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
353 if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
354 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
355 mem_types[i].prot_sect &= ~PMD_SECT_S;
358 * ARMv5 and lower, bit 4 must be set for page tables (was: cache
359 * "update-able on write" bit on ARM610). However, Xscale and
360 * Xscale3 require this bit to be cleared.
362 if (cpu_is_xscale() || cpu_is_xsc3()) {
363 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
364 mem_types[i].prot_sect &= ~PMD_BIT4;
365 mem_types[i].prot_l1 &= ~PMD_BIT4;
367 } else if (cpu_arch < CPU_ARCH_ARMv6) {
368 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
369 if (mem_types[i].prot_l1)
370 mem_types[i].prot_l1 |= PMD_BIT4;
371 if (mem_types[i].prot_sect)
372 mem_types[i].prot_sect |= PMD_BIT4;
377 * Mark the device areas according to the CPU/architecture.
379 if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
380 if (!cpu_is_xsc3()) {
382 * Mark device regions on ARMv6+ as execute-never
383 * to prevent speculative instruction fetches.
385 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
386 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
387 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
388 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
390 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
392 * For ARMv7 with TEX remapping,
393 * - shared device is SXCB=1100
394 * - nonshared device is SXCB=0100
395 * - write combine device mem is SXCB=0001
396 * (Uncached Normal memory)
398 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
399 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
400 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
401 } else if (cpu_is_xsc3()) {
404 * - shared device is TEXCB=00101
405 * - nonshared device is TEXCB=01000
406 * - write combine device mem is TEXCB=00100
407 * (Inner/Outer Uncacheable in xsc3 parlance)
409 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
410 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
411 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
414 * For ARMv6 and ARMv7 without TEX remapping,
415 * - shared device is TEXCB=00001
416 * - nonshared device is TEXCB=01000
417 * - write combine device mem is TEXCB=00100
418 * (Uncached Normal in ARMv6 parlance).
420 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
421 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
422 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
426 * On others, write combining is "Uncached/Buffered"
428 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
432 * Now deal with the memory-type mappings
434 cp = &cache_policies[cachepolicy];
435 vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
438 * Only use write-through for non-SMP systems
440 if (!is_smp() && cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH)
441 vecs_pgprot = cache_policies[CPOLICY_WRITETHROUGH].pte;
444 * Enable CPU-specific coherency if supported.
445 * (Only available on XSC3 at the moment.)
447 if (arch_is_coherent() && cpu_is_xsc3()) {
448 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
449 mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
450 mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED;
451 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
452 mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
455 * ARMv6 and above have extended page tables.
457 if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
458 #ifndef CONFIG_ARM_LPAE
460 * Mark cache clean areas and XIP ROM read only
461 * from SVC mode and no access from userspace.
463 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
464 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
465 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
470 * Mark memory with the "shared" attribute
473 user_pgprot |= L_PTE_SHARED;
474 kern_pgprot |= L_PTE_SHARED;
475 vecs_pgprot |= L_PTE_SHARED;
476 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
477 mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
478 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
479 mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
480 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
481 mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
482 mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED;
483 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
484 mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
489 * Non-cacheable Normal - intended for memory areas that must
490 * not cause dirty cache line writebacks when used
492 if (cpu_arch >= CPU_ARCH_ARMv6) {
493 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
494 /* Non-cacheable Normal is XCB = 001 */
495 mem_types[MT_MEMORY_NONCACHED].prot_sect |=
498 /* For both ARMv6 and non-TEX-remapping ARMv7 */
499 mem_types[MT_MEMORY_NONCACHED].prot_sect |=
503 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
506 #ifdef CONFIG_ARM_LPAE
508 * Do not generate access flag faults for the kernel mappings.
510 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
511 mem_types[i].prot_pte |= PTE_EXT_AF;
512 mem_types[i].prot_sect |= PMD_SECT_AF;
514 kern_pgprot |= PTE_EXT_AF;
515 vecs_pgprot |= PTE_EXT_AF;
518 for (i = 0; i < 16; i++) {
519 pteval_t v = pgprot_val(protection_map[i]);
520 protection_map[i] = __pgprot(v | user_pgprot);
523 mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
524 mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
526 pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
527 pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
528 L_PTE_DIRTY | kern_pgprot);
530 mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
531 mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
532 mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
533 mem_types[MT_MEMORY].prot_pte |= kern_pgprot;
534 mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot;
535 mem_types[MT_MEMORY_NONCACHED].prot_sect |= ecc_mask;
536 mem_types[MT_ROM].prot_sect |= cp->pmd;
540 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
544 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
547 printk("Memory policy: ECC %sabled, Data cache %s\n",
548 ecc_mask ? "en" : "dis", cp->policy);
550 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
551 struct mem_type *t = &mem_types[i];
553 t->prot_l1 |= PMD_DOMAIN(t->domain);
555 t->prot_sect |= PMD_DOMAIN(t->domain);
558 #if defined(CONFIG_SYS_SUPPORTS_HUGETLBFS) && !defined(CONFIG_ARM_LPAE)
560 * we assume all huge pages are user pages and that hardware access
561 * flag updates are disabled (i.e. SCTLR.AFE == 0b).
563 arm_hugepteprotval = mem_types[MT_MEMORY].prot_pte | L_PTE_USER | L_PTE_VALID;
565 arm_hugepmdprotval = mem_types[MT_MEMORY].prot_sect | PMD_SECT_AP_READ
568 /* HACK: make huge pages WT
569 * XXX: mm will not know nothing about this..
570 * FIXME: should only do it on Cortex-A8 or below */
571 arm_hugepmdprotval &= ~(PMD_SECT_WB | PMD_SECT_TEX(1));
572 arm_hugepmdprotval |= PMD_SECT_WT;
577 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
578 pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
579 unsigned long size, pgprot_t vma_prot)
582 return pgprot_noncached(vma_prot);
583 else if (file->f_flags & O_SYNC)
584 return pgprot_writecombine(vma_prot);
587 EXPORT_SYMBOL(phys_mem_access_prot);
590 #define vectors_base() (vectors_high() ? 0xffff0000 : 0)
592 static void __init *early_alloc_aligned(unsigned long sz, unsigned long align)
594 void *ptr = __va(memblock_alloc(sz, align));
599 static void __init *early_alloc(unsigned long sz)
601 return early_alloc_aligned(sz, sz);
604 static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot)
606 if (pmd_none(*pmd)) {
607 pte_t *pte = early_alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE);
608 __pmd_populate(pmd, __pa(pte), prot);
610 BUG_ON(pmd_bad(*pmd));
611 return pte_offset_kernel(pmd, addr);
614 static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
615 unsigned long end, unsigned long pfn,
616 const struct mem_type *type)
618 pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1);
620 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0);
622 } while (pte++, addr += PAGE_SIZE, addr != end);
625 static void __init alloc_init_section(pud_t *pud, unsigned long addr,
626 unsigned long end, phys_addr_t phys,
627 const struct mem_type *type)
629 pmd_t *pmd = pmd_offset(pud, addr);
632 * Try a section mapping - end, addr and phys must all be aligned
633 * to a section boundary. Note that PMDs refer to the individual
634 * L1 entries, whereas PGDs refer to a group of L1 entries making
635 * up one logical pointer to an L2 table.
637 if (type->prot_sect && ((addr | end | phys) & ~SECTION_MASK) == 0) {
640 #ifndef CONFIG_ARM_LPAE
641 if (addr & SECTION_SIZE)
646 *pmd = __pmd(phys | type->prot_sect);
647 phys += SECTION_SIZE;
648 } while (pmd++, addr += SECTION_SIZE, addr != end);
653 * No need to loop; pte's aren't interested in the
654 * individual L1 entries.
656 alloc_init_pte(pmd, addr, end, __phys_to_pfn(phys), type);
660 static void alloc_init_pud(pgd_t *pgd, unsigned long addr, unsigned long end,
661 unsigned long phys, const struct mem_type *type)
663 pud_t *pud = pud_offset(pgd, addr);
667 next = pud_addr_end(addr, end);
668 alloc_init_section(pud, addr, next, phys, type);
670 } while (pud++, addr = next, addr != end);
673 #ifndef CONFIG_ARM_LPAE
674 static void __init create_36bit_mapping(struct map_desc *md,
675 const struct mem_type *type)
677 unsigned long addr, length, end;
682 phys = __pfn_to_phys(md->pfn);
683 length = PAGE_ALIGN(md->length);
685 if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
686 printk(KERN_ERR "MM: CPU does not support supersection "
687 "mapping for 0x%08llx at 0x%08lx\n",
688 (long long)__pfn_to_phys((u64)md->pfn), addr);
692 /* N.B. ARMv6 supersections are only defined to work with domain 0.
693 * Since domain assignments can in fact be arbitrary, the
694 * 'domain == 0' check below is required to insure that ARMv6
695 * supersections are only allocated for domain 0 regardless
696 * of the actual domain assignments in use.
699 printk(KERN_ERR "MM: invalid domain in supersection "
700 "mapping for 0x%08llx at 0x%08lx\n",
701 (long long)__pfn_to_phys((u64)md->pfn), addr);
705 if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
706 printk(KERN_ERR "MM: cannot create mapping for 0x%08llx"
707 " at 0x%08lx invalid alignment\n",
708 (long long)__pfn_to_phys((u64)md->pfn), addr);
713 * Shift bits [35:32] of address into bits [23:20] of PMD
716 phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
718 pgd = pgd_offset_k(addr);
721 pud_t *pud = pud_offset(pgd, addr);
722 pmd_t *pmd = pmd_offset(pud, addr);
725 for (i = 0; i < 16; i++)
726 *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER);
728 addr += SUPERSECTION_SIZE;
729 phys += SUPERSECTION_SIZE;
730 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
731 } while (addr != end);
733 #endif /* !CONFIG_ARM_LPAE */
736 * Create the page directory entries and any necessary
737 * page tables for the mapping specified by `md'. We
738 * are able to cope here with varying sizes and address
739 * offsets, and we take full advantage of sections and
742 static void __init create_mapping(struct map_desc *md)
744 unsigned long addr, length, end;
746 const struct mem_type *type;
749 if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
750 printk(KERN_WARNING "BUG: not creating mapping for 0x%08llx"
751 " at 0x%08lx in user region\n",
752 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
756 if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
757 md->virtual >= PAGE_OFFSET &&
758 (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) {
759 printk(KERN_WARNING "BUG: mapping for 0x%08llx"
760 " at 0x%08lx out of vmalloc space\n",
761 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
764 type = &mem_types[md->type];
766 #ifndef CONFIG_ARM_LPAE
768 * Catch 36-bit addresses
770 if (md->pfn >= 0x100000) {
771 create_36bit_mapping(md, type);
776 addr = md->virtual & PAGE_MASK;
777 phys = __pfn_to_phys(md->pfn);
778 length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
780 if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
781 printk(KERN_WARNING "BUG: map for 0x%08llx at 0x%08lx can not "
782 "be mapped using pages, ignoring.\n",
783 (long long)__pfn_to_phys(md->pfn), addr);
787 pgd = pgd_offset_k(addr);
790 unsigned long next = pgd_addr_end(addr, end);
792 alloc_init_pud(pgd, addr, next, phys, type);
796 } while (pgd++, addr != end);
800 * Create the architecture specific mappings
802 void __init iotable_init(struct map_desc *io_desc, int nr)
805 struct vm_struct *vm;
810 vm = early_alloc_aligned(sizeof(*vm) * nr, __alignof__(*vm));
812 for (md = io_desc; nr; md++, nr--) {
814 vm->addr = (void *)(md->virtual & PAGE_MASK);
815 vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
816 vm->phys_addr = __pfn_to_phys(md->pfn);
817 vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING;
818 vm->flags |= VM_ARM_MTYPE(md->type);
819 vm->caller = iotable_init;
820 vm_area_add_early(vm++);
824 static void * __initdata vmalloc_min =
825 (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET);
828 * vmalloc=size forces the vmalloc area to be exactly 'size'
829 * bytes. This can be used to increase (or decrease) the vmalloc
830 * area - the default is 240m.
832 static int __init early_vmalloc(char *arg)
834 unsigned long vmalloc_reserve = memparse(arg, NULL);
836 if (vmalloc_reserve < SZ_16M) {
837 vmalloc_reserve = SZ_16M;
839 "vmalloc area too small, limiting to %luMB\n",
840 vmalloc_reserve >> 20);
843 if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) {
844 vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M);
846 "vmalloc area is too big, limiting to %luMB\n",
847 vmalloc_reserve >> 20);
850 vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve);
853 early_param("vmalloc", early_vmalloc);
855 phys_addr_t arm_lowmem_limit __initdata = 0;
857 void __init sanity_check_meminfo(void)
859 int i, j, highmem = 0;
861 for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
862 struct membank *bank = &meminfo.bank[j];
863 *bank = meminfo.bank[i];
865 if (bank->start > ULONG_MAX)
868 #ifdef CONFIG_HIGHMEM
869 if (__va(bank->start) >= vmalloc_min ||
870 __va(bank->start) < (void *)PAGE_OFFSET)
873 bank->highmem = highmem;
876 * Split those memory banks which are partially overlapping
877 * the vmalloc area greatly simplifying things later.
879 if (!highmem && __va(bank->start) < vmalloc_min &&
880 bank->size > vmalloc_min - __va(bank->start)) {
881 if (meminfo.nr_banks >= NR_BANKS) {
882 printk(KERN_CRIT "NR_BANKS too low, "
883 "ignoring high memory\n");
885 memmove(bank + 1, bank,
886 (meminfo.nr_banks - i) * sizeof(*bank));
889 bank[1].size -= vmalloc_min - __va(bank->start);
890 bank[1].start = __pa(vmalloc_min - 1) + 1;
891 bank[1].highmem = highmem = 1;
894 bank->size = vmalloc_min - __va(bank->start);
897 bank->highmem = highmem;
900 * Highmem banks not allowed with !CONFIG_HIGHMEM.
903 printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
904 "(!CONFIG_HIGHMEM).\n",
905 (unsigned long long)bank->start,
906 (unsigned long long)bank->start + bank->size - 1);
911 * Check whether this memory bank would entirely overlap
914 if (__va(bank->start) >= vmalloc_min ||
915 __va(bank->start) < (void *)PAGE_OFFSET) {
916 printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
917 "(vmalloc region overlap).\n",
918 (unsigned long long)bank->start,
919 (unsigned long long)bank->start + bank->size - 1);
924 * Check whether this memory bank would partially overlap
927 if (__va(bank->start + bank->size) > vmalloc_min ||
928 __va(bank->start + bank->size) < __va(bank->start)) {
929 unsigned long newsize = vmalloc_min - __va(bank->start);
930 printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx "
931 "to -%.8llx (vmalloc region overlap).\n",
932 (unsigned long long)bank->start,
933 (unsigned long long)bank->start + bank->size - 1,
934 (unsigned long long)bank->start + newsize - 1);
935 bank->size = newsize;
938 if (!bank->highmem && bank->start + bank->size > arm_lowmem_limit)
939 arm_lowmem_limit = bank->start + bank->size;
943 #ifdef CONFIG_HIGHMEM
945 const char *reason = NULL;
947 if (cache_is_vipt_aliasing()) {
949 * Interactions between kmap and other mappings
950 * make highmem support with aliasing VIPT caches
953 reason = "with VIPT aliasing cache";
956 printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n",
958 while (j > 0 && meminfo.bank[j - 1].highmem)
963 meminfo.nr_banks = j;
964 high_memory = __va(arm_lowmem_limit - 1) + 1;
965 memblock_set_current_limit(arm_lowmem_limit);
968 static inline void prepare_page_table(void)
974 * Clear out all the mappings below the kernel image.
976 for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE)
977 pmd_clear(pmd_off_k(addr));
979 #ifdef CONFIG_XIP_KERNEL
980 /* The XIP kernel is mapped in the module area -- skip over it */
981 addr = ((unsigned long)_etext + PMD_SIZE - 1) & PMD_MASK;
983 for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE)
984 pmd_clear(pmd_off_k(addr));
987 * Find the end of the first block of lowmem.
989 end = memblock.memory.regions[0].base + memblock.memory.regions[0].size;
990 if (end >= arm_lowmem_limit)
991 end = arm_lowmem_limit;
994 * Clear out all the kernel space mappings, except for the first
995 * memory bank, up to the vmalloc region.
997 for (addr = __phys_to_virt(end);
998 addr < VMALLOC_START; addr += PMD_SIZE)
999 pmd_clear(pmd_off_k(addr));
1002 #ifdef CONFIG_ARM_LPAE
1003 /* the first page is reserved for pgd */
1004 #define SWAPPER_PG_DIR_SIZE (PAGE_SIZE + \
1005 PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t))
1007 #define SWAPPER_PG_DIR_SIZE (PTRS_PER_PGD * sizeof(pgd_t))
1011 * Reserve the special regions of memory
1013 void __init arm_mm_memblock_reserve(void)
1016 * Reserve the page tables. These are already in use,
1017 * and can only be in node 0.
1019 memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE);
1021 #ifdef CONFIG_SA1111
1023 * Because of the SA1111 DMA bug, we want to preserve our
1024 * precious DMA-able memory...
1026 memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
1031 * Set up the device mappings. Since we clear out the page tables for all
1032 * mappings above VMALLOC_START, we will remove any debug device mappings.
1033 * This means you have to be careful how you debug this function, or any
1034 * called function. This means you can't use any function or debugging
1035 * method which may touch any device, otherwise the kernel _will_ crash.
1037 static void __init devicemaps_init(struct machine_desc *mdesc)
1039 struct map_desc map;
1043 * Allocate the vector page early.
1045 vectors_page = early_alloc(PAGE_SIZE);
1047 for (addr = VMALLOC_START; addr; addr += PMD_SIZE)
1048 pmd_clear(pmd_off_k(addr));
1051 * Map the kernel if it is XIP.
1052 * It is always first in the modulearea.
1054 #ifdef CONFIG_XIP_KERNEL
1055 map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
1056 map.virtual = MODULES_VADDR;
1057 map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK;
1059 create_mapping(&map);
1063 * Map the cache flushing regions.
1066 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
1067 map.virtual = FLUSH_BASE;
1069 map.type = MT_CACHECLEAN;
1070 create_mapping(&map);
1072 #ifdef FLUSH_BASE_MINICACHE
1073 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
1074 map.virtual = FLUSH_BASE_MINICACHE;
1076 map.type = MT_MINICLEAN;
1077 create_mapping(&map);
1081 * Create a mapping for the machine vectors at the high-vectors
1082 * location (0xffff0000). If we aren't using high-vectors, also
1083 * create a mapping at the low-vectors virtual address.
1085 map.pfn = __phys_to_pfn(virt_to_phys(vectors_page));
1086 map.virtual = 0xffff0000;
1087 map.length = PAGE_SIZE;
1088 map.type = MT_HIGH_VECTORS;
1089 create_mapping(&map);
1091 if (!vectors_high()) {
1093 map.type = MT_LOW_VECTORS;
1094 create_mapping(&map);
1098 * Ask the machine support to map in the statically mapped devices.
1104 * Finally flush the caches and tlb to ensure that we're in a
1105 * consistent state wrt the writebuffer. This also ensures that
1106 * any write-allocated cache lines in the vector page are written
1107 * back. After this point, we can start to touch devices again.
1109 local_flush_tlb_all();
1113 static void __init kmap_init(void)
1115 #ifdef CONFIG_HIGHMEM
1116 pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE),
1117 PKMAP_BASE, _PAGE_KERNEL_TABLE);
1121 static void __init map_lowmem(void)
1123 struct memblock_region *reg;
1125 /* Map all the lowmem memory banks. */
1126 for_each_memblock(memory, reg) {
1127 phys_addr_t start = reg->base;
1128 phys_addr_t end = start + reg->size;
1129 struct map_desc map;
1131 if (end > arm_lowmem_limit)
1132 end = arm_lowmem_limit;
1136 map.pfn = __phys_to_pfn(start);
1137 map.virtual = __phys_to_virt(start);
1138 map.length = end - start;
1139 map.type = MT_MEMORY;
1141 create_mapping(&map);
1146 * paging_init() sets up the page tables, initialises the zone memory
1147 * maps, and sets up the zero page, bad page and bad page tables.
1149 void __init paging_init(struct machine_desc *mdesc)
1153 memblock_set_current_limit(arm_lowmem_limit);
1155 build_mem_type_table();
1156 prepare_page_table();
1158 dma_contiguous_remap();
1159 devicemaps_init(mdesc);
1162 top_pmd = pmd_off_k(0xffff0000);
1164 /* allocate the zero page. */
1165 zero_page = early_alloc(PAGE_SIZE);
1169 empty_zero_page = virt_to_page(zero_page);
1170 __flush_dcache_page(NULL, empty_zero_page);