arch/arm/mm/mmu.c

   1 /*
   2  *  linux/arch/arm/mm/mmu.c
   3  *
   4  *  Copyright (C) 1995-2005 Russell King
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #include <linux/module.h>
  11 #include <linux/kernel.h>
  12 #include <linux/errno.h>
  13 #include <linux/init.h>
  14 #include <linux/mman.h>
  15 #include <linux/nodemask.h>
  16 #include <linux/memblock.h>
  17 #include <linux/fs.h>
  18
  19 #include <asm/cputype.h>
  20 #include <asm/sections.h>
  21 #include <asm/cachetype.h>
  22 #include <asm/setup.h>
  23 #include <asm/sizes.h>
  24 #include <asm/smp_plat.h>
  25 #include <asm/tlb.h>
  26 #include <asm/highmem.h>
  27 #include <asm/traps.h>
  28
  29 #include <asm/mach/arch.h>
  30 #include <asm/mach/map.h>
  31
  32 #include "mm.h"
  33
  34 /*
  35  * empty_zero_page is a special page that is used for
  36  * zero-initialized data and COW.
  37  */
  38 struct page *empty_zero_page;
  39 EXPORT_SYMBOL(empty_zero_page);
  40
  41 /*
  42  * The pmd table for the upper-most set of pages.
  43  */
  44 pmd_t *top_pmd;
  45
  46 #define CPOLICY_UNCACHED        0
  47 #define CPOLICY_BUFFERED        1
  48 #define CPOLICY_WRITETHROUGH    2
  49 #define CPOLICY_WRITEBACK       3
  50 #define CPOLICY_WRITEALLOC      4
  51
  52 static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
  53 static unsigned int ecc_mask __initdata = 0;
  54 pgprot_t pgprot_user;
  55 pgprot_t pgprot_kernel;
  56
  57 EXPORT_SYMBOL(pgprot_user);
  58 EXPORT_SYMBOL(pgprot_kernel);
  59
  60 struct cachepolicy {
  61         const char      policy[16];
  62         unsigned int    cr_mask;
  63         pmdval_t        pmd;
  64         pteval_t        pte;
  65 };
  66
  67 static struct cachepolicy cache_policies[] __initdata = {
  68         {
  69                 .policy         = "uncached",
  70                 .cr_mask        = CR_W|CR_C,
  71                 .pmd            = PMD_SECT_UNCACHED,
  72                 .pte            = L_PTE_MT_UNCACHED,
  73         }, {
  74                 .policy         = "buffered",
  75                 .cr_mask        = CR_C,
  76                 .pmd            = PMD_SECT_BUFFERED,
  77                 .pte            = L_PTE_MT_BUFFERABLE,
  78         }, {
  79                 .policy         = "writethrough",
  80                 .cr_mask        = 0,
  81                 .pmd            = PMD_SECT_WT,
  82                 .pte            = L_PTE_MT_WRITETHROUGH,
  83         }, {
  84                 .policy         = "writeback",
  85                 .cr_mask        = 0,
  86                 .pmd            = PMD_SECT_WB,
  87                 .pte            = L_PTE_MT_WRITEBACK,
  88         }, {
  89                 .policy         = "writealloc",
  90                 .cr_mask        = 0,
  91                 .pmd            = PMD_SECT_WBWA,
  92                 .pte            = L_PTE_MT_WRITEALLOC,
  93         }
  94 };
  95
  96 /*
  97  * These are useful for identifying cache coherency
  98  * problems by allowing the cache or the cache and
  99  * writebuffer to be turned off.  (Note: the write
 100  * buffer should not be on and the cache off).
 101  */
 102 static int __init early_cachepolicy(char *p)
 103 {
 104         int i;
 105
 106         for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
 107                 int len = strlen(cache_policies[i].policy);
 108
 109                 if (memcmp(p, cache_policies[i].policy, len) == 0) {
 110                         cachepolicy = i;
 111                         cr_alignment &= ~cache_policies[i].cr_mask;
 112                         cr_no_alignment &= ~cache_policies[i].cr_mask;
 113                         break;
 114                 }
 115         }
 116         if (i == ARRAY_SIZE(cache_policies))
 117                 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
 118         /*
 119          * This restriction is partly to do with the way we boot; it is
 120          * unpredictable to have memory mapped using two different sets of
 121          * memory attributes (shared, type, and cache attribs).  We can not
 122          * change these attributes once the initial assembly has setup the
 123          * page tables.
 124          */
 125         if (cpu_architecture() >= CPU_ARCH_ARMv6) {
 126                 printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
 127                 cachepolicy = CPOLICY_WRITEBACK;
 128         }
 129         flush_cache_all();
 130         set_cr(cr_alignment);
 131         return 0;
 132 }
 133 early_param("cachepolicy", early_cachepolicy);
 134
 135 static int __init early_nocache(char *__unused)
 136 {
 137         char *p = "buffered";
 138         printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
 139         early_cachepolicy(p);
 140         return 0;
 141 }
 142 early_param("nocache", early_nocache);
 143
 144 static int __init early_nowrite(char *__unused)
 145 {
 146         char *p = "uncached";
 147         printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
 148         early_cachepolicy(p);
 149         return 0;
 150 }
 151 early_param("nowb", early_nowrite);
 152
 153 #ifndef CONFIG_ARM_LPAE
 154 static int __init early_ecc(char *p)
 155 {
 156         if (memcmp(p, "on", 2) == 0)
 157                 ecc_mask = PMD_PROTECTION;
 158         else if (memcmp(p, "off", 3) == 0)
 159                 ecc_mask = 0;
 160         return 0;
 161 }
 162 early_param("ecc", early_ecc);
 163 #endif
 164
 165 static int __init noalign_setup(char *__unused)
 166 {
 167         cr_alignment &= ~CR_A;
 168         cr_no_alignment &= ~CR_A;
 169         set_cr(cr_alignment);
 170         return 1;
 171 }
 172 __setup("noalign", noalign_setup);
 173
 174 #ifndef CONFIG_SMP
 175 void adjust_cr(unsigned long mask, unsigned long set)
 176 {
 177         unsigned long flags;
 178
 179         mask &= ~CR_A;
 180
 181         set &= mask;
 182
 183         local_irq_save(flags);
 184
 185         cr_no_alignment = (cr_no_alignment & ~mask) | set;
 186         cr_alignment = (cr_alignment & ~mask) | set;
 187
 188         set_cr((get_cr() & ~mask) | set);
 189
 190         local_irq_restore(flags);
 191 }
 192 #endif
 193
 194 #define PROT_PTE_DEVICE         L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
 195 #define PROT_SECT_DEVICE        PMD_TYPE_SECT|PMD_SECT_AP_WRITE
 196
 197 static struct mem_type mem_types[] = {
 198         [MT_DEVICE] = {           /* Strongly ordered / ARMv6 shared device */
 199                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
 200                                   L_PTE_SHARED,
 201                 .prot_l1        = PMD_TYPE_TABLE,
 202                 .prot_sect      = PROT_SECT_DEVICE | PMD_SECT_S,
 203                 .domain         = DOMAIN_IO,
 204         },
 205         [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
 206                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
 207                 .prot_l1        = PMD_TYPE_TABLE,
 208                 .prot_sect      = PROT_SECT_DEVICE,
 209                 .domain         = DOMAIN_IO,
 210         },
 211         [MT_DEVICE_CACHED] = {    /* ioremap_cached */
 212                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
 213                 .prot_l1        = PMD_TYPE_TABLE,
 214                 .prot_sect      = PROT_SECT_DEVICE | PMD_SECT_WB,
 215                 .domain         = DOMAIN_IO,
 216         },
 217         [MT_DEVICE_WC] = {      /* ioremap_wc */
 218                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
 219                 .prot_l1        = PMD_TYPE_TABLE,
 220                 .prot_sect      = PROT_SECT_DEVICE,
 221                 .domain         = DOMAIN_IO,
 222         },
 223         [MT_UNCACHED] = {
 224                 .prot_pte       = PROT_PTE_DEVICE,
 225                 .prot_l1        = PMD_TYPE_TABLE,
 226                 .prot_sect      = PMD_TYPE_SECT | PMD_SECT_XN,
 227                 .domain         = DOMAIN_IO,
 228         },
 229         [MT_CACHECLEAN] = {
 230                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
 231                 .domain    = DOMAIN_KERNEL,
 232         },
 233 #ifndef CONFIG_ARM_LPAE
 234         [MT_MINICLEAN] = {
 235                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
 236                 .domain    = DOMAIN_KERNEL,
 237         },
 238 #endif
 239         [MT_LOW_VECTORS] = {
 240                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 241                                 L_PTE_RDONLY,
 242                 .prot_l1   = PMD_TYPE_TABLE,
 243                 .domain    = DOMAIN_USER,
 244         },
 245         [MT_HIGH_VECTORS] = {
 246                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 247                                 L_PTE_USER | L_PTE_RDONLY,
 248                 .prot_l1   = PMD_TYPE_TABLE,
 249                 .domain    = DOMAIN_USER,
 250         },
 251         [MT_MEMORY] = {
 252                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
 253                 .prot_l1   = PMD_TYPE_TABLE,
 254                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
 255                 .domain    = DOMAIN_KERNEL,
 256         },
 257         [MT_ROM] = {
 258                 .prot_sect = PMD_TYPE_SECT,
 259                 .domain    = DOMAIN_KERNEL,
 260         },
 261         [MT_MEMORY_NONCACHED] = {
 262                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 263                                 L_PTE_MT_BUFFERABLE,
 264                 .prot_l1   = PMD_TYPE_TABLE,
 265                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
 266                 .domain    = DOMAIN_KERNEL,
 267         },
 268         [MT_MEMORY_DTCM] = {
 269                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 270                                 L_PTE_XN,
 271                 .prot_l1   = PMD_TYPE_TABLE,
 272                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
 273                 .domain    = DOMAIN_KERNEL,
 274         },
 275         [MT_MEMORY_ITCM] = {
 276                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
 277                 .prot_l1   = PMD_TYPE_TABLE,
 278                 .domain    = DOMAIN_KERNEL,
 279         },
 280         [MT_MEMORY_SO] = {
 281                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 282                                 L_PTE_MT_UNCACHED,
 283                 .prot_l1   = PMD_TYPE_TABLE,
 284                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S |
 285                                 PMD_SECT_UNCACHED | PMD_SECT_XN,
 286                 .domain    = DOMAIN_KERNEL,
 287         },
 288         [MT_MEMORY_DMA_READY] = {
 289                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
 290                 .prot_l1   = PMD_TYPE_TABLE,
 291                 .domain    = DOMAIN_KERNEL,
 292         },
 293 };
 294
 295 const struct mem_type *get_mem_type(unsigned int type)
 296 {
 297         return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
 298 }
 299 EXPORT_SYMBOL(get_mem_type);
 300
 301 /*
 302  * If the system supports huge pages and we are running with short descriptors,
 303  * then compute the pmd and linux pte prot values for a huge page.
 304  *
 305  * These values are used by both the HugeTLB and THP code.
 306  */
 307 #if defined(CONFIG_SYS_SUPPORTS_HUGETLBFS) && !defined(CONFIG_ARM_LPAE)
 308 pmdval_t arm_hugepmdprotval;
 309 EXPORT_SYMBOL(arm_hugepmdprotval);
 310
 311 pteval_t arm_hugepteprotval;
 312 EXPORT_SYMBOL(arm_hugepteprotval);
 313 #endif
 314
 315
 316 /*
 317  * Adjust the PMD section entries according to the CPU in use.
 318  */
 319 static void __init build_mem_type_table(void)
 320 {
 321         struct cachepolicy *cp;
 322         unsigned int cr = get_cr();
 323         pteval_t user_pgprot, kern_pgprot, vecs_pgprot;
 324         int cpu_arch = cpu_architecture();
 325         int i;
 326
 327         if (cpu_arch < CPU_ARCH_ARMv6) {
 328 #if defined(CONFIG_CPU_DCACHE_DISABLE)
 329                 if (cachepolicy > CPOLICY_BUFFERED)
 330                         cachepolicy = CPOLICY_BUFFERED;
 331 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
 332                 if (cachepolicy > CPOLICY_WRITETHROUGH)
 333                         cachepolicy = CPOLICY_WRITETHROUGH;
 334 #endif
 335         }
 336         if (cpu_arch < CPU_ARCH_ARMv5) {
 337                 if (cachepolicy >= CPOLICY_WRITEALLOC)
 338                         cachepolicy = CPOLICY_WRITEBACK;
 339                 ecc_mask = 0;
 340         }
 341         if (is_smp())
 342                 cachepolicy = CPOLICY_WRITEALLOC;
 343
 344         /*
 345          * Strip out features not present on earlier architectures.
 346          * Pre-ARMv5 CPUs don't have TEX bits.  Pre-ARMv6 CPUs or those
 347          * without extended page tables don't have the 'Shared' bit.
 348          */
 349         if (cpu_arch < CPU_ARCH_ARMv5)
 350                 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
 351                         mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
 352         if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
 353                 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
 354                         mem_types[i].prot_sect &= ~PMD_SECT_S;
 355
 356         /*
 357          * ARMv5 and lower, bit 4 must be set for page tables (was: cache
 358          * "update-able on write" bit on ARM610).  However, Xscale and
 359          * Xscale3 require this bit to be cleared.
 360          */
 361         if (cpu_is_xscale() || cpu_is_xsc3()) {
 362                 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
 363                         mem_types[i].prot_sect &= ~PMD_BIT4;
 364                         mem_types[i].prot_l1 &= ~PMD_BIT4;
 365                 }
 366         } else if (cpu_arch < CPU_ARCH_ARMv6) {
 367                 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
 368                         if (mem_types[i].prot_l1)
 369                                 mem_types[i].prot_l1 |= PMD_BIT4;
 370                         if (mem_types[i].prot_sect)
 371                                 mem_types[i].prot_sect |= PMD_BIT4;
 372                 }
 373         }
 374
 375         /*
 376          * Mark the device areas according to the CPU/architecture.
 377          */
 378         if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
 379                 if (!cpu_is_xsc3()) {
 380                         /*
 381                          * Mark device regions on ARMv6+ as execute-never
 382                          * to prevent speculative instruction fetches.
 383                          */
 384                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
 385                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
 386                         mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
 387                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
 388                 }
 389                 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
 390                         /*
 391                          * For ARMv7 with TEX remapping,
 392                          * - shared device is SXCB=1100
 393                          * - nonshared device is SXCB=0100
 394                          * - write combine device mem is SXCB=0001
 395                          * (Uncached Normal memory)
 396                          */
 397                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
 398                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
 399                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
 400                 } else if (cpu_is_xsc3()) {
 401                         /*
 402                          * For Xscale3,
 403                          * - shared device is TEXCB=00101
 404                          * - nonshared device is TEXCB=01000
 405                          * - write combine device mem is TEXCB=00100
 406                          * (Inner/Outer Uncacheable in xsc3 parlance)
 407                          */
 408                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
 409                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
 410                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
 411                 } else {
 412                         /*
 413                          * For ARMv6 and ARMv7 without TEX remapping,
 414                          * - shared device is TEXCB=00001
 415                          * - nonshared device is TEXCB=01000
 416                          * - write combine device mem is TEXCB=00100
 417                          * (Uncached Normal in ARMv6 parlance).
 418                          */
 419                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
 420                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
 421                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
 422                 }
 423         } else {
 424                 /*
 425                  * On others, write combining is "Uncached/Buffered"
 426                  */
 427                 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
 428         }
 429
 430         /*
 431          * Now deal with the memory-type mappings
 432          */
 433         cp = &cache_policies[cachepolicy];
 434         vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
 435
 436         /*
 437          * Only use write-through for non-SMP systems
 438          */
 439         if (!is_smp() && cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH)
 440                 vecs_pgprot = cache_policies[CPOLICY_WRITETHROUGH].pte;
 441
 442         /*
 443          * Enable CPU-specific coherency if supported.
 444          * (Only available on XSC3 at the moment.)
 445          */
 446         if (arch_is_coherent() && cpu_is_xsc3()) {
 447                 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
 448                 mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
 449                 mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED;
 450                 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
 451                 mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
 452         }
 453         /*
 454          * ARMv6 and above have extended page tables.
 455          */
 456         if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
 457 #ifndef CONFIG_ARM_LPAE
 458                 /*
 459                  * Mark cache clean areas and XIP ROM read only
 460                  * from SVC mode and no access from userspace.
 461                  */
 462                 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 463                 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 464                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 465 #endif
 466
 467                 if (is_smp()) {
 468                         /*
 469                          * Mark memory with the "shared" attribute
 470                          * for SMP systems
 471                          */
 472                         user_pgprot |= L_PTE_SHARED;
 473                         kern_pgprot |= L_PTE_SHARED;
 474                         vecs_pgprot |= L_PTE_SHARED;
 475                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
 476                         mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
 477                         mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
 478                         mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
 479                         mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
 480                         mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
 481                         mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED;
 482                         mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
 483                         mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
 484                 }
 485         }
 486
 487         /*
 488          * Non-cacheable Normal - intended for memory areas that must
 489          * not cause dirty cache line writebacks when used
 490          */
 491         if (cpu_arch >= CPU_ARCH_ARMv6) {
 492                 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
 493                         /* Non-cacheable Normal is XCB = 001 */
 494                         mem_types[MT_MEMORY_NONCACHED].prot_sect |=
 495                                 PMD_SECT_BUFFERED;
 496                 } else {
 497                         /* For both ARMv6 and non-TEX-remapping ARMv7 */
 498                         mem_types[MT_MEMORY_NONCACHED].prot_sect |=
 499                                 PMD_SECT_TEX(1);
 500                 }
 501         } else {
 502                 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
 503         }
 504
 505 #ifdef CONFIG_ARM_LPAE
 506         /*
 507          * Do not generate access flag faults for the kernel mappings.
 508          */
 509         for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
 510                 mem_types[i].prot_pte |= PTE_EXT_AF;
 511                 mem_types[i].prot_sect |= PMD_SECT_AF;
 512         }
 513         kern_pgprot |= PTE_EXT_AF;
 514         vecs_pgprot |= PTE_EXT_AF;
 515 #endif
 516
 517         for (i = 0; i < 16; i++) {
 518                 pteval_t v = pgprot_val(protection_map[i]);
 519                 protection_map[i] = __pgprot(v | user_pgprot);
 520         }
 521
 522         mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
 523         mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
 524
 525         pgprot_user   = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
 526         pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
 527                                  L_PTE_DIRTY | kern_pgprot);
 528
 529         mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
 530         mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
 531         mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
 532         mem_types[MT_MEMORY].prot_pte |= kern_pgprot;
 533         mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot;
 534         mem_types[MT_MEMORY_NONCACHED].prot_sect |= ecc_mask;
 535         mem_types[MT_ROM].prot_sect |= cp->pmd;
 536
 537         switch (cp->pmd) {
 538         case PMD_SECT_WT:
 539                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
 540                 break;
 541         case PMD_SECT_WB:
 542         case PMD_SECT_WBWA:
 543                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
 544                 break;
 545         }
 546         printk("Memory policy: ECC %sabled, Data cache %s\n",
 547                 ecc_mask ? "en" : "dis", cp->policy);
 548
 549         for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
 550                 struct mem_type *t = &mem_types[i];
 551                 if (t->prot_l1)
 552                         t->prot_l1 |= PMD_DOMAIN(t->domain);
 553                 if (t->prot_sect)
 554                         t->prot_sect |= PMD_DOMAIN(t->domain);
 555         }
 556
 557 #if defined(CONFIG_SYS_SUPPORTS_HUGETLBFS) && !defined(CONFIG_ARM_LPAE)
 558         /*
 559          * we assume all huge pages are user pages and that hardware access
 560          * flag updates are disabled (i.e. SCTLR.AFE == 0b).
 561          */
 562         arm_hugepteprotval = mem_types[MT_MEMORY].prot_pte | L_PTE_USER | L_PTE_VALID;
 563
 564         arm_hugepmdprotval = mem_types[MT_MEMORY].prot_sect | PMD_SECT_AP_READ
 565                                 | PMD_SECT_nG;
 566 #endif
 567
 568 }
 569
 570 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
 571 pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
 572                               unsigned long size, pgprot_t vma_prot)
 573 {
 574         if (!pfn_valid(pfn))
 575                 return pgprot_noncached(vma_prot);
 576         else if (file->f_flags & O_SYNC)
 577                 return pgprot_writecombine(vma_prot);
 578         return vma_prot;
 579 }
 580 EXPORT_SYMBOL(phys_mem_access_prot);
 581 #endif
 582
 583 #define vectors_base()  (vectors_high() ? 0xffff0000 : 0)
 584
 585 static void __init *early_alloc(unsigned long sz)
 586 {
 587         void *ptr = __va(memblock_alloc(sz, sz));
 588         memset(ptr, 0, sz);
 589         return ptr;
 590 }
 591
 592 static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot)
 593 {
 594         if (pmd_none(*pmd)) {
 595                 pte_t *pte = early_alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE);
 596                 __pmd_populate(pmd, __pa(pte), prot);
 597         }
 598         BUG_ON(pmd_bad(*pmd));
 599         return pte_offset_kernel(pmd, addr);
 600 }
 601
 602 static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
 603                                   unsigned long end, unsigned long pfn,
 604                                   const struct mem_type *type)
 605 {
 606         pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1);
 607         do {
 608                 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0);
 609                 pfn++;
 610         } while (pte++, addr += PAGE_SIZE, addr != end);
 611 }
 612
 613 static void __init alloc_init_section(pud_t *pud, unsigned long addr,
 614                                       unsigned long end, phys_addr_t phys,
 615                                       const struct mem_type *type)
 616 {
 617         pmd_t *pmd = pmd_offset(pud, addr);
 618
 619         /*
 620          * Try a section mapping - end, addr and phys must all be aligned
 621          * to a section boundary.  Note that PMDs refer to the individual
 622          * L1 entries, whereas PGDs refer to a group of L1 entries making
 623          * up one logical pointer to an L2 table.
 624          */
 625         if (type->prot_sect && ((addr | end | phys) & ~SECTION_MASK) == 0) {
 626                 pmd_t *p = pmd;
 627
 628 #ifndef CONFIG_ARM_LPAE
 629                 if (addr & SECTION_SIZE)
 630                         pmd++;
 631 #endif
 632
 633                 do {
 634                         *pmd = __pmd(phys | type->prot_sect);
 635                         phys += SECTION_SIZE;
 636                 } while (pmd++, addr += SECTION_SIZE, addr != end);
 637
 638                 flush_pmd_entry(p);
 639         } else {
 640                 /*
 641                  * No need to loop; pte's aren't interested in the
 642                  * individual L1 entries.
 643                  */
 644                 alloc_init_pte(pmd, addr, end, __phys_to_pfn(phys), type);
 645         }
 646 }
 647
 648 static void alloc_init_pud(pgd_t *pgd, unsigned long addr, unsigned long end,
 649         unsigned long phys, const struct mem_type *type)
 650 {
 651         pud_t *pud = pud_offset(pgd, addr);
 652         unsigned long next;
 653
 654         do {
 655                 next = pud_addr_end(addr, end);
 656                 alloc_init_section(pud, addr, next, phys, type);
 657                 phys += next - addr;
 658         } while (pud++, addr = next, addr != end);
 659 }
 660
 661 #ifndef CONFIG_ARM_LPAE
 662 static void __init create_36bit_mapping(struct map_desc *md,
 663                                         const struct mem_type *type)
 664 {
 665         unsigned long addr, length, end;
 666         phys_addr_t phys;
 667         pgd_t *pgd;
 668
 669         addr = md->virtual;
 670         phys = __pfn_to_phys(md->pfn);
 671         length = PAGE_ALIGN(md->length);
 672
 673         if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
 674                 printk(KERN_ERR "MM: CPU does not support supersection "
 675                        "mapping for 0x%08llx at 0x%08lx\n",
 676                        (long long)__pfn_to_phys((u64)md->pfn), addr);
 677                 return;
 678         }
 679
 680         /* N.B. ARMv6 supersections are only defined to work with domain 0.
 681          *      Since domain assignments can in fact be arbitrary, the
 682          *      'domain == 0' check below is required to insure that ARMv6
 683          *      supersections are only allocated for domain 0 regardless
 684          *      of the actual domain assignments in use.
 685          */
 686         if (type->domain) {
 687                 printk(KERN_ERR "MM: invalid domain in supersection "
 688                        "mapping for 0x%08llx at 0x%08lx\n",
 689                        (long long)__pfn_to_phys((u64)md->pfn), addr);
 690                 return;
 691         }
 692
 693         if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
 694                 printk(KERN_ERR "MM: cannot create mapping for 0x%08llx"
 695                        " at 0x%08lx invalid alignment\n",
 696                        (long long)__pfn_to_phys((u64)md->pfn), addr);
 697                 return;
 698         }
 699
 700         /*
 701          * Shift bits [35:32] of address into bits [23:20] of PMD
 702          * (See ARMv6 spec).
 703          */
 704         phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
 705
 706         pgd = pgd_offset_k(addr);
 707         end = addr + length;
 708         do {
 709                 pud_t *pud = pud_offset(pgd, addr);
 710                 pmd_t *pmd = pmd_offset(pud, addr);
 711                 int i;
 712
 713                 for (i = 0; i < 16; i++)
 714                         *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER);
 715
 716                 addr += SUPERSECTION_SIZE;
 717                 phys += SUPERSECTION_SIZE;
 718                 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
 719         } while (addr != end);
 720 }
 721 #endif  /* !CONFIG_ARM_LPAE */
 722
 723 /*
 724  * Create the page directory entries and any necessary
 725  * page tables for the mapping specified by `md'.  We
 726  * are able to cope here with varying sizes and address
 727  * offsets, and we take full advantage of sections and
 728  * supersections.
 729  */
 730 static void __init create_mapping(struct map_desc *md)
 731 {
 732         unsigned long addr, length, end;
 733         phys_addr_t phys;
 734         const struct mem_type *type;
 735         pgd_t *pgd;
 736
 737         if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
 738                 printk(KERN_WARNING "BUG: not creating mapping for 0x%08llx"
 739                        " at 0x%08lx in user region\n",
 740                        (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
 741                 return;
 742         }
 743
 744         if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
 745             md->virtual >= PAGE_OFFSET && md->virtual < VMALLOC_END) {
 746                 printk(KERN_WARNING "BUG: mapping for 0x%08llx"
 747                        " at 0x%08lx overlaps vmalloc space\n",
 748                        (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
 749         }
 750
 751         type = &mem_types[md->type];
 752
 753 #ifndef CONFIG_ARM_LPAE
 754         /*
 755          * Catch 36-bit addresses
 756          */
 757         if (md->pfn >= 0x100000) {
 758                 create_36bit_mapping(md, type);
 759                 return;
 760         }
 761 #endif
 762
 763         addr = md->virtual & PAGE_MASK;
 764         phys = __pfn_to_phys(md->pfn);
 765         length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
 766
 767         if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
 768                 printk(KERN_WARNING "BUG: map for 0x%08llx at 0x%08lx can not "
 769                        "be mapped using pages, ignoring.\n",
 770                        (long long)__pfn_to_phys(md->pfn), addr);
 771                 return;
 772         }
 773
 774         pgd = pgd_offset_k(addr);
 775         end = addr + length;
 776         do {
 777                 unsigned long next = pgd_addr_end(addr, end);
 778
 779                 alloc_init_pud(pgd, addr, next, phys, type);
 780
 781                 phys += next - addr;
 782                 addr = next;
 783         } while (pgd++, addr != end);
 784 }
 785
 786 /*
 787  * Create the architecture specific mappings
 788  */
 789 void __init iotable_init(struct map_desc *io_desc, int nr)
 790 {
 791         int i;
 792
 793         for (i = 0; i < nr; i++)
 794                 create_mapping(io_desc + i);
 795 }
 796
 797 static void * __initdata vmalloc_min = (void *)(VMALLOC_END - SZ_128M);
 798
 799 /*
 800  * vmalloc=size forces the vmalloc area to be exactly 'size'
 801  * bytes. This can be used to increase (or decrease) the vmalloc
 802  * area - the default is 128m.
 803  */
 804 static int __init early_vmalloc(char *arg)
 805 {
 806         unsigned long vmalloc_reserve = memparse(arg, NULL);
 807
 808         if (vmalloc_reserve < SZ_16M) {
 809                 vmalloc_reserve = SZ_16M;
 810                 printk(KERN_WARNING
 811                         "vmalloc area too small, limiting to %luMB\n",
 812                         vmalloc_reserve >> 20);
 813         }
 814
 815         if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) {
 816                 vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M);
 817                 printk(KERN_WARNING
 818                         "vmalloc area is too big, limiting to %luMB\n",
 819                         vmalloc_reserve >> 20);
 820         }
 821
 822         vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve);
 823         return 0;
 824 }
 825 early_param("vmalloc", early_vmalloc);
 826
 827 phys_addr_t arm_lowmem_limit __initdata = 0;
 828
 829 void __init sanity_check_meminfo(void)
 830 {
 831         int i, j, highmem = 0;
 832
 833         for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
 834                 struct membank *bank = &meminfo.bank[j];
 835                 *bank = meminfo.bank[i];
 836
 837                 if (bank->start > ULONG_MAX)
 838                         highmem = 1;
 839
 840 #ifdef CONFIG_HIGHMEM
 841                 if (__va(bank->start) >= vmalloc_min ||
 842                     __va(bank->start) < (void *)PAGE_OFFSET)
 843                         highmem = 1;
 844
 845                 bank->highmem = highmem;
 846
 847                 /*
 848                  * Split those memory banks which are partially overlapping
 849                  * the vmalloc area greatly simplifying things later.
 850                  */
 851                 if (!highmem && __va(bank->start) < vmalloc_min &&
 852                     bank->size > vmalloc_min - __va(bank->start)) {
 853                         if (meminfo.nr_banks >= NR_BANKS) {
 854                                 printk(KERN_CRIT "NR_BANKS too low, "
 855                                                  "ignoring high memory\n");
 856                         } else {
 857                                 memmove(bank + 1, bank,
 858                                         (meminfo.nr_banks - i) * sizeof(*bank));
 859                                 meminfo.nr_banks++;
 860                                 i++;
 861                                 bank[1].size -= vmalloc_min - __va(bank->start);
 862                                 bank[1].start = __pa(vmalloc_min - 1) + 1;
 863                                 bank[1].highmem = highmem = 1;
 864                                 j++;
 865                         }
 866                         bank->size = vmalloc_min - __va(bank->start);
 867                 }
 868 #else
 869                 bank->highmem = highmem;
 870
 871                 /*
 872                  * Highmem banks not allowed with !CONFIG_HIGHMEM.
 873                  */
 874                 if (highmem) {
 875                         printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
 876                                "(!CONFIG_HIGHMEM).\n",
 877                                (unsigned long long)bank->start,
 878                                (unsigned long long)bank->start + bank->size - 1);
 879                         continue;
 880                 }
 881
 882                 /*
 883                  * Check whether this memory bank would entirely overlap
 884                  * the vmalloc area.
 885                  */
 886                 if (__va(bank->start) >= vmalloc_min ||
 887                     __va(bank->start) < (void *)PAGE_OFFSET) {
 888                         printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
 889                                "(vmalloc region overlap).\n",
 890                                (unsigned long long)bank->start,
 891                                (unsigned long long)bank->start + bank->size - 1);
 892                         continue;
 893                 }
 894
 895                 /*
 896                  * Check whether this memory bank would partially overlap
 897                  * the vmalloc area.
 898                  */
 899                 if (__va(bank->start + bank->size) > vmalloc_min ||
 900                     __va(bank->start + bank->size) < __va(bank->start)) {
 901                         unsigned long newsize = vmalloc_min - __va(bank->start);
 902                         printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx "
 903                                "to -%.8llx (vmalloc region overlap).\n",
 904                                (unsigned long long)bank->start,
 905                                (unsigned long long)bank->start + bank->size - 1,
 906                                (unsigned long long)bank->start + newsize - 1);
 907                         bank->size = newsize;
 908                 }
 909 #endif
 910                 if (!bank->highmem && bank->start + bank->size > arm_lowmem_limit)
 911                         arm_lowmem_limit = bank->start + bank->size;
 912
 913                 j++;
 914         }
 915 #ifdef CONFIG_HIGHMEM
 916         if (highmem) {
 917                 const char *reason = NULL;
 918
 919                 if (cache_is_vipt_aliasing()) {
 920                         /*
 921                          * Interactions between kmap and other mappings
 922                          * make highmem support with aliasing VIPT caches
 923                          * rather difficult.
 924                          */
 925                         reason = "with VIPT aliasing cache";
 926                 }
 927                 if (reason) {
 928                         printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n",
 929                                 reason);
 930                         while (j > 0 && meminfo.bank[j - 1].highmem)
 931                                 j--;
 932                 }
 933         }
 934 #endif
 935         meminfo.nr_banks = j;
 936         high_memory = __va(arm_lowmem_limit - 1) + 1;
 937         memblock_set_current_limit(arm_lowmem_limit);
 938 }
 939
 940 static inline void prepare_page_table(void)
 941 {
 942         unsigned long addr;
 943         phys_addr_t end;
 944
 945         /*
 946          * Clear out all the mappings below the kernel image.
 947          */
 948         for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE)
 949                 pmd_clear(pmd_off_k(addr));
 950
 951 #ifdef CONFIG_XIP_KERNEL
 952         /* The XIP kernel is mapped in the module area -- skip over it */
 953         addr = ((unsigned long)_etext + PMD_SIZE - 1) & PMD_MASK;
 954 #endif
 955         for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE)
 956                 pmd_clear(pmd_off_k(addr));
 957
 958         /*
 959          * Find the end of the first block of lowmem.
 960          */
 961         end = memblock.memory.regions[0].base + memblock.memory.regions[0].size;
 962         if (end >= arm_lowmem_limit)
 963                 end = arm_lowmem_limit;
 964
 965         /*
 966          * Clear out all the kernel space mappings, except for the first
 967          * memory bank, up to the end of the vmalloc region.
 968          */
 969         for (addr = __phys_to_virt(end);
 970              addr < VMALLOC_END; addr += PMD_SIZE)
 971                 pmd_clear(pmd_off_k(addr));
 972 }
 973
 974 #ifdef CONFIG_ARM_LPAE
 975 /* the first page is reserved for pgd */
 976 #define SWAPPER_PG_DIR_SIZE     (PAGE_SIZE + \
 977                                  PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t))
 978 #else
 979 #define SWAPPER_PG_DIR_SIZE     (PTRS_PER_PGD * sizeof(pgd_t))
 980 #endif
 981
 982 /*
 983  * Reserve the special regions of memory
 984  */
 985 void __init arm_mm_memblock_reserve(void)
 986 {
 987         /*
 988          * Reserve the page tables.  These are already in use,
 989          * and can only be in node 0.
 990          */
 991         memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE);
 992
 993 #ifdef CONFIG_SA1111
 994         /*
 995          * Because of the SA1111 DMA bug, we want to preserve our
 996          * precious DMA-able memory...
 997          */
 998         memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
 999 #endif
1000 }
1001
1002 /*
1003  * Set up device the mappings.  Since we clear out the page tables for all
1004  * mappings above VMALLOC_END, we will remove any debug device mappings.
1005  * This means you have to be careful how you debug this function, or any
1006  * called function.  This means you can't use any function or debugging
1007  * method which may touch any device, otherwise the kernel _will_ crash.
1008  */
1009 static void __init devicemaps_init(struct machine_desc *mdesc)
1010 {
1011         struct map_desc map;
1012         unsigned long addr;
1013
1014         /*
1015          * Allocate the vector page early.
1016          */
1017         vectors_page = early_alloc(PAGE_SIZE);
1018
1019         for (addr = VMALLOC_END; addr; addr += PMD_SIZE)
1020                 pmd_clear(pmd_off_k(addr));
1021
1022         /*
1023          * Map the kernel if it is XIP.
1024          * It is always first in the modulearea.
1025          */
1026 #ifdef CONFIG_XIP_KERNEL
1027         map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
1028         map.virtual = MODULES_VADDR;
1029         map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK;
1030         map.type = MT_ROM;
1031         create_mapping(&map);
1032 #endif
1033
1034         /*
1035          * Map the cache flushing regions.
1036          */
1037 #ifdef FLUSH_BASE
1038         map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
1039         map.virtual = FLUSH_BASE;
1040         map.length = SZ_1M;
1041         map.type = MT_CACHECLEAN;
1042         create_mapping(&map);
1043 #endif
1044 #ifdef FLUSH_BASE_MINICACHE
1045         map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
1046         map.virtual = FLUSH_BASE_MINICACHE;
1047         map.length = SZ_1M;
1048         map.type = MT_MINICLEAN;
1049         create_mapping(&map);
1050 #endif
1051
1052         /*
1053          * Create a mapping for the machine vectors at the high-vectors
1054          * location (0xffff0000).  If we aren't using high-vectors, also
1055          * create a mapping at the low-vectors virtual address.
1056          */
1057         map.pfn = __phys_to_pfn(virt_to_phys(vectors_page));
1058         map.virtual = 0xffff0000;
1059         map.length = PAGE_SIZE;
1060         map.type = MT_HIGH_VECTORS;
1061         create_mapping(&map);
1062
1063         if (!vectors_high()) {
1064                 map.virtual = 0;
1065                 map.type = MT_LOW_VECTORS;
1066                 create_mapping(&map);
1067         }
1068
1069         /*
1070          * Ask the machine support to map in the statically mapped devices.
1071          */
1072         if (mdesc->map_io)
1073                 mdesc->map_io();
1074
1075         /*
1076          * Finally flush the caches and tlb to ensure that we're in a
1077          * consistent state wrt the writebuffer.  This also ensures that
1078          * any write-allocated cache lines in the vector page are written
1079          * back.  After this point, we can start to touch devices again.
1080          */
1081         local_flush_tlb_all();
1082         flush_cache_all();
1083 }
1084
1085 static void __init kmap_init(void)
1086 {
1087 #ifdef CONFIG_HIGHMEM
1088         pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE),
1089                 PKMAP_BASE, _PAGE_KERNEL_TABLE);
1090 #endif
1091 }
1092
1093 static void __init map_lowmem(void)
1094 {
1095         struct memblock_region *reg;
1096
1097         /* Map all the lowmem memory banks. */
1098         for_each_memblock(memory, reg) {
1099                 phys_addr_t start = reg->base;
1100                 phys_addr_t end = start + reg->size;
1101                 struct map_desc map;
1102
1103                 if (end > arm_lowmem_limit)
1104                         end = arm_lowmem_limit;
1105                 if (start >= end)
1106                         break;
1107
1108                 map.pfn = __phys_to_pfn(start);
1109                 map.virtual = __phys_to_virt(start);
1110                 map.length = end - start;
1111                 map.type = MT_MEMORY;
1112
1113                 create_mapping(&map);
1114         }
1115 }
1116
1117 /*
1118  * paging_init() sets up the page tables, initialises the zone memory
1119  * maps, and sets up the zero page, bad page and bad page tables.
1120  */
1121 void __init paging_init(struct machine_desc *mdesc)
1122 {
1123         void *zero_page;
1124
1125         memblock_set_current_limit(arm_lowmem_limit);
1126
1127         build_mem_type_table();
1128         prepare_page_table();
1129         map_lowmem();
1130         dma_contiguous_remap();
1131         devicemaps_init(mdesc);
1132         kmap_init();
1133
1134         top_pmd = pmd_off_k(0xffff0000);
1135
1136         /* allocate the zero page. */
1137         zero_page = early_alloc(PAGE_SIZE);
1138
1139         bootmem_init();
1140
1141         empty_zero_page = virt_to_page(zero_page);
1142         __flush_dcache_page(NULL, empty_zero_page);
1143 }