cabbc23a8917a29c2cc10c427153ad5fe36411f7
[pandora-kernel.git] / arch / arm / mm / mmu.c
1 /*
2  *  linux/arch/arm/mm/mmu.c
3  *
4  *  Copyright (C) 1995-2005 Russell King
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  */
10 #include <linux/module.h>
11 #include <linux/kernel.h>
12 #include <linux/errno.h>
13 #include <linux/init.h>
14 #include <linux/mman.h>
15 #include <linux/nodemask.h>
16 #include <linux/memblock.h>
17 #include <linux/fs.h>
18
19 #include <asm/cputype.h>
20 #include <asm/sections.h>
21 #include <asm/cachetype.h>
22 #include <asm/setup.h>
23 #include <asm/sizes.h>
24 #include <asm/smp_plat.h>
25 #include <asm/tlb.h>
26 #include <asm/highmem.h>
27 #include <asm/traps.h>
28
29 #include <asm/mach/arch.h>
30 #include <asm/mach/map.h>
31
32 #include "mm.h"
33
34 /*
35  * empty_zero_page is a special page that is used for
36  * zero-initialized data and COW.
37  */
38 struct page *empty_zero_page;
39 EXPORT_SYMBOL(empty_zero_page);
40
41 /*
42  * The pmd table for the upper-most set of pages.
43  */
44 pmd_t *top_pmd;
45
46 #define CPOLICY_UNCACHED        0
47 #define CPOLICY_BUFFERED        1
48 #define CPOLICY_WRITETHROUGH    2
49 #define CPOLICY_WRITEBACK       3
50 #define CPOLICY_WRITEALLOC      4
51
52 static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
53 static unsigned int ecc_mask __initdata = 0;
54 pgprot_t pgprot_user;
55 pgprot_t pgprot_kernel;
56
57 EXPORT_SYMBOL(pgprot_user);
58 EXPORT_SYMBOL(pgprot_kernel);
59
60 struct cachepolicy {
61         const char      policy[16];
62         unsigned int    cr_mask;
63         pmdval_t        pmd;
64         pteval_t        pte;
65 };
66
67 static struct cachepolicy cache_policies[] __initdata = {
68         {
69                 .policy         = "uncached",
70                 .cr_mask        = CR_W|CR_C,
71                 .pmd            = PMD_SECT_UNCACHED,
72                 .pte            = L_PTE_MT_UNCACHED,
73         }, {
74                 .policy         = "buffered",
75                 .cr_mask        = CR_C,
76                 .pmd            = PMD_SECT_BUFFERED,
77                 .pte            = L_PTE_MT_BUFFERABLE,
78         }, {
79                 .policy         = "writethrough",
80                 .cr_mask        = 0,
81                 .pmd            = PMD_SECT_WT,
82                 .pte            = L_PTE_MT_WRITETHROUGH,
83         }, {
84                 .policy         = "writeback",
85                 .cr_mask        = 0,
86                 .pmd            = PMD_SECT_WB,
87                 .pte            = L_PTE_MT_WRITEBACK,
88         }, {
89                 .policy         = "writealloc",
90                 .cr_mask        = 0,
91                 .pmd            = PMD_SECT_WBWA,
92                 .pte            = L_PTE_MT_WRITEALLOC,
93         }
94 };
95
96 /*
97  * These are useful for identifying cache coherency
98  * problems by allowing the cache or the cache and
99  * writebuffer to be turned off.  (Note: the write
100  * buffer should not be on and the cache off).
101  */
102 static int __init early_cachepolicy(char *p)
103 {
104         int i;
105
106         for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
107                 int len = strlen(cache_policies[i].policy);
108
109                 if (memcmp(p, cache_policies[i].policy, len) == 0) {
110                         cachepolicy = i;
111                         cr_alignment &= ~cache_policies[i].cr_mask;
112                         cr_no_alignment &= ~cache_policies[i].cr_mask;
113                         break;
114                 }
115         }
116         if (i == ARRAY_SIZE(cache_policies))
117                 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
118         /*
119          * This restriction is partly to do with the way we boot; it is
120          * unpredictable to have memory mapped using two different sets of
121          * memory attributes (shared, type, and cache attribs).  We can not
122          * change these attributes once the initial assembly has setup the
123          * page tables.
124          */
125         if (cpu_architecture() >= CPU_ARCH_ARMv6) {
126                 printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
127                 cachepolicy = CPOLICY_WRITEBACK;
128         }
129         flush_cache_all();
130         set_cr(cr_alignment);
131         return 0;
132 }
133 early_param("cachepolicy", early_cachepolicy);
134
135 static int __init early_nocache(char *__unused)
136 {
137         char *p = "buffered";
138         printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
139         early_cachepolicy(p);
140         return 0;
141 }
142 early_param("nocache", early_nocache);
143
144 static int __init early_nowrite(char *__unused)
145 {
146         char *p = "uncached";
147         printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
148         early_cachepolicy(p);
149         return 0;
150 }
151 early_param("nowb", early_nowrite);
152
153 #ifndef CONFIG_ARM_LPAE
154 static int __init early_ecc(char *p)
155 {
156         if (memcmp(p, "on", 2) == 0)
157                 ecc_mask = PMD_PROTECTION;
158         else if (memcmp(p, "off", 3) == 0)
159                 ecc_mask = 0;
160         return 0;
161 }
162 early_param("ecc", early_ecc);
163 #endif
164
165 static int __init noalign_setup(char *__unused)
166 {
167         cr_alignment &= ~CR_A;
168         cr_no_alignment &= ~CR_A;
169         set_cr(cr_alignment);
170         return 1;
171 }
172 __setup("noalign", noalign_setup);
173
174 #ifndef CONFIG_SMP
175 void adjust_cr(unsigned long mask, unsigned long set)
176 {
177         unsigned long flags;
178
179         mask &= ~CR_A;
180
181         set &= mask;
182
183         local_irq_save(flags);
184
185         cr_no_alignment = (cr_no_alignment & ~mask) | set;
186         cr_alignment = (cr_alignment & ~mask) | set;
187
188         set_cr((get_cr() & ~mask) | set);
189
190         local_irq_restore(flags);
191 }
192 #endif
193
194 #define PROT_PTE_DEVICE         L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
195 #define PROT_SECT_DEVICE        PMD_TYPE_SECT|PMD_SECT_AP_WRITE
196
197 static struct mem_type mem_types[] = {
198         [MT_DEVICE] = {           /* Strongly ordered / ARMv6 shared device */
199                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
200                                   L_PTE_SHARED,
201                 .prot_l1        = PMD_TYPE_TABLE,
202                 .prot_sect      = PROT_SECT_DEVICE | PMD_SECT_S,
203                 .domain         = DOMAIN_IO,
204         },
205         [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
206                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
207                 .prot_l1        = PMD_TYPE_TABLE,
208                 .prot_sect      = PROT_SECT_DEVICE,
209                 .domain         = DOMAIN_IO,
210         },
211         [MT_DEVICE_CACHED] = {    /* ioremap_cached */
212                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
213                 .prot_l1        = PMD_TYPE_TABLE,
214                 .prot_sect      = PROT_SECT_DEVICE | PMD_SECT_WB,
215                 .domain         = DOMAIN_IO,
216         },      
217         [MT_DEVICE_WC] = {      /* ioremap_wc */
218                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
219                 .prot_l1        = PMD_TYPE_TABLE,
220                 .prot_sect      = PROT_SECT_DEVICE,
221                 .domain         = DOMAIN_IO,
222         },
223         [MT_UNCACHED] = {
224                 .prot_pte       = PROT_PTE_DEVICE,
225                 .prot_l1        = PMD_TYPE_TABLE,
226                 .prot_sect      = PMD_TYPE_SECT | PMD_SECT_XN,
227                 .domain         = DOMAIN_IO,
228         },
229         [MT_CACHECLEAN] = {
230                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
231                 .domain    = DOMAIN_KERNEL,
232         },
233 #ifndef CONFIG_ARM_LPAE
234         [MT_MINICLEAN] = {
235                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
236                 .domain    = DOMAIN_KERNEL,
237         },
238 #endif
239         [MT_LOW_VECTORS] = {
240                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
241                                 L_PTE_RDONLY,
242                 .prot_l1   = PMD_TYPE_TABLE,
243                 .domain    = DOMAIN_USER,
244         },
245         [MT_HIGH_VECTORS] = {
246                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
247                                 L_PTE_USER | L_PTE_RDONLY,
248                 .prot_l1   = PMD_TYPE_TABLE,
249                 .domain    = DOMAIN_USER,
250         },
251         [MT_MEMORY] = {
252                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
253                 .prot_l1   = PMD_TYPE_TABLE,
254                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
255                 .domain    = DOMAIN_KERNEL,
256         },
257         [MT_ROM] = {
258                 .prot_sect = PMD_TYPE_SECT,
259                 .domain    = DOMAIN_KERNEL,
260         },
261         [MT_MEMORY_NONCACHED] = {
262                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
263                                 L_PTE_MT_BUFFERABLE,
264                 .prot_l1   = PMD_TYPE_TABLE,
265                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
266                 .domain    = DOMAIN_KERNEL,
267         },
268         [MT_MEMORY_DTCM] = {
269                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
270                                 L_PTE_XN,
271                 .prot_l1   = PMD_TYPE_TABLE,
272                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
273                 .domain    = DOMAIN_KERNEL,
274         },
275         [MT_MEMORY_ITCM] = {
276                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
277                 .prot_l1   = PMD_TYPE_TABLE,
278                 .domain    = DOMAIN_KERNEL,
279         },
280         [MT_MEMORY_SO] = {
281                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
282                                 L_PTE_MT_UNCACHED,
283                 .prot_l1   = PMD_TYPE_TABLE,
284                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S |
285                                 PMD_SECT_UNCACHED | PMD_SECT_XN,
286                 .domain    = DOMAIN_KERNEL,
287         },
288 };
289
290 const struct mem_type *get_mem_type(unsigned int type)
291 {
292         return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
293 }
294 EXPORT_SYMBOL(get_mem_type);
295
296 /*
297  * If the system supports huge pages and we are running with short descriptors,
298  * then compute the pmd and linux pte prot values for a huge page.
299  *
300  * These values are used by both the HugeTLB and THP code.
301  */
302 #if defined(CONFIG_SYS_SUPPORTS_HUGETLBFS) && !defined(CONFIG_ARM_LPAE)
303 pmdval_t arm_hugepmdprotval;
304 EXPORT_SYMBOL(arm_hugepmdprotval);
305
306 pteval_t arm_hugepteprotval;
307 EXPORT_SYMBOL(arm_hugepteprotval);
308 #endif
309
310
311 /*
312  * Adjust the PMD section entries according to the CPU in use.
313  */
314 static void __init build_mem_type_table(void)
315 {
316         struct cachepolicy *cp;
317         unsigned int cr = get_cr();
318         pteval_t user_pgprot, kern_pgprot, vecs_pgprot;
319         int cpu_arch = cpu_architecture();
320         int i;
321
322         if (cpu_arch < CPU_ARCH_ARMv6) {
323 #if defined(CONFIG_CPU_DCACHE_DISABLE)
324                 if (cachepolicy > CPOLICY_BUFFERED)
325                         cachepolicy = CPOLICY_BUFFERED;
326 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
327                 if (cachepolicy > CPOLICY_WRITETHROUGH)
328                         cachepolicy = CPOLICY_WRITETHROUGH;
329 #endif
330         }
331         if (cpu_arch < CPU_ARCH_ARMv5) {
332                 if (cachepolicy >= CPOLICY_WRITEALLOC)
333                         cachepolicy = CPOLICY_WRITEBACK;
334                 ecc_mask = 0;
335         }
336         if (is_smp())
337                 cachepolicy = CPOLICY_WRITEALLOC;
338
339         /*
340          * Strip out features not present on earlier architectures.
341          * Pre-ARMv5 CPUs don't have TEX bits.  Pre-ARMv6 CPUs or those
342          * without extended page tables don't have the 'Shared' bit.
343          */
344         if (cpu_arch < CPU_ARCH_ARMv5)
345                 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
346                         mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
347         if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
348                 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
349                         mem_types[i].prot_sect &= ~PMD_SECT_S;
350
351         /*
352          * ARMv5 and lower, bit 4 must be set for page tables (was: cache
353          * "update-able on write" bit on ARM610).  However, Xscale and
354          * Xscale3 require this bit to be cleared.
355          */
356         if (cpu_is_xscale() || cpu_is_xsc3()) {
357                 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
358                         mem_types[i].prot_sect &= ~PMD_BIT4;
359                         mem_types[i].prot_l1 &= ~PMD_BIT4;
360                 }
361         } else if (cpu_arch < CPU_ARCH_ARMv6) {
362                 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
363                         if (mem_types[i].prot_l1)
364                                 mem_types[i].prot_l1 |= PMD_BIT4;
365                         if (mem_types[i].prot_sect)
366                                 mem_types[i].prot_sect |= PMD_BIT4;
367                 }
368         }
369
370         /*
371          * Mark the device areas according to the CPU/architecture.
372          */
373         if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
374                 if (!cpu_is_xsc3()) {
375                         /*
376                          * Mark device regions on ARMv6+ as execute-never
377                          * to prevent speculative instruction fetches.
378                          */
379                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
380                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
381                         mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
382                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
383                 }
384                 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
385                         /*
386                          * For ARMv7 with TEX remapping,
387                          * - shared device is SXCB=1100
388                          * - nonshared device is SXCB=0100
389                          * - write combine device mem is SXCB=0001
390                          * (Uncached Normal memory)
391                          */
392                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
393                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
394                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
395                 } else if (cpu_is_xsc3()) {
396                         /*
397                          * For Xscale3,
398                          * - shared device is TEXCB=00101
399                          * - nonshared device is TEXCB=01000
400                          * - write combine device mem is TEXCB=00100
401                          * (Inner/Outer Uncacheable in xsc3 parlance)
402                          */
403                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
404                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
405                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
406                 } else {
407                         /*
408                          * For ARMv6 and ARMv7 without TEX remapping,
409                          * - shared device is TEXCB=00001
410                          * - nonshared device is TEXCB=01000
411                          * - write combine device mem is TEXCB=00100
412                          * (Uncached Normal in ARMv6 parlance).
413                          */
414                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
415                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
416                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
417                 }
418         } else {
419                 /*
420                  * On others, write combining is "Uncached/Buffered"
421                  */
422                 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
423         }
424
425         /*
426          * Now deal with the memory-type mappings
427          */
428         cp = &cache_policies[cachepolicy];
429         vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
430
431         /*
432          * Only use write-through for non-SMP systems
433          */
434         if (!is_smp() && cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH)
435                 vecs_pgprot = cache_policies[CPOLICY_WRITETHROUGH].pte;
436
437         /*
438          * Enable CPU-specific coherency if supported.
439          * (Only available on XSC3 at the moment.)
440          */
441         if (arch_is_coherent() && cpu_is_xsc3()) {
442                 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
443                 mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
444                 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
445                 mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
446         }
447         /*
448          * ARMv6 and above have extended page tables.
449          */
450         if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
451 #ifndef CONFIG_ARM_LPAE
452                 /*
453                  * Mark cache clean areas and XIP ROM read only
454                  * from SVC mode and no access from userspace.
455                  */
456                 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
457                 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
458                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
459 #endif
460
461                 if (is_smp()) {
462                         /*
463                          * Mark memory with the "shared" attribute
464                          * for SMP systems
465                          */
466                         user_pgprot |= L_PTE_SHARED;
467                         kern_pgprot |= L_PTE_SHARED;
468                         vecs_pgprot |= L_PTE_SHARED;
469                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
470                         mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
471                         mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
472                         mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
473                         mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
474                         mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
475                         mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
476                         mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
477                 }
478         }
479
480         /*
481          * Non-cacheable Normal - intended for memory areas that must
482          * not cause dirty cache line writebacks when used
483          */
484         if (cpu_arch >= CPU_ARCH_ARMv6) {
485                 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
486                         /* Non-cacheable Normal is XCB = 001 */
487                         mem_types[MT_MEMORY_NONCACHED].prot_sect |=
488                                 PMD_SECT_BUFFERED;
489                 } else {
490                         /* For both ARMv6 and non-TEX-remapping ARMv7 */
491                         mem_types[MT_MEMORY_NONCACHED].prot_sect |=
492                                 PMD_SECT_TEX(1);
493                 }
494         } else {
495                 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
496         }
497
498 #ifdef CONFIG_ARM_LPAE
499         /*
500          * Do not generate access flag faults for the kernel mappings.
501          */
502         for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
503                 mem_types[i].prot_pte |= PTE_EXT_AF;
504                 mem_types[i].prot_sect |= PMD_SECT_AF;
505         }
506         kern_pgprot |= PTE_EXT_AF;
507         vecs_pgprot |= PTE_EXT_AF;
508 #endif
509
510         for (i = 0; i < 16; i++) {
511                 pteval_t v = pgprot_val(protection_map[i]);
512                 protection_map[i] = __pgprot(v | user_pgprot);
513         }
514
515         mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
516         mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
517
518         pgprot_user   = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
519         pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
520                                  L_PTE_DIRTY | kern_pgprot);
521
522         mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
523         mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
524         mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
525         mem_types[MT_MEMORY].prot_pte |= kern_pgprot;
526         mem_types[MT_MEMORY_NONCACHED].prot_sect |= ecc_mask;
527         mem_types[MT_ROM].prot_sect |= cp->pmd;
528
529         switch (cp->pmd) {
530         case PMD_SECT_WT:
531                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
532                 break;
533         case PMD_SECT_WB:
534         case PMD_SECT_WBWA:
535                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
536                 break;
537         }
538         printk("Memory policy: ECC %sabled, Data cache %s\n",
539                 ecc_mask ? "en" : "dis", cp->policy);
540
541         for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
542                 struct mem_type *t = &mem_types[i];
543                 if (t->prot_l1)
544                         t->prot_l1 |= PMD_DOMAIN(t->domain);
545                 if (t->prot_sect)
546                         t->prot_sect |= PMD_DOMAIN(t->domain);
547         }
548
549 #if defined(CONFIG_SYS_SUPPORTS_HUGETLBFS) && !defined(CONFIG_ARM_LPAE)
550         /*
551          * we assume all huge pages are user pages and that hardware access
552          * flag updates are disabled (i.e. SCTLR.AFE == 0b).
553          */
554         arm_hugepteprotval = mem_types[MT_MEMORY].prot_pte | L_PTE_USER | L_PTE_VALID;
555
556         arm_hugepmdprotval = mem_types[MT_MEMORY].prot_sect | PMD_SECT_AP_READ
557                                 | PMD_SECT_nG;
558 #endif
559
560 }
561
562 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
563 pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
564                               unsigned long size, pgprot_t vma_prot)
565 {
566         if (!pfn_valid(pfn))
567                 return pgprot_noncached(vma_prot);
568         else if (file->f_flags & O_SYNC)
569                 return pgprot_writecombine(vma_prot);
570         return vma_prot;
571 }
572 EXPORT_SYMBOL(phys_mem_access_prot);
573 #endif
574
575 #define vectors_base()  (vectors_high() ? 0xffff0000 : 0)
576
577 static void __init *early_alloc(unsigned long sz)
578 {
579         void *ptr = __va(memblock_alloc(sz, sz));
580         memset(ptr, 0, sz);
581         return ptr;
582 }
583
584 static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot)
585 {
586         if (pmd_none(*pmd)) {
587                 pte_t *pte = early_alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE);
588                 __pmd_populate(pmd, __pa(pte), prot);
589         }
590         BUG_ON(pmd_bad(*pmd));
591         return pte_offset_kernel(pmd, addr);
592 }
593
594 static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
595                                   unsigned long end, unsigned long pfn,
596                                   const struct mem_type *type)
597 {
598         pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1);
599         do {
600                 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0);
601                 pfn++;
602         } while (pte++, addr += PAGE_SIZE, addr != end);
603 }
604
605 static void __init alloc_init_section(pud_t *pud, unsigned long addr,
606                                       unsigned long end, phys_addr_t phys,
607                                       const struct mem_type *type)
608 {
609         pmd_t *pmd = pmd_offset(pud, addr);
610
611         /*
612          * Try a section mapping - end, addr and phys must all be aligned
613          * to a section boundary.  Note that PMDs refer to the individual
614          * L1 entries, whereas PGDs refer to a group of L1 entries making
615          * up one logical pointer to an L2 table.
616          */
617         if (((addr | end | phys) & ~SECTION_MASK) == 0) {
618                 pmd_t *p = pmd;
619
620 #ifndef CONFIG_ARM_LPAE
621                 if (addr & SECTION_SIZE)
622                         pmd++;
623 #endif
624
625                 do {
626                         *pmd = __pmd(phys | type->prot_sect);
627                         phys += SECTION_SIZE;
628                 } while (pmd++, addr += SECTION_SIZE, addr != end);
629
630                 flush_pmd_entry(p);
631         } else {
632                 /*
633                  * No need to loop; pte's aren't interested in the
634                  * individual L1 entries.
635                  */
636                 alloc_init_pte(pmd, addr, end, __phys_to_pfn(phys), type);
637         }
638 }
639
640 static void alloc_init_pud(pgd_t *pgd, unsigned long addr, unsigned long end,
641         unsigned long phys, const struct mem_type *type)
642 {
643         pud_t *pud = pud_offset(pgd, addr);
644         unsigned long next;
645
646         do {
647                 next = pud_addr_end(addr, end);
648                 alloc_init_section(pud, addr, next, phys, type);
649                 phys += next - addr;
650         } while (pud++, addr = next, addr != end);
651 }
652
653 #ifndef CONFIG_ARM_LPAE
654 static void __init create_36bit_mapping(struct map_desc *md,
655                                         const struct mem_type *type)
656 {
657         unsigned long addr, length, end;
658         phys_addr_t phys;
659         pgd_t *pgd;
660
661         addr = md->virtual;
662         phys = __pfn_to_phys(md->pfn);
663         length = PAGE_ALIGN(md->length);
664
665         if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
666                 printk(KERN_ERR "MM: CPU does not support supersection "
667                        "mapping for 0x%08llx at 0x%08lx\n",
668                        (long long)__pfn_to_phys((u64)md->pfn), addr);
669                 return;
670         }
671
672         /* N.B. ARMv6 supersections are only defined to work with domain 0.
673          *      Since domain assignments can in fact be arbitrary, the
674          *      'domain == 0' check below is required to insure that ARMv6
675          *      supersections are only allocated for domain 0 regardless
676          *      of the actual domain assignments in use.
677          */
678         if (type->domain) {
679                 printk(KERN_ERR "MM: invalid domain in supersection "
680                        "mapping for 0x%08llx at 0x%08lx\n",
681                        (long long)__pfn_to_phys((u64)md->pfn), addr);
682                 return;
683         }
684
685         if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
686                 printk(KERN_ERR "MM: cannot create mapping for 0x%08llx"
687                        " at 0x%08lx invalid alignment\n",
688                        (long long)__pfn_to_phys((u64)md->pfn), addr);
689                 return;
690         }
691
692         /*
693          * Shift bits [35:32] of address into bits [23:20] of PMD
694          * (See ARMv6 spec).
695          */
696         phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
697
698         pgd = pgd_offset_k(addr);
699         end = addr + length;
700         do {
701                 pud_t *pud = pud_offset(pgd, addr);
702                 pmd_t *pmd = pmd_offset(pud, addr);
703                 int i;
704
705                 for (i = 0; i < 16; i++)
706                         *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER);
707
708                 addr += SUPERSECTION_SIZE;
709                 phys += SUPERSECTION_SIZE;
710                 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
711         } while (addr != end);
712 }
713 #endif  /* !CONFIG_ARM_LPAE */
714
715 /*
716  * Create the page directory entries and any necessary
717  * page tables for the mapping specified by `md'.  We
718  * are able to cope here with varying sizes and address
719  * offsets, and we take full advantage of sections and
720  * supersections.
721  */
722 static void __init create_mapping(struct map_desc *md)
723 {
724         unsigned long addr, length, end;
725         phys_addr_t phys;
726         const struct mem_type *type;
727         pgd_t *pgd;
728
729         if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
730                 printk(KERN_WARNING "BUG: not creating mapping for 0x%08llx"
731                        " at 0x%08lx in user region\n",
732                        (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
733                 return;
734         }
735
736         if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
737             md->virtual >= PAGE_OFFSET && md->virtual < VMALLOC_END) {
738                 printk(KERN_WARNING "BUG: mapping for 0x%08llx"
739                        " at 0x%08lx overlaps vmalloc space\n",
740                        (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
741         }
742
743         type = &mem_types[md->type];
744
745 #ifndef CONFIG_ARM_LPAE
746         /*
747          * Catch 36-bit addresses
748          */
749         if (md->pfn >= 0x100000) {
750                 create_36bit_mapping(md, type);
751                 return;
752         }
753 #endif
754
755         addr = md->virtual & PAGE_MASK;
756         phys = __pfn_to_phys(md->pfn);
757         length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
758
759         if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
760                 printk(KERN_WARNING "BUG: map for 0x%08llx at 0x%08lx can not "
761                        "be mapped using pages, ignoring.\n",
762                        (long long)__pfn_to_phys(md->pfn), addr);
763                 return;
764         }
765
766         pgd = pgd_offset_k(addr);
767         end = addr + length;
768         do {
769                 unsigned long next = pgd_addr_end(addr, end);
770
771                 alloc_init_pud(pgd, addr, next, phys, type);
772
773                 phys += next - addr;
774                 addr = next;
775         } while (pgd++, addr != end);
776 }
777
778 /*
779  * Create the architecture specific mappings
780  */
781 void __init iotable_init(struct map_desc *io_desc, int nr)
782 {
783         int i;
784
785         for (i = 0; i < nr; i++)
786                 create_mapping(io_desc + i);
787 }
788
789 static void * __initdata vmalloc_min = (void *)(VMALLOC_END - SZ_128M);
790
791 /*
792  * vmalloc=size forces the vmalloc area to be exactly 'size'
793  * bytes. This can be used to increase (or decrease) the vmalloc
794  * area - the default is 128m.
795  */
796 static int __init early_vmalloc(char *arg)
797 {
798         unsigned long vmalloc_reserve = memparse(arg, NULL);
799
800         if (vmalloc_reserve < SZ_16M) {
801                 vmalloc_reserve = SZ_16M;
802                 printk(KERN_WARNING
803                         "vmalloc area too small, limiting to %luMB\n",
804                         vmalloc_reserve >> 20);
805         }
806
807         if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) {
808                 vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M);
809                 printk(KERN_WARNING
810                         "vmalloc area is too big, limiting to %luMB\n",
811                         vmalloc_reserve >> 20);
812         }
813
814         vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve);
815         return 0;
816 }
817 early_param("vmalloc", early_vmalloc);
818
819 static phys_addr_t lowmem_limit __initdata = 0;
820
821 void __init sanity_check_meminfo(void)
822 {
823         int i, j, highmem = 0;
824
825         for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
826                 struct membank *bank = &meminfo.bank[j];
827                 *bank = meminfo.bank[i];
828
829                 if (bank->start > ULONG_MAX)
830                         highmem = 1;
831
832 #ifdef CONFIG_HIGHMEM
833                 if (__va(bank->start) >= vmalloc_min ||
834                     __va(bank->start) < (void *)PAGE_OFFSET)
835                         highmem = 1;
836
837                 bank->highmem = highmem;
838
839                 /*
840                  * Split those memory banks which are partially overlapping
841                  * the vmalloc area greatly simplifying things later.
842                  */
843                 if (!highmem && __va(bank->start) < vmalloc_min &&
844                     bank->size > vmalloc_min - __va(bank->start)) {
845                         if (meminfo.nr_banks >= NR_BANKS) {
846                                 printk(KERN_CRIT "NR_BANKS too low, "
847                                                  "ignoring high memory\n");
848                         } else {
849                                 memmove(bank + 1, bank,
850                                         (meminfo.nr_banks - i) * sizeof(*bank));
851                                 meminfo.nr_banks++;
852                                 i++;
853                                 bank[1].size -= vmalloc_min - __va(bank->start);
854                                 bank[1].start = __pa(vmalloc_min - 1) + 1;
855                                 bank[1].highmem = highmem = 1;
856                                 j++;
857                         }
858                         bank->size = vmalloc_min - __va(bank->start);
859                 }
860 #else
861                 bank->highmem = highmem;
862
863                 /*
864                  * Highmem banks not allowed with !CONFIG_HIGHMEM.
865                  */
866                 if (highmem) {
867                         printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
868                                "(!CONFIG_HIGHMEM).\n",
869                                (unsigned long long)bank->start,
870                                (unsigned long long)bank->start + bank->size - 1);
871                         continue;
872                 }
873
874                 /*
875                  * Check whether this memory bank would entirely overlap
876                  * the vmalloc area.
877                  */
878                 if (__va(bank->start) >= vmalloc_min ||
879                     __va(bank->start) < (void *)PAGE_OFFSET) {
880                         printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
881                                "(vmalloc region overlap).\n",
882                                (unsigned long long)bank->start,
883                                (unsigned long long)bank->start + bank->size - 1);
884                         continue;
885                 }
886
887                 /*
888                  * Check whether this memory bank would partially overlap
889                  * the vmalloc area.
890                  */
891                 if (__va(bank->start + bank->size) > vmalloc_min ||
892                     __va(bank->start + bank->size) < __va(bank->start)) {
893                         unsigned long newsize = vmalloc_min - __va(bank->start);
894                         printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx "
895                                "to -%.8llx (vmalloc region overlap).\n",
896                                (unsigned long long)bank->start,
897                                (unsigned long long)bank->start + bank->size - 1,
898                                (unsigned long long)bank->start + newsize - 1);
899                         bank->size = newsize;
900                 }
901 #endif
902                 if (!bank->highmem && bank->start + bank->size > lowmem_limit)
903                         lowmem_limit = bank->start + bank->size;
904
905                 j++;
906         }
907 #ifdef CONFIG_HIGHMEM
908         if (highmem) {
909                 const char *reason = NULL;
910
911                 if (cache_is_vipt_aliasing()) {
912                         /*
913                          * Interactions between kmap and other mappings
914                          * make highmem support with aliasing VIPT caches
915                          * rather difficult.
916                          */
917                         reason = "with VIPT aliasing cache";
918                 }
919                 if (reason) {
920                         printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n",
921                                 reason);
922                         while (j > 0 && meminfo.bank[j - 1].highmem)
923                                 j--;
924                 }
925         }
926 #endif
927         meminfo.nr_banks = j;
928         high_memory = __va(lowmem_limit - 1) + 1;
929         memblock_set_current_limit(lowmem_limit);
930 }
931
932 static inline void prepare_page_table(void)
933 {
934         unsigned long addr;
935         phys_addr_t end;
936
937         /*
938          * Clear out all the mappings below the kernel image.
939          */
940         for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE)
941                 pmd_clear(pmd_off_k(addr));
942
943 #ifdef CONFIG_XIP_KERNEL
944         /* The XIP kernel is mapped in the module area -- skip over it */
945         addr = ((unsigned long)_etext + PMD_SIZE - 1) & PMD_MASK;
946 #endif
947         for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE)
948                 pmd_clear(pmd_off_k(addr));
949
950         /*
951          * Find the end of the first block of lowmem.
952          */
953         end = memblock.memory.regions[0].base + memblock.memory.regions[0].size;
954         if (end >= lowmem_limit)
955                 end = lowmem_limit;
956
957         /*
958          * Clear out all the kernel space mappings, except for the first
959          * memory bank, up to the end of the vmalloc region.
960          */
961         for (addr = __phys_to_virt(end);
962              addr < VMALLOC_END; addr += PMD_SIZE)
963                 pmd_clear(pmd_off_k(addr));
964 }
965
966 #ifdef CONFIG_ARM_LPAE
967 /* the first page is reserved for pgd */
968 #define SWAPPER_PG_DIR_SIZE     (PAGE_SIZE + \
969                                  PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t))
970 #else
971 #define SWAPPER_PG_DIR_SIZE     (PTRS_PER_PGD * sizeof(pgd_t))
972 #endif
973
974 /*
975  * Reserve the special regions of memory
976  */
977 void __init arm_mm_memblock_reserve(void)
978 {
979         /*
980          * Reserve the page tables.  These are already in use,
981          * and can only be in node 0.
982          */
983         memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE);
984
985 #ifdef CONFIG_SA1111
986         /*
987          * Because of the SA1111 DMA bug, we want to preserve our
988          * precious DMA-able memory...
989          */
990         memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
991 #endif
992 }
993
994 /*
995  * Set up device the mappings.  Since we clear out the page tables for all
996  * mappings above VMALLOC_END, we will remove any debug device mappings.
997  * This means you have to be careful how you debug this function, or any
998  * called function.  This means you can't use any function or debugging
999  * method which may touch any device, otherwise the kernel _will_ crash.
1000  */
1001 static void __init devicemaps_init(struct machine_desc *mdesc)
1002 {
1003         struct map_desc map;
1004         unsigned long addr;
1005
1006         /*
1007          * Allocate the vector page early.
1008          */
1009         vectors_page = early_alloc(PAGE_SIZE);
1010
1011         for (addr = VMALLOC_END; addr; addr += PMD_SIZE)
1012                 pmd_clear(pmd_off_k(addr));
1013
1014         /*
1015          * Map the kernel if it is XIP.
1016          * It is always first in the modulearea.
1017          */
1018 #ifdef CONFIG_XIP_KERNEL
1019         map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
1020         map.virtual = MODULES_VADDR;
1021         map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK;
1022         map.type = MT_ROM;
1023         create_mapping(&map);
1024 #endif
1025
1026         /*
1027          * Map the cache flushing regions.
1028          */
1029 #ifdef FLUSH_BASE
1030         map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
1031         map.virtual = FLUSH_BASE;
1032         map.length = SZ_1M;
1033         map.type = MT_CACHECLEAN;
1034         create_mapping(&map);
1035 #endif
1036 #ifdef FLUSH_BASE_MINICACHE
1037         map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
1038         map.virtual = FLUSH_BASE_MINICACHE;
1039         map.length = SZ_1M;
1040         map.type = MT_MINICLEAN;
1041         create_mapping(&map);
1042 #endif
1043
1044         /*
1045          * Create a mapping for the machine vectors at the high-vectors
1046          * location (0xffff0000).  If we aren't using high-vectors, also
1047          * create a mapping at the low-vectors virtual address.
1048          */
1049         map.pfn = __phys_to_pfn(virt_to_phys(vectors_page));
1050         map.virtual = 0xffff0000;
1051         map.length = PAGE_SIZE;
1052         map.type = MT_HIGH_VECTORS;
1053         create_mapping(&map);
1054
1055         if (!vectors_high()) {
1056                 map.virtual = 0;
1057                 map.type = MT_LOW_VECTORS;
1058                 create_mapping(&map);
1059         }
1060
1061         /*
1062          * Ask the machine support to map in the statically mapped devices.
1063          */
1064         if (mdesc->map_io)
1065                 mdesc->map_io();
1066
1067         /*
1068          * Finally flush the caches and tlb to ensure that we're in a
1069          * consistent state wrt the writebuffer.  This also ensures that
1070          * any write-allocated cache lines in the vector page are written
1071          * back.  After this point, we can start to touch devices again.
1072          */
1073         local_flush_tlb_all();
1074         flush_cache_all();
1075 }
1076
1077 static void __init kmap_init(void)
1078 {
1079 #ifdef CONFIG_HIGHMEM
1080         pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE),
1081                 PKMAP_BASE, _PAGE_KERNEL_TABLE);
1082 #endif
1083 }
1084
1085 static void __init map_lowmem(void)
1086 {
1087         struct memblock_region *reg;
1088
1089         /* Map all the lowmem memory banks. */
1090         for_each_memblock(memory, reg) {
1091                 phys_addr_t start = reg->base;
1092                 phys_addr_t end = start + reg->size;
1093                 struct map_desc map;
1094
1095                 if (end > lowmem_limit)
1096                         end = lowmem_limit;
1097                 if (start >= end)
1098                         break;
1099
1100                 map.pfn = __phys_to_pfn(start);
1101                 map.virtual = __phys_to_virt(start);
1102                 map.length = end - start;
1103                 map.type = MT_MEMORY;
1104
1105                 create_mapping(&map);
1106         }
1107 }
1108
1109 /*
1110  * paging_init() sets up the page tables, initialises the zone memory
1111  * maps, and sets up the zero page, bad page and bad page tables.
1112  */
1113 void __init paging_init(struct machine_desc *mdesc)
1114 {
1115         void *zero_page;
1116
1117         memblock_set_current_limit(lowmem_limit);
1118
1119         build_mem_type_table();
1120         prepare_page_table();
1121         map_lowmem();
1122         devicemaps_init(mdesc);
1123         kmap_init();
1124
1125         top_pmd = pmd_off_k(0xffff0000);
1126
1127         /* allocate the zero page. */
1128         zero_page = early_alloc(PAGE_SIZE);
1129
1130         bootmem_init();
1131
1132         empty_zero_page = virt_to_page(zero_page);
1133         __flush_dcache_page(NULL, empty_zero_page);
1134 }