2 * linux/arch/arm/mm/mmu.c
4 * Copyright (C) 1995-2005 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #include <linux/module.h>
11 #include <linux/kernel.h>
12 #include <linux/errno.h>
13 #include <linux/init.h>
14 #include <linux/mman.h>
15 #include <linux/nodemask.h>
16 #include <linux/memblock.h>
19 #include <asm/cputype.h>
20 #include <asm/sections.h>
21 #include <asm/cachetype.h>
22 #include <asm/setup.h>
23 #include <asm/sizes.h>
24 #include <asm/smp_plat.h>
26 #include <asm/highmem.h>
27 #include <asm/traps.h>
29 #include <asm/mach/arch.h>
30 #include <asm/mach/map.h>
34 DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
37 * empty_zero_page is a special page that is used for
38 * zero-initialized data and COW.
40 struct page *empty_zero_page;
41 EXPORT_SYMBOL(empty_zero_page);
44 * The pmd table for the upper-most set of pages.
48 #define CPOLICY_UNCACHED 0
49 #define CPOLICY_BUFFERED 1
50 #define CPOLICY_WRITETHROUGH 2
51 #define CPOLICY_WRITEBACK 3
52 #define CPOLICY_WRITEALLOC 4
54 static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
55 static unsigned int ecc_mask __initdata = 0;
57 pgprot_t pgprot_kernel;
59 EXPORT_SYMBOL(pgprot_user);
60 EXPORT_SYMBOL(pgprot_kernel);
63 const char policy[16];
69 static struct cachepolicy cache_policies[] __initdata = {
73 .pmd = PMD_SECT_UNCACHED,
74 .pte = L_PTE_MT_UNCACHED,
78 .pmd = PMD_SECT_BUFFERED,
79 .pte = L_PTE_MT_BUFFERABLE,
81 .policy = "writethrough",
84 .pte = L_PTE_MT_WRITETHROUGH,
86 .policy = "writeback",
89 .pte = L_PTE_MT_WRITEBACK,
91 .policy = "writealloc",
94 .pte = L_PTE_MT_WRITEALLOC,
99 * These are useful for identifying cache coherency
100 * problems by allowing the cache or the cache and
101 * writebuffer to be turned off. (Note: the write
102 * buffer should not be on and the cache off).
104 static int __init early_cachepolicy(char *p)
108 for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
109 int len = strlen(cache_policies[i].policy);
111 if (memcmp(p, cache_policies[i].policy, len) == 0) {
113 cr_alignment &= ~cache_policies[i].cr_mask;
114 cr_no_alignment &= ~cache_policies[i].cr_mask;
118 if (i == ARRAY_SIZE(cache_policies))
119 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
121 * This restriction is partly to do with the way we boot; it is
122 * unpredictable to have memory mapped using two different sets of
123 * memory attributes (shared, type, and cache attribs). We can not
124 * change these attributes once the initial assembly has setup the
127 if (cpu_architecture() >= CPU_ARCH_ARMv6) {
128 printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
129 cachepolicy = CPOLICY_WRITEBACK;
132 set_cr(cr_alignment);
135 early_param("cachepolicy", early_cachepolicy);
137 static int __init early_nocache(char *__unused)
139 char *p = "buffered";
140 printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
141 early_cachepolicy(p);
144 early_param("nocache", early_nocache);
146 static int __init early_nowrite(char *__unused)
148 char *p = "uncached";
149 printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
150 early_cachepolicy(p);
153 early_param("nowb", early_nowrite);
155 static int __init early_ecc(char *p)
157 if (memcmp(p, "on", 2) == 0)
158 ecc_mask = PMD_PROTECTION;
159 else if (memcmp(p, "off", 3) == 0)
163 early_param("ecc", early_ecc);
165 static int __init noalign_setup(char *__unused)
167 cr_alignment &= ~CR_A;
168 cr_no_alignment &= ~CR_A;
169 set_cr(cr_alignment);
172 __setup("noalign", noalign_setup);
175 void adjust_cr(unsigned long mask, unsigned long set)
183 local_irq_save(flags);
185 cr_no_alignment = (cr_no_alignment & ~mask) | set;
186 cr_alignment = (cr_alignment & ~mask) | set;
188 set_cr((get_cr() & ~mask) | set);
190 local_irq_restore(flags);
194 #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
195 #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE
197 static struct mem_type mem_types[] = {
198 [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */
199 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
201 .prot_l1 = PMD_TYPE_TABLE,
202 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S,
205 [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
206 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
207 .prot_l1 = PMD_TYPE_TABLE,
208 .prot_sect = PROT_SECT_DEVICE,
211 [MT_DEVICE_CACHED] = { /* ioremap_cached */
212 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
213 .prot_l1 = PMD_TYPE_TABLE,
214 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB,
217 [MT_DEVICE_WC] = { /* ioremap_wc */
218 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
219 .prot_l1 = PMD_TYPE_TABLE,
220 .prot_sect = PROT_SECT_DEVICE,
224 .prot_pte = PROT_PTE_DEVICE,
225 .prot_l1 = PMD_TYPE_TABLE,
226 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
230 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
231 .domain = DOMAIN_KERNEL,
234 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
235 .domain = DOMAIN_KERNEL,
238 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
240 .prot_l1 = PMD_TYPE_TABLE,
241 .domain = DOMAIN_USER,
243 [MT_HIGH_VECTORS] = {
244 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
245 L_PTE_USER | L_PTE_RDONLY,
246 .prot_l1 = PMD_TYPE_TABLE,
247 .domain = DOMAIN_USER,
250 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
251 .prot_l1 = PMD_TYPE_TABLE,
252 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
253 .domain = DOMAIN_KERNEL,
256 .prot_sect = PMD_TYPE_SECT,
257 .domain = DOMAIN_KERNEL,
259 [MT_MEMORY_NONCACHED] = {
260 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
262 .prot_l1 = PMD_TYPE_TABLE,
263 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
264 .domain = DOMAIN_KERNEL,
267 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
269 .prot_l1 = PMD_TYPE_TABLE,
270 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
271 .domain = DOMAIN_KERNEL,
274 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
275 .prot_l1 = PMD_TYPE_TABLE,
276 .domain = DOMAIN_KERNEL,
280 const struct mem_type *get_mem_type(unsigned int type)
282 return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
284 EXPORT_SYMBOL(get_mem_type);
287 * Adjust the PMD section entries according to the CPU in use.
289 static void __init build_mem_type_table(void)
291 struct cachepolicy *cp;
292 unsigned int cr = get_cr();
293 unsigned int user_pgprot, kern_pgprot, vecs_pgprot;
294 int cpu_arch = cpu_architecture();
297 if (cpu_arch < CPU_ARCH_ARMv6) {
298 #if defined(CONFIG_CPU_DCACHE_DISABLE)
299 if (cachepolicy > CPOLICY_BUFFERED)
300 cachepolicy = CPOLICY_BUFFERED;
301 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
302 if (cachepolicy > CPOLICY_WRITETHROUGH)
303 cachepolicy = CPOLICY_WRITETHROUGH;
306 if (cpu_arch < CPU_ARCH_ARMv5) {
307 if (cachepolicy >= CPOLICY_WRITEALLOC)
308 cachepolicy = CPOLICY_WRITEBACK;
312 cachepolicy = CPOLICY_WRITEALLOC;
315 * Strip out features not present on earlier architectures.
316 * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those
317 * without extended page tables don't have the 'Shared' bit.
319 if (cpu_arch < CPU_ARCH_ARMv5)
320 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
321 mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
322 if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
323 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
324 mem_types[i].prot_sect &= ~PMD_SECT_S;
327 * ARMv5 and lower, bit 4 must be set for page tables (was: cache
328 * "update-able on write" bit on ARM610). However, Xscale and
329 * Xscale3 require this bit to be cleared.
331 if (cpu_is_xscale() || cpu_is_xsc3()) {
332 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
333 mem_types[i].prot_sect &= ~PMD_BIT4;
334 mem_types[i].prot_l1 &= ~PMD_BIT4;
336 } else if (cpu_arch < CPU_ARCH_ARMv6) {
337 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
338 if (mem_types[i].prot_l1)
339 mem_types[i].prot_l1 |= PMD_BIT4;
340 if (mem_types[i].prot_sect)
341 mem_types[i].prot_sect |= PMD_BIT4;
346 * Mark the device areas according to the CPU/architecture.
348 if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
349 if (!cpu_is_xsc3()) {
351 * Mark device regions on ARMv6+ as execute-never
352 * to prevent speculative instruction fetches.
354 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
355 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
356 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
357 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
359 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
361 * For ARMv7 with TEX remapping,
362 * - shared device is SXCB=1100
363 * - nonshared device is SXCB=0100
364 * - write combine device mem is SXCB=0001
365 * (Uncached Normal memory)
367 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
368 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
369 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
370 } else if (cpu_is_xsc3()) {
373 * - shared device is TEXCB=00101
374 * - nonshared device is TEXCB=01000
375 * - write combine device mem is TEXCB=00100
376 * (Inner/Outer Uncacheable in xsc3 parlance)
378 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
379 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
380 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
383 * For ARMv6 and ARMv7 without TEX remapping,
384 * - shared device is TEXCB=00001
385 * - nonshared device is TEXCB=01000
386 * - write combine device mem is TEXCB=00100
387 * (Uncached Normal in ARMv6 parlance).
389 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
390 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
391 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
395 * On others, write combining is "Uncached/Buffered"
397 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
401 * Now deal with the memory-type mappings
403 cp = &cache_policies[cachepolicy];
404 vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
407 * Only use write-through for non-SMP systems
409 if (!is_smp() && cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH)
410 vecs_pgprot = cache_policies[CPOLICY_WRITETHROUGH].pte;
413 * Enable CPU-specific coherency if supported.
414 * (Only available on XSC3 at the moment.)
416 if (arch_is_coherent() && cpu_is_xsc3()) {
417 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
418 mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
419 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
420 mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
423 * ARMv6 and above have extended page tables.
425 if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
427 * Mark cache clean areas and XIP ROM read only
428 * from SVC mode and no access from userspace.
430 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
431 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
432 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
436 * Mark memory with the "shared" attribute
439 user_pgprot |= L_PTE_SHARED;
440 kern_pgprot |= L_PTE_SHARED;
441 vecs_pgprot |= L_PTE_SHARED;
442 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
443 mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
444 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
445 mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
446 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
447 mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
448 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
449 mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
454 * Non-cacheable Normal - intended for memory areas that must
455 * not cause dirty cache line writebacks when used
457 if (cpu_arch >= CPU_ARCH_ARMv6) {
458 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
459 /* Non-cacheable Normal is XCB = 001 */
460 mem_types[MT_MEMORY_NONCACHED].prot_sect |=
463 /* For both ARMv6 and non-TEX-remapping ARMv7 */
464 mem_types[MT_MEMORY_NONCACHED].prot_sect |=
468 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
471 for (i = 0; i < 16; i++) {
472 unsigned long v = pgprot_val(protection_map[i]);
473 protection_map[i] = __pgprot(v | user_pgprot);
476 mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
477 mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
479 pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
480 pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
481 L_PTE_DIRTY | kern_pgprot);
483 mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
484 mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
485 mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
486 mem_types[MT_MEMORY].prot_pte |= kern_pgprot;
487 mem_types[MT_MEMORY_NONCACHED].prot_sect |= ecc_mask;
488 mem_types[MT_ROM].prot_sect |= cp->pmd;
492 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
496 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
499 printk("Memory policy: ECC %sabled, Data cache %s\n",
500 ecc_mask ? "en" : "dis", cp->policy);
502 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
503 struct mem_type *t = &mem_types[i];
505 t->prot_l1 |= PMD_DOMAIN(t->domain);
507 t->prot_sect |= PMD_DOMAIN(t->domain);
511 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
512 pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
513 unsigned long size, pgprot_t vma_prot)
516 return pgprot_noncached(vma_prot);
517 else if (file->f_flags & O_SYNC)
518 return pgprot_writecombine(vma_prot);
521 EXPORT_SYMBOL(phys_mem_access_prot);
524 #define vectors_base() (vectors_high() ? 0xffff0000 : 0)
526 static void __init *early_alloc(unsigned long sz)
528 void *ptr = __va(memblock_alloc(sz, sz));
533 static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot)
535 if (pmd_none(*pmd)) {
536 pte_t *pte = early_alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE);
537 __pmd_populate(pmd, __pa(pte), prot);
539 BUG_ON(pmd_bad(*pmd));
540 return pte_offset_kernel(pmd, addr);
543 static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
544 unsigned long end, unsigned long pfn,
545 const struct mem_type *type)
547 pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1);
549 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0);
551 } while (pte++, addr += PAGE_SIZE, addr != end);
554 static void __init alloc_init_section(pud_t *pud, unsigned long addr,
555 unsigned long end, phys_addr_t phys,
556 const struct mem_type *type)
558 pmd_t *pmd = pmd_offset(pud, addr);
561 * Try a section mapping - end, addr and phys must all be aligned
562 * to a section boundary. Note that PMDs refer to the individual
563 * L1 entries, whereas PGDs refer to a group of L1 entries making
564 * up one logical pointer to an L2 table.
566 if (((addr | end | phys) & ~SECTION_MASK) == 0) {
569 if (addr & SECTION_SIZE)
573 *pmd = __pmd(phys | type->prot_sect);
574 phys += SECTION_SIZE;
575 } while (pmd++, addr += SECTION_SIZE, addr != end);
580 * No need to loop; pte's aren't interested in the
581 * individual L1 entries.
583 alloc_init_pte(pmd, addr, end, __phys_to_pfn(phys), type);
587 static void alloc_init_pud(pgd_t *pgd, unsigned long addr, unsigned long end,
588 unsigned long phys, const struct mem_type *type)
590 pud_t *pud = pud_offset(pgd, addr);
594 next = pud_addr_end(addr, end);
595 alloc_init_section(pud, addr, next, phys, type);
597 } while (pud++, addr = next, addr != end);
600 static void __init create_36bit_mapping(struct map_desc *md,
601 const struct mem_type *type)
603 unsigned long addr, length, end;
608 phys = __pfn_to_phys(md->pfn);
609 length = PAGE_ALIGN(md->length);
611 if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
612 printk(KERN_ERR "MM: CPU does not support supersection "
613 "mapping for 0x%08llx at 0x%08lx\n",
614 (long long)__pfn_to_phys((u64)md->pfn), addr);
618 /* N.B. ARMv6 supersections are only defined to work with domain 0.
619 * Since domain assignments can in fact be arbitrary, the
620 * 'domain == 0' check below is required to insure that ARMv6
621 * supersections are only allocated for domain 0 regardless
622 * of the actual domain assignments in use.
625 printk(KERN_ERR "MM: invalid domain in supersection "
626 "mapping for 0x%08llx at 0x%08lx\n",
627 (long long)__pfn_to_phys((u64)md->pfn), addr);
631 if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
632 printk(KERN_ERR "MM: cannot create mapping for 0x%08llx"
633 " at 0x%08lx invalid alignment\n",
634 (long long)__pfn_to_phys((u64)md->pfn), addr);
639 * Shift bits [35:32] of address into bits [23:20] of PMD
642 phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
644 pgd = pgd_offset_k(addr);
647 pud_t *pud = pud_offset(pgd, addr);
648 pmd_t *pmd = pmd_offset(pud, addr);
651 for (i = 0; i < 16; i++)
652 *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER);
654 addr += SUPERSECTION_SIZE;
655 phys += SUPERSECTION_SIZE;
656 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
657 } while (addr != end);
661 * Create the page directory entries and any necessary
662 * page tables for the mapping specified by `md'. We
663 * are able to cope here with varying sizes and address
664 * offsets, and we take full advantage of sections and
667 static void __init create_mapping(struct map_desc *md)
669 unsigned long addr, length, end;
671 const struct mem_type *type;
674 if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
675 printk(KERN_WARNING "BUG: not creating mapping for 0x%08llx"
676 " at 0x%08lx in user region\n",
677 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
681 if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
682 md->virtual >= PAGE_OFFSET && md->virtual < VMALLOC_END) {
683 printk(KERN_WARNING "BUG: mapping for 0x%08llx"
684 " at 0x%08lx overlaps vmalloc space\n",
685 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
688 type = &mem_types[md->type];
691 * Catch 36-bit addresses
693 if (md->pfn >= 0x100000) {
694 create_36bit_mapping(md, type);
698 addr = md->virtual & PAGE_MASK;
699 phys = __pfn_to_phys(md->pfn);
700 length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
702 if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
703 printk(KERN_WARNING "BUG: map for 0x%08llx at 0x%08lx can not "
704 "be mapped using pages, ignoring.\n",
705 (long long)__pfn_to_phys(md->pfn), addr);
709 pgd = pgd_offset_k(addr);
712 unsigned long next = pgd_addr_end(addr, end);
714 alloc_init_pud(pgd, addr, next, phys, type);
718 } while (pgd++, addr != end);
722 * Create the architecture specific mappings
724 void __init iotable_init(struct map_desc *io_desc, int nr)
728 for (i = 0; i < nr; i++)
729 create_mapping(io_desc + i);
732 static void * __initdata vmalloc_min = (void *)(VMALLOC_END - SZ_128M);
735 * vmalloc=size forces the vmalloc area to be exactly 'size'
736 * bytes. This can be used to increase (or decrease) the vmalloc
737 * area - the default is 128m.
739 static int __init early_vmalloc(char *arg)
741 unsigned long vmalloc_reserve = memparse(arg, NULL);
743 if (vmalloc_reserve < SZ_16M) {
744 vmalloc_reserve = SZ_16M;
746 "vmalloc area too small, limiting to %luMB\n",
747 vmalloc_reserve >> 20);
750 if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) {
751 vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M);
753 "vmalloc area is too big, limiting to %luMB\n",
754 vmalloc_reserve >> 20);
757 vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve);
760 early_param("vmalloc", early_vmalloc);
762 static phys_addr_t lowmem_limit __initdata = 0;
764 static void __init sanity_check_meminfo(void)
766 int i, j, highmem = 0;
768 lowmem_limit = __pa(vmalloc_min - 1) + 1;
769 memblock_set_current_limit(lowmem_limit);
771 for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
772 struct membank *bank = &meminfo.bank[j];
773 *bank = meminfo.bank[i];
775 #ifdef CONFIG_HIGHMEM
776 if (__va(bank->start) > vmalloc_min ||
777 __va(bank->start) < (void *)PAGE_OFFSET)
780 bank->highmem = highmem;
783 * Split those memory banks which are partially overlapping
784 * the vmalloc area greatly simplifying things later.
786 if (__va(bank->start) < vmalloc_min &&
787 bank->size > vmalloc_min - __va(bank->start)) {
788 if (meminfo.nr_banks >= NR_BANKS) {
789 printk(KERN_CRIT "NR_BANKS too low, "
790 "ignoring high memory\n");
792 memmove(bank + 1, bank,
793 (meminfo.nr_banks - i) * sizeof(*bank));
796 bank[1].size -= vmalloc_min - __va(bank->start);
797 bank[1].start = __pa(vmalloc_min - 1) + 1;
798 bank[1].highmem = highmem = 1;
801 bank->size = vmalloc_min - __va(bank->start);
804 bank->highmem = highmem;
807 * Check whether this memory bank would entirely overlap
810 if (__va(bank->start) >= vmalloc_min ||
811 __va(bank->start) < (void *)PAGE_OFFSET) {
812 printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
813 "(vmalloc region overlap).\n",
814 (unsigned long long)bank->start,
815 (unsigned long long)bank->start + bank->size - 1);
820 * Check whether this memory bank would partially overlap
823 if (__va(bank->start + bank->size) > vmalloc_min ||
824 __va(bank->start + bank->size) < __va(bank->start)) {
825 unsigned long newsize = vmalloc_min - __va(bank->start);
826 printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx "
827 "to -%.8llx (vmalloc region overlap).\n",
828 (unsigned long long)bank->start,
829 (unsigned long long)bank->start + bank->size - 1,
830 (unsigned long long)bank->start + newsize - 1);
831 bank->size = newsize;
836 #ifdef CONFIG_HIGHMEM
838 const char *reason = NULL;
840 if (cache_is_vipt_aliasing()) {
842 * Interactions between kmap and other mappings
843 * make highmem support with aliasing VIPT caches
846 reason = "with VIPT aliasing cache";
849 printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n",
851 while (j > 0 && meminfo.bank[j - 1].highmem)
856 meminfo.nr_banks = j;
859 static inline void prepare_page_table(void)
865 * Clear out all the mappings below the kernel image.
867 for (addr = 0; addr < MODULES_VADDR; addr += PGDIR_SIZE)
868 pmd_clear(pmd_off_k(addr));
870 #ifdef CONFIG_XIP_KERNEL
871 /* The XIP kernel is mapped in the module area -- skip over it */
872 addr = ((unsigned long)_etext + PGDIR_SIZE - 1) & PGDIR_MASK;
874 for ( ; addr < PAGE_OFFSET; addr += PGDIR_SIZE)
875 pmd_clear(pmd_off_k(addr));
878 * Find the end of the first block of lowmem.
880 end = memblock.memory.regions[0].base + memblock.memory.regions[0].size;
881 if (end >= lowmem_limit)
885 * Clear out all the kernel space mappings, except for the first
886 * memory bank, up to the end of the vmalloc region.
888 for (addr = __phys_to_virt(end);
889 addr < VMALLOC_END; addr += PGDIR_SIZE)
890 pmd_clear(pmd_off_k(addr));
894 * Reserve the special regions of memory
896 void __init arm_mm_memblock_reserve(void)
899 * Reserve the page tables. These are already in use,
900 * and can only be in node 0.
902 memblock_reserve(__pa(swapper_pg_dir), PTRS_PER_PGD * sizeof(pgd_t));
906 * Because of the SA1111 DMA bug, we want to preserve our
907 * precious DMA-able memory...
909 memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
914 * Set up device the mappings. Since we clear out the page tables for all
915 * mappings above VMALLOC_END, we will remove any debug device mappings.
916 * This means you have to be careful how you debug this function, or any
917 * called function. This means you can't use any function or debugging
918 * method which may touch any device, otherwise the kernel _will_ crash.
920 static void __init devicemaps_init(struct machine_desc *mdesc)
926 * Allocate the vector page early.
928 vectors_page = early_alloc(PAGE_SIZE);
930 for (addr = VMALLOC_END; addr; addr += PGDIR_SIZE)
931 pmd_clear(pmd_off_k(addr));
934 * Map the kernel if it is XIP.
935 * It is always first in the modulearea.
937 #ifdef CONFIG_XIP_KERNEL
938 map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
939 map.virtual = MODULES_VADDR;
940 map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK;
942 create_mapping(&map);
946 * Map the cache flushing regions.
949 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
950 map.virtual = FLUSH_BASE;
952 map.type = MT_CACHECLEAN;
953 create_mapping(&map);
955 #ifdef FLUSH_BASE_MINICACHE
956 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
957 map.virtual = FLUSH_BASE_MINICACHE;
959 map.type = MT_MINICLEAN;
960 create_mapping(&map);
964 * Create a mapping for the machine vectors at the high-vectors
965 * location (0xffff0000). If we aren't using high-vectors, also
966 * create a mapping at the low-vectors virtual address.
968 map.pfn = __phys_to_pfn(virt_to_phys(vectors_page));
969 map.virtual = 0xffff0000;
970 map.length = PAGE_SIZE;
971 map.type = MT_HIGH_VECTORS;
972 create_mapping(&map);
974 if (!vectors_high()) {
976 map.type = MT_LOW_VECTORS;
977 create_mapping(&map);
981 * Ask the machine support to map in the statically mapped devices.
987 * Finally flush the caches and tlb to ensure that we're in a
988 * consistent state wrt the writebuffer. This also ensures that
989 * any write-allocated cache lines in the vector page are written
990 * back. After this point, we can start to touch devices again.
992 local_flush_tlb_all();
996 static void __init kmap_init(void)
998 #ifdef CONFIG_HIGHMEM
999 pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE),
1000 PKMAP_BASE, _PAGE_KERNEL_TABLE);
1004 static void __init map_lowmem(void)
1006 struct memblock_region *reg;
1008 /* Map all the lowmem memory banks. */
1009 for_each_memblock(memory, reg) {
1010 phys_addr_t start = reg->base;
1011 phys_addr_t end = start + reg->size;
1012 struct map_desc map;
1014 if (end > lowmem_limit)
1019 map.pfn = __phys_to_pfn(start);
1020 map.virtual = __phys_to_virt(start);
1021 map.length = end - start;
1022 map.type = MT_MEMORY;
1024 create_mapping(&map);
1029 * paging_init() sets up the page tables, initialises the zone memory
1030 * maps, and sets up the zero page, bad page and bad page tables.
1032 void __init paging_init(struct machine_desc *mdesc)
1036 build_mem_type_table();
1037 sanity_check_meminfo();
1038 prepare_page_table();
1040 devicemaps_init(mdesc);
1043 top_pmd = pmd_off_k(0xffff0000);
1045 /* allocate the zero page. */
1046 zero_page = early_alloc(PAGE_SIZE);
1050 empty_zero_page = virt_to_page(zero_page);
1051 __flush_dcache_page(NULL, empty_zero_page);