arch/arm/mm/mmu.c

   1 /*
   2  *  linux/arch/arm/mm/mmu.c
   3  *
   4  *  Copyright (C) 1995-2005 Russell King
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #include <linux/module.h>
  11 #include <linux/kernel.h>
  12 #include <linux/errno.h>
  13 #include <linux/init.h>
  14 #include <linux/mman.h>
  15 #include <linux/nodemask.h>
  16 #include <linux/memblock.h>
  17 #include <linux/fs.h>
  18
  19 #include <asm/cputype.h>
  20 #include <asm/sections.h>
  21 #include <asm/cachetype.h>
  22 #include <asm/setup.h>
  23 #include <asm/sizes.h>
  24 #include <asm/smp_plat.h>
  25 #include <asm/tlb.h>
  26 #include <asm/highmem.h>
  27 #include <asm/traps.h>
  28
  29 #include <asm/mach/arch.h>
  30 #include <asm/mach/map.h>
  31
  32 #include "mm.h"
  33
  34 DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
  35
  36 /*
  37  * empty_zero_page is a special page that is used for
  38  * zero-initialized data and COW.
  39  */
  40 struct page *empty_zero_page;
  41 EXPORT_SYMBOL(empty_zero_page);
  42
  43 /*
  44  * The pmd table for the upper-most set of pages.
  45  */
  46 pmd_t *top_pmd;
  47
  48 #define CPOLICY_UNCACHED        0
  49 #define CPOLICY_BUFFERED        1
  50 #define CPOLICY_WRITETHROUGH    2
  51 #define CPOLICY_WRITEBACK       3
  52 #define CPOLICY_WRITEALLOC      4
  53
  54 static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
  55 static unsigned int ecc_mask __initdata = 0;
  56 pgprot_t pgprot_user;
  57 pgprot_t pgprot_kernel;
  58
  59 EXPORT_SYMBOL(pgprot_user);
  60 EXPORT_SYMBOL(pgprot_kernel);
  61
  62 struct cachepolicy {
  63         const char      policy[16];
  64         unsigned int    cr_mask;
  65         unsigned int    pmd;
  66         pteval_t        pte;
  67 };
  68
  69 static struct cachepolicy cache_policies[] __initdata = {
  70         {
  71                 .policy         = "uncached",
  72                 .cr_mask        = CR_W|CR_C,
  73                 .pmd            = PMD_SECT_UNCACHED,
  74                 .pte            = L_PTE_MT_UNCACHED,
  75         }, {
  76                 .policy         = "buffered",
  77                 .cr_mask        = CR_C,
  78                 .pmd            = PMD_SECT_BUFFERED,
  79                 .pte            = L_PTE_MT_BUFFERABLE,
  80         }, {
  81                 .policy         = "writethrough",
  82                 .cr_mask        = 0,
  83                 .pmd            = PMD_SECT_WT,
  84                 .pte            = L_PTE_MT_WRITETHROUGH,
  85         }, {
  86                 .policy         = "writeback",
  87                 .cr_mask        = 0,
  88                 .pmd            = PMD_SECT_WB,
  89                 .pte            = L_PTE_MT_WRITEBACK,
  90         }, {
  91                 .policy         = "writealloc",
  92                 .cr_mask        = 0,
  93                 .pmd            = PMD_SECT_WBWA,
  94                 .pte            = L_PTE_MT_WRITEALLOC,
  95         }
  96 };
  97
  98 /*
  99  * These are useful for identifying cache coherency
 100  * problems by allowing the cache or the cache and
 101  * writebuffer to be turned off.  (Note: the write
 102  * buffer should not be on and the cache off).
 103  */
 104 static int __init early_cachepolicy(char *p)
 105 {
 106         int i;
 107
 108         for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
 109                 int len = strlen(cache_policies[i].policy);
 110
 111                 if (memcmp(p, cache_policies[i].policy, len) == 0) {
 112                         cachepolicy = i;
 113                         cr_alignment &= ~cache_policies[i].cr_mask;
 114                         cr_no_alignment &= ~cache_policies[i].cr_mask;
 115                         break;
 116                 }
 117         }
 118         if (i == ARRAY_SIZE(cache_policies))
 119                 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
 120         /*
 121          * This restriction is partly to do with the way we boot; it is
 122          * unpredictable to have memory mapped using two different sets of
 123          * memory attributes (shared, type, and cache attribs).  We can not
 124          * change these attributes once the initial assembly has setup the
 125          * page tables.
 126          */
 127         if (cpu_architecture() >= CPU_ARCH_ARMv6) {
 128                 printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
 129                 cachepolicy = CPOLICY_WRITEBACK;
 130         }
 131         flush_cache_all();
 132         set_cr(cr_alignment);
 133         return 0;
 134 }
 135 early_param("cachepolicy", early_cachepolicy);
 136
 137 static int __init early_nocache(char *__unused)
 138 {
 139         char *p = "buffered";
 140         printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
 141         early_cachepolicy(p);
 142         return 0;
 143 }
 144 early_param("nocache", early_nocache);
 145
 146 static int __init early_nowrite(char *__unused)
 147 {
 148         char *p = "uncached";
 149         printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
 150         early_cachepolicy(p);
 151         return 0;
 152 }
 153 early_param("nowb", early_nowrite);
 154
 155 static int __init early_ecc(char *p)
 156 {
 157         if (memcmp(p, "on", 2) == 0)
 158                 ecc_mask = PMD_PROTECTION;
 159         else if (memcmp(p, "off", 3) == 0)
 160                 ecc_mask = 0;
 161         return 0;
 162 }
 163 early_param("ecc", early_ecc);
 164
 165 static int __init noalign_setup(char *__unused)
 166 {
 167         cr_alignment &= ~CR_A;
 168         cr_no_alignment &= ~CR_A;
 169         set_cr(cr_alignment);
 170         return 1;
 171 }
 172 __setup("noalign", noalign_setup);
 173
 174 #ifndef CONFIG_SMP
 175 void adjust_cr(unsigned long mask, unsigned long set)
 176 {
 177         unsigned long flags;
 178
 179         mask &= ~CR_A;
 180
 181         set &= mask;
 182
 183         local_irq_save(flags);
 184
 185         cr_no_alignment = (cr_no_alignment & ~mask) | set;
 186         cr_alignment = (cr_alignment & ~mask) | set;
 187
 188         set_cr((get_cr() & ~mask) | set);
 189
 190         local_irq_restore(flags);
 191 }
 192 #endif
 193
 194 #define PROT_PTE_DEVICE         L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
 195 #define PROT_SECT_DEVICE        PMD_TYPE_SECT|PMD_SECT_AP_WRITE
 196
 197 static struct mem_type mem_types[] = {
 198         [MT_DEVICE] = {           /* Strongly ordered / ARMv6 shared device */
 199                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
 200                                   L_PTE_SHARED,
 201                 .prot_l1        = PMD_TYPE_TABLE,
 202                 .prot_sect      = PROT_SECT_DEVICE | PMD_SECT_S,
 203                 .domain         = DOMAIN_IO,
 204         },
 205         [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
 206                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
 207                 .prot_l1        = PMD_TYPE_TABLE,
 208                 .prot_sect      = PROT_SECT_DEVICE,
 209                 .domain         = DOMAIN_IO,
 210         },
 211         [MT_DEVICE_CACHED] = {    /* ioremap_cached */
 212                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
 213                 .prot_l1        = PMD_TYPE_TABLE,
 214                 .prot_sect      = PROT_SECT_DEVICE | PMD_SECT_WB,
 215                 .domain         = DOMAIN_IO,
 216         },
 217         [MT_DEVICE_WC] = {      /* ioremap_wc */
 218                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
 219                 .prot_l1        = PMD_TYPE_TABLE,
 220                 .prot_sect      = PROT_SECT_DEVICE,
 221                 .domain         = DOMAIN_IO,
 222         },
 223         [MT_UNCACHED] = {
 224                 .prot_pte       = PROT_PTE_DEVICE,
 225                 .prot_l1        = PMD_TYPE_TABLE,
 226                 .prot_sect      = PMD_TYPE_SECT | PMD_SECT_XN,
 227                 .domain         = DOMAIN_IO,
 228         },
 229         [MT_CACHECLEAN] = {
 230                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
 231                 .domain    = DOMAIN_KERNEL,
 232         },
 233         [MT_MINICLEAN] = {
 234                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
 235                 .domain    = DOMAIN_KERNEL,
 236         },
 237         [MT_LOW_VECTORS] = {
 238                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 239                                 L_PTE_RDONLY,
 240                 .prot_l1   = PMD_TYPE_TABLE,
 241                 .domain    = DOMAIN_USER,
 242         },
 243         [MT_HIGH_VECTORS] = {
 244                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 245                                 L_PTE_USER | L_PTE_RDONLY,
 246                 .prot_l1   = PMD_TYPE_TABLE,
 247                 .domain    = DOMAIN_USER,
 248         },
 249         [MT_MEMORY] = {
 250                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
 251                 .prot_l1   = PMD_TYPE_TABLE,
 252                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
 253                 .domain    = DOMAIN_KERNEL,
 254         },
 255         [MT_ROM] = {
 256                 .prot_sect = PMD_TYPE_SECT,
 257                 .domain    = DOMAIN_KERNEL,
 258         },
 259         [MT_MEMORY_NONCACHED] = {
 260                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 261                                 L_PTE_MT_BUFFERABLE,
 262                 .prot_l1   = PMD_TYPE_TABLE,
 263                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
 264                 .domain    = DOMAIN_KERNEL,
 265         },
 266         [MT_MEMORY_DTCM] = {
 267                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 268                                 L_PTE_XN,
 269                 .prot_l1   = PMD_TYPE_TABLE,
 270                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
 271                 .domain    = DOMAIN_KERNEL,
 272         },
 273         [MT_MEMORY_ITCM] = {
 274                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
 275                 .prot_l1   = PMD_TYPE_TABLE,
 276                 .domain    = DOMAIN_KERNEL,
 277         },
 278 };
 279
 280 const struct mem_type *get_mem_type(unsigned int type)
 281 {
 282         return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
 283 }
 284 EXPORT_SYMBOL(get_mem_type);
 285
 286 /*
 287  * Adjust the PMD section entries according to the CPU in use.
 288  */
 289 static void __init build_mem_type_table(void)
 290 {
 291         struct cachepolicy *cp;
 292         unsigned int cr = get_cr();
 293         unsigned int user_pgprot, kern_pgprot, vecs_pgprot;
 294         int cpu_arch = cpu_architecture();
 295         int i;
 296
 297         if (cpu_arch < CPU_ARCH_ARMv6) {
 298 #if defined(CONFIG_CPU_DCACHE_DISABLE)
 299                 if (cachepolicy > CPOLICY_BUFFERED)
 300                         cachepolicy = CPOLICY_BUFFERED;
 301 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
 302                 if (cachepolicy > CPOLICY_WRITETHROUGH)
 303                         cachepolicy = CPOLICY_WRITETHROUGH;
 304 #endif
 305         }
 306         if (cpu_arch < CPU_ARCH_ARMv5) {
 307                 if (cachepolicy >= CPOLICY_WRITEALLOC)
 308                         cachepolicy = CPOLICY_WRITEBACK;
 309                 ecc_mask = 0;
 310         }
 311         if (is_smp())
 312                 cachepolicy = CPOLICY_WRITEALLOC;
 313
 314         /*
 315          * Strip out features not present on earlier architectures.
 316          * Pre-ARMv5 CPUs don't have TEX bits.  Pre-ARMv6 CPUs or those
 317          * without extended page tables don't have the 'Shared' bit.
 318          */
 319         if (cpu_arch < CPU_ARCH_ARMv5)
 320                 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
 321                         mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
 322         if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
 323                 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
 324                         mem_types[i].prot_sect &= ~PMD_SECT_S;
 325
 326         /*
 327          * ARMv5 and lower, bit 4 must be set for page tables (was: cache
 328          * "update-able on write" bit on ARM610).  However, Xscale and
 329          * Xscale3 require this bit to be cleared.
 330          */
 331         if (cpu_is_xscale() || cpu_is_xsc3()) {
 332                 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
 333                         mem_types[i].prot_sect &= ~PMD_BIT4;
 334                         mem_types[i].prot_l1 &= ~PMD_BIT4;
 335                 }
 336         } else if (cpu_arch < CPU_ARCH_ARMv6) {
 337                 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
 338                         if (mem_types[i].prot_l1)
 339                                 mem_types[i].prot_l1 |= PMD_BIT4;
 340                         if (mem_types[i].prot_sect)
 341                                 mem_types[i].prot_sect |= PMD_BIT4;
 342                 }
 343         }
 344
 345         /*
 346          * Mark the device areas according to the CPU/architecture.
 347          */
 348         if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
 349                 if (!cpu_is_xsc3()) {
 350                         /*
 351                          * Mark device regions on ARMv6+ as execute-never
 352                          * to prevent speculative instruction fetches.
 353                          */
 354                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
 355                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
 356                         mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
 357                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
 358                 }
 359                 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
 360                         /*
 361                          * For ARMv7 with TEX remapping,
 362                          * - shared device is SXCB=1100
 363                          * - nonshared device is SXCB=0100
 364                          * - write combine device mem is SXCB=0001
 365                          * (Uncached Normal memory)
 366                          */
 367                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
 368                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
 369                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
 370                 } else if (cpu_is_xsc3()) {
 371                         /*
 372                          * For Xscale3,
 373                          * - shared device is TEXCB=00101
 374                          * - nonshared device is TEXCB=01000
 375                          * - write combine device mem is TEXCB=00100
 376                          * (Inner/Outer Uncacheable in xsc3 parlance)
 377                          */
 378                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
 379                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
 380                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
 381                 } else {
 382                         /*
 383                          * For ARMv6 and ARMv7 without TEX remapping,
 384                          * - shared device is TEXCB=00001
 385                          * - nonshared device is TEXCB=01000
 386                          * - write combine device mem is TEXCB=00100
 387                          * (Uncached Normal in ARMv6 parlance).
 388                          */
 389                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
 390                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
 391                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
 392                 }
 393         } else {
 394                 /*
 395                  * On others, write combining is "Uncached/Buffered"
 396                  */
 397                 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
 398         }
 399
 400         /*
 401          * Now deal with the memory-type mappings
 402          */
 403         cp = &cache_policies[cachepolicy];
 404         vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
 405
 406         /*
 407          * Only use write-through for non-SMP systems
 408          */
 409         if (!is_smp() && cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH)
 410                 vecs_pgprot = cache_policies[CPOLICY_WRITETHROUGH].pte;
 411
 412         /*
 413          * Enable CPU-specific coherency if supported.
 414          * (Only available on XSC3 at the moment.)
 415          */
 416         if (arch_is_coherent() && cpu_is_xsc3()) {
 417                 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
 418                 mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
 419                 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
 420                 mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
 421         }
 422         /*
 423          * ARMv6 and above have extended page tables.
 424          */
 425         if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
 426                 /*
 427                  * Mark cache clean areas and XIP ROM read only
 428                  * from SVC mode and no access from userspace.
 429                  */
 430                 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 431                 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 432                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 433
 434                 if (is_smp()) {
 435                         /*
 436                          * Mark memory with the "shared" attribute
 437                          * for SMP systems
 438                          */
 439                         user_pgprot |= L_PTE_SHARED;
 440                         kern_pgprot |= L_PTE_SHARED;
 441                         vecs_pgprot |= L_PTE_SHARED;
 442                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
 443                         mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
 444                         mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
 445                         mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
 446                         mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
 447                         mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
 448                         mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
 449                         mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
 450                 }
 451         }
 452
 453         /*
 454          * Non-cacheable Normal - intended for memory areas that must
 455          * not cause dirty cache line writebacks when used
 456          */
 457         if (cpu_arch >= CPU_ARCH_ARMv6) {
 458                 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
 459                         /* Non-cacheable Normal is XCB = 001 */
 460                         mem_types[MT_MEMORY_NONCACHED].prot_sect |=
 461                                 PMD_SECT_BUFFERED;
 462                 } else {
 463                         /* For both ARMv6 and non-TEX-remapping ARMv7 */
 464                         mem_types[MT_MEMORY_NONCACHED].prot_sect |=
 465                                 PMD_SECT_TEX(1);
 466                 }
 467         } else {
 468                 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
 469         }
 470
 471         for (i = 0; i < 16; i++) {
 472                 unsigned long v = pgprot_val(protection_map[i]);
 473                 protection_map[i] = __pgprot(v | user_pgprot);
 474         }
 475
 476         mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
 477         mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
 478
 479         pgprot_user   = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
 480         pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
 481                                  L_PTE_DIRTY | kern_pgprot);
 482
 483         mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
 484         mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
 485         mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
 486         mem_types[MT_MEMORY].prot_pte |= kern_pgprot;
 487         mem_types[MT_MEMORY_NONCACHED].prot_sect |= ecc_mask;
 488         mem_types[MT_ROM].prot_sect |= cp->pmd;
 489
 490         switch (cp->pmd) {
 491         case PMD_SECT_WT:
 492                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
 493                 break;
 494         case PMD_SECT_WB:
 495         case PMD_SECT_WBWA:
 496                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
 497                 break;
 498         }
 499         printk("Memory policy: ECC %sabled, Data cache %s\n",
 500                 ecc_mask ? "en" : "dis", cp->policy);
 501
 502         for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
 503                 struct mem_type *t = &mem_types[i];
 504                 if (t->prot_l1)
 505                         t->prot_l1 |= PMD_DOMAIN(t->domain);
 506                 if (t->prot_sect)
 507                         t->prot_sect |= PMD_DOMAIN(t->domain);
 508         }
 509 }
 510
 511 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
 512 pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
 513                               unsigned long size, pgprot_t vma_prot)
 514 {
 515         if (!pfn_valid(pfn))
 516                 return pgprot_noncached(vma_prot);
 517         else if (file->f_flags & O_SYNC)
 518                 return pgprot_writecombine(vma_prot);
 519         return vma_prot;
 520 }
 521 EXPORT_SYMBOL(phys_mem_access_prot);
 522 #endif
 523
 524 #define vectors_base()  (vectors_high() ? 0xffff0000 : 0)
 525
 526 static void __init *early_alloc(unsigned long sz)
 527 {
 528         void *ptr = __va(memblock_alloc(sz, sz));
 529         memset(ptr, 0, sz);
 530         return ptr;
 531 }
 532
 533 static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot)
 534 {
 535         if (pmd_none(*pmd)) {
 536                 pte_t *pte = early_alloc(2 * PTRS_PER_PTE * sizeof(pte_t));
 537                 __pmd_populate(pmd, __pa(pte), prot);
 538         }
 539         BUG_ON(pmd_bad(*pmd));
 540         return pte_offset_kernel(pmd, addr);
 541 }
 542
 543 static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
 544                                   unsigned long end, unsigned long pfn,
 545                                   const struct mem_type *type)
 546 {
 547         pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1);
 548         do {
 549                 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0);
 550                 pfn++;
 551         } while (pte++, addr += PAGE_SIZE, addr != end);
 552 }
 553
 554 static void __init alloc_init_section(pgd_t *pgd, unsigned long addr,
 555                                       unsigned long end, phys_addr_t phys,
 556                                       const struct mem_type *type)
 557 {
 558         pmd_t *pmd = pmd_offset(pgd, addr);
 559
 560         /*
 561          * Try a section mapping - end, addr and phys must all be aligned
 562          * to a section boundary.  Note that PMDs refer to the individual
 563          * L1 entries, whereas PGDs refer to a group of L1 entries making
 564          * up one logical pointer to an L2 table.
 565          */
 566         if (((addr | end | phys) & ~SECTION_MASK) == 0) {
 567                 pmd_t *p = pmd;
 568
 569                 if (addr & SECTION_SIZE)
 570                         pmd++;
 571
 572                 do {
 573                         *pmd = __pmd(phys | type->prot_sect);
 574                         phys += SECTION_SIZE;
 575                 } while (pmd++, addr += SECTION_SIZE, addr != end);
 576
 577                 flush_pmd_entry(p);
 578         } else {
 579                 /*
 580                  * No need to loop; pte's aren't interested in the
 581                  * individual L1 entries.
 582                  */
 583                 alloc_init_pte(pmd, addr, end, __phys_to_pfn(phys), type);
 584         }
 585 }
 586
 587 static void __init create_36bit_mapping(struct map_desc *md,
 588                                         const struct mem_type *type)
 589 {
 590         unsigned long addr, length, end;
 591         phys_addr_t phys;
 592         pgd_t *pgd;
 593
 594         addr = md->virtual;
 595         phys = (unsigned long)__pfn_to_phys(md->pfn);
 596         length = PAGE_ALIGN(md->length);
 597
 598         if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
 599                 printk(KERN_ERR "MM: CPU does not support supersection "
 600                        "mapping for 0x%08llx at 0x%08lx\n",
 601                        __pfn_to_phys((u64)md->pfn), addr);
 602                 return;
 603         }
 604
 605         /* N.B. ARMv6 supersections are only defined to work with domain 0.
 606          *      Since domain assignments can in fact be arbitrary, the
 607          *      'domain == 0' check below is required to insure that ARMv6
 608          *      supersections are only allocated for domain 0 regardless
 609          *      of the actual domain assignments in use.
 610          */
 611         if (type->domain) {
 612                 printk(KERN_ERR "MM: invalid domain in supersection "
 613                        "mapping for 0x%08llx at 0x%08lx\n",
 614                        __pfn_to_phys((u64)md->pfn), addr);
 615                 return;
 616         }
 617
 618         if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
 619                 printk(KERN_ERR "MM: cannot create mapping for "
 620                        "0x%08llx at 0x%08lx invalid alignment\n",
 621                        __pfn_to_phys((u64)md->pfn), addr);
 622                 return;
 623         }
 624
 625         /*
 626          * Shift bits [35:32] of address into bits [23:20] of PMD
 627          * (See ARMv6 spec).
 628          */
 629         phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
 630
 631         pgd = pgd_offset_k(addr);
 632         end = addr + length;
 633         do {
 634                 pmd_t *pmd = pmd_offset(pgd, addr);
 635                 int i;
 636
 637                 for (i = 0; i < 16; i++)
 638                         *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER);
 639
 640                 addr += SUPERSECTION_SIZE;
 641                 phys += SUPERSECTION_SIZE;
 642                 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
 643         } while (addr != end);
 644 }
 645
 646 /*
 647  * Create the page directory entries and any necessary
 648  * page tables for the mapping specified by `md'.  We
 649  * are able to cope here with varying sizes and address
 650  * offsets, and we take full advantage of sections and
 651  * supersections.
 652  */
 653 static void __init create_mapping(struct map_desc *md)
 654 {
 655         unsigned long phys, addr, length, end;
 656         const struct mem_type *type;
 657         pgd_t *pgd;
 658
 659         if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
 660                 printk(KERN_WARNING "BUG: not creating mapping for "
 661                        "0x%08llx at 0x%08lx in user region\n",
 662                        __pfn_to_phys((u64)md->pfn), md->virtual);
 663                 return;
 664         }
 665
 666         if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
 667             md->virtual >= PAGE_OFFSET && md->virtual < VMALLOC_END) {
 668                 printk(KERN_WARNING "BUG: mapping for 0x%08llx at 0x%08lx "
 669                        "overlaps vmalloc space\n",
 670                        __pfn_to_phys((u64)md->pfn), md->virtual);
 671         }
 672
 673         type = &mem_types[md->type];
 674
 675         /*
 676          * Catch 36-bit addresses
 677          */
 678         if (md->pfn >= 0x100000) {
 679                 create_36bit_mapping(md, type);
 680                 return;
 681         }
 682
 683         addr = md->virtual & PAGE_MASK;
 684         phys = (unsigned long)__pfn_to_phys(md->pfn);
 685         length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
 686
 687         if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
 688                 printk(KERN_WARNING "BUG: map for 0x%08lx at 0x%08lx can not "
 689                        "be mapped using pages, ignoring.\n",
 690                        __pfn_to_phys(md->pfn), addr);
 691                 return;
 692         }
 693
 694         pgd = pgd_offset_k(addr);
 695         end = addr + length;
 696         do {
 697                 unsigned long next = pgd_addr_end(addr, end);
 698
 699                 alloc_init_section(pgd, addr, next, phys, type);
 700
 701                 phys += next - addr;
 702                 addr = next;
 703         } while (pgd++, addr != end);
 704 }
 705
 706 /*
 707  * Create the architecture specific mappings
 708  */
 709 void __init iotable_init(struct map_desc *io_desc, int nr)
 710 {
 711         int i;
 712
 713         for (i = 0; i < nr; i++)
 714                 create_mapping(io_desc + i);
 715 }
 716
 717 static void * __initdata vmalloc_min = (void *)(VMALLOC_END - SZ_128M);
 718
 719 /*
 720  * vmalloc=size forces the vmalloc area to be exactly 'size'
 721  * bytes. This can be used to increase (or decrease) the vmalloc
 722  * area - the default is 128m.
 723  */
 724 static int __init early_vmalloc(char *arg)
 725 {
 726         unsigned long vmalloc_reserve = memparse(arg, NULL);
 727
 728         if (vmalloc_reserve < SZ_16M) {
 729                 vmalloc_reserve = SZ_16M;
 730                 printk(KERN_WARNING
 731                         "vmalloc area too small, limiting to %luMB\n",
 732                         vmalloc_reserve >> 20);
 733         }
 734
 735         if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) {
 736                 vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M);
 737                 printk(KERN_WARNING
 738                         "vmalloc area is too big, limiting to %luMB\n",
 739                         vmalloc_reserve >> 20);
 740         }
 741
 742         vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve);
 743         return 0;
 744 }
 745 early_param("vmalloc", early_vmalloc);
 746
 747 static phys_addr_t lowmem_limit __initdata = 0;
 748
 749 static void __init sanity_check_meminfo(void)
 750 {
 751         int i, j, highmem = 0;
 752
 753         lowmem_limit = __pa(vmalloc_min - 1) + 1;
 754         memblock_set_current_limit(lowmem_limit);
 755
 756         for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
 757                 struct membank *bank = &meminfo.bank[j];
 758                 *bank = meminfo.bank[i];
 759
 760 #ifdef CONFIG_HIGHMEM
 761                 if (__va(bank->start) > vmalloc_min ||
 762                     __va(bank->start) < (void *)PAGE_OFFSET)
 763                         highmem = 1;
 764
 765                 bank->highmem = highmem;
 766
 767                 /*
 768                  * Split those memory banks which are partially overlapping
 769                  * the vmalloc area greatly simplifying things later.
 770                  */
 771                 if (__va(bank->start) < vmalloc_min &&
 772                     bank->size > vmalloc_min - __va(bank->start)) {
 773                         if (meminfo.nr_banks >= NR_BANKS) {
 774                                 printk(KERN_CRIT "NR_BANKS too low, "
 775                                                  "ignoring high memory\n");
 776                         } else {
 777                                 memmove(bank + 1, bank,
 778                                         (meminfo.nr_banks - i) * sizeof(*bank));
 779                                 meminfo.nr_banks++;
 780                                 i++;
 781                                 bank[1].size -= vmalloc_min - __va(bank->start);
 782                                 bank[1].start = __pa(vmalloc_min - 1) + 1;
 783                                 bank[1].highmem = highmem = 1;
 784                                 j++;
 785                         }
 786                         bank->size = vmalloc_min - __va(bank->start);
 787                 }
 788 #else
 789                 bank->highmem = highmem;
 790
 791                 /*
 792                  * Check whether this memory bank would entirely overlap
 793                  * the vmalloc area.
 794                  */
 795                 if (__va(bank->start) >= vmalloc_min ||
 796                     __va(bank->start) < (void *)PAGE_OFFSET) {
 797                         printk(KERN_NOTICE "Ignoring RAM at %.8lx-%.8lx "
 798                                "(vmalloc region overlap).\n",
 799                                bank->start, bank->start + bank->size - 1);
 800                         continue;
 801                 }
 802
 803                 /*
 804                  * Check whether this memory bank would partially overlap
 805                  * the vmalloc area.
 806                  */
 807                 if (__va(bank->start + bank->size) > vmalloc_min ||
 808                     __va(bank->start + bank->size) < __va(bank->start)) {
 809                         unsigned long newsize = vmalloc_min - __va(bank->start);
 810                         printk(KERN_NOTICE "Truncating RAM at %.8lx-%.8lx "
 811                                "to -%.8lx (vmalloc region overlap).\n",
 812                                bank->start, bank->start + bank->size - 1,
 813                                bank->start + newsize - 1);
 814                         bank->size = newsize;
 815                 }
 816 #endif
 817                 j++;
 818         }
 819 #ifdef CONFIG_HIGHMEM
 820         if (highmem) {
 821                 const char *reason = NULL;
 822
 823                 if (cache_is_vipt_aliasing()) {
 824                         /*
 825                          * Interactions between kmap and other mappings
 826                          * make highmem support with aliasing VIPT caches
 827                          * rather difficult.
 828                          */
 829                         reason = "with VIPT aliasing cache";
 830                 } else if (is_smp() && tlb_ops_need_broadcast()) {
 831                         /*
 832                          * kmap_high needs to occasionally flush TLB entries,
 833                          * however, if the TLB entries need to be broadcast
 834                          * we may deadlock:
 835                          *  kmap_high(irqs off)->flush_all_zero_pkmaps->
 836                          *  flush_tlb_kernel_range->smp_call_function_many
 837                          *   (must not be called with irqs off)
 838                          */
 839                         reason = "without hardware TLB ops broadcasting";
 840                 }
 841                 if (reason) {
 842                         printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n",
 843                                 reason);
 844                         while (j > 0 && meminfo.bank[j - 1].highmem)
 845                                 j--;
 846                 }
 847         }
 848 #endif
 849         meminfo.nr_banks = j;
 850 }
 851
 852 static inline void prepare_page_table(void)
 853 {
 854         unsigned long addr;
 855         phys_addr_t end;
 856
 857         /*
 858          * Clear out all the mappings below the kernel image.
 859          */
 860         for (addr = 0; addr < MODULES_VADDR; addr += PGDIR_SIZE)
 861                 pmd_clear(pmd_off_k(addr));
 862
 863 #ifdef CONFIG_XIP_KERNEL
 864         /* The XIP kernel is mapped in the module area -- skip over it */
 865         addr = ((unsigned long)_etext + PGDIR_SIZE - 1) & PGDIR_MASK;
 866 #endif
 867         for ( ; addr < PAGE_OFFSET; addr += PGDIR_SIZE)
 868                 pmd_clear(pmd_off_k(addr));
 869
 870         /*
 871          * Find the end of the first block of lowmem.
 872          */
 873         end = memblock.memory.regions[0].base + memblock.memory.regions[0].size;
 874         if (end >= lowmem_limit)
 875                 end = lowmem_limit;
 876
 877         /*
 878          * Clear out all the kernel space mappings, except for the first
 879          * memory bank, up to the end of the vmalloc region.
 880          */
 881         for (addr = __phys_to_virt(end);
 882              addr < VMALLOC_END; addr += PGDIR_SIZE)
 883                 pmd_clear(pmd_off_k(addr));
 884 }
 885
 886 /*
 887  * Reserve the special regions of memory
 888  */
 889 void __init arm_mm_memblock_reserve(void)
 890 {
 891         /*
 892          * Reserve the page tables.  These are already in use,
 893          * and can only be in node 0.
 894          */
 895         memblock_reserve(__pa(swapper_pg_dir), PTRS_PER_PGD * sizeof(pgd_t));
 896
 897 #ifdef CONFIG_SA1111
 898         /*
 899          * Because of the SA1111 DMA bug, we want to preserve our
 900          * precious DMA-able memory...
 901          */
 902         memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
 903 #endif
 904 }
 905
 906 /*
 907  * Set up device the mappings.  Since we clear out the page tables for all
 908  * mappings above VMALLOC_END, we will remove any debug device mappings.
 909  * This means you have to be careful how you debug this function, or any
 910  * called function.  This means you can't use any function or debugging
 911  * method which may touch any device, otherwise the kernel _will_ crash.
 912  */
 913 static void __init devicemaps_init(struct machine_desc *mdesc)
 914 {
 915         struct map_desc map;
 916         unsigned long addr;
 917
 918         /*
 919          * Allocate the vector page early.
 920          */
 921         vectors_page = early_alloc(PAGE_SIZE);
 922
 923         for (addr = VMALLOC_END; addr; addr += PGDIR_SIZE)
 924                 pmd_clear(pmd_off_k(addr));
 925
 926         /*
 927          * Map the kernel if it is XIP.
 928          * It is always first in the modulearea.
 929          */
 930 #ifdef CONFIG_XIP_KERNEL
 931         map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
 932         map.virtual = MODULES_VADDR;
 933         map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK;
 934         map.type = MT_ROM;
 935         create_mapping(&map);
 936 #endif
 937
 938         /*
 939          * Map the cache flushing regions.
 940          */
 941 #ifdef FLUSH_BASE
 942         map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
 943         map.virtual = FLUSH_BASE;
 944         map.length = SZ_1M;
 945         map.type = MT_CACHECLEAN;
 946         create_mapping(&map);
 947 #endif
 948 #ifdef FLUSH_BASE_MINICACHE
 949         map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
 950         map.virtual = FLUSH_BASE_MINICACHE;
 951         map.length = SZ_1M;
 952         map.type = MT_MINICLEAN;
 953         create_mapping(&map);
 954 #endif
 955
 956         /*
 957          * Create a mapping for the machine vectors at the high-vectors
 958          * location (0xffff0000).  If we aren't using high-vectors, also
 959          * create a mapping at the low-vectors virtual address.
 960          */
 961         map.pfn = __phys_to_pfn(virt_to_phys(vectors_page));
 962         map.virtual = 0xffff0000;
 963         map.length = PAGE_SIZE;
 964         map.type = MT_HIGH_VECTORS;
 965         create_mapping(&map);
 966
 967         if (!vectors_high()) {
 968                 map.virtual = 0;
 969                 map.type = MT_LOW_VECTORS;
 970                 create_mapping(&map);
 971         }
 972
 973         /*
 974          * Ask the machine support to map in the statically mapped devices.
 975          */
 976         if (mdesc->map_io)
 977                 mdesc->map_io();
 978
 979         /*
 980          * Finally flush the caches and tlb to ensure that we're in a
 981          * consistent state wrt the writebuffer.  This also ensures that
 982          * any write-allocated cache lines in the vector page are written
 983          * back.  After this point, we can start to touch devices again.
 984          */
 985         local_flush_tlb_all();
 986         flush_cache_all();
 987 }
 988
 989 static void __init kmap_init(void)
 990 {
 991 #ifdef CONFIG_HIGHMEM
 992         pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE),
 993                 PKMAP_BASE, _PAGE_KERNEL_TABLE);
 994 #endif
 995 }
 996
 997 static void __init map_lowmem(void)
 998 {
 999         struct memblock_region *reg;
1000
1001         /* Map all the lowmem memory banks. */
1002         for_each_memblock(memory, reg) {
1003                 phys_addr_t start = reg->base;
1004                 phys_addr_t end = start + reg->size;
1005                 struct map_desc map;
1006
1007                 if (end > lowmem_limit)
1008                         end = lowmem_limit;
1009                 if (start >= end)
1010                         break;
1011
1012                 map.pfn = __phys_to_pfn(start);
1013                 map.virtual = __phys_to_virt(start);
1014                 map.length = end - start;
1015                 map.type = MT_MEMORY;
1016
1017                 create_mapping(&map);
1018         }
1019 }
1020
1021 /*
1022  * paging_init() sets up the page tables, initialises the zone memory
1023  * maps, and sets up the zero page, bad page and bad page tables.
1024  */
1025 void __init paging_init(struct machine_desc *mdesc)
1026 {
1027         void *zero_page;
1028
1029         build_mem_type_table();
1030         sanity_check_meminfo();
1031         prepare_page_table();
1032         map_lowmem();
1033         devicemaps_init(mdesc);
1034         kmap_init();
1035
1036         top_pmd = pmd_off_k(0xffff0000);
1037
1038         /* allocate the zero page. */
1039         zero_page = early_alloc(PAGE_SIZE);
1040
1041         bootmem_init();
1042
1043         empty_zero_page = virt_to_page(zero_page);
1044         __flush_dcache_page(NULL, empty_zero_page);
1045 }