arch/arm/mm/mmu.c

   1 /*
   2  *  linux/arch/arm/mm/mmu.c
   3  *
   4  *  Copyright (C) 1995-2005 Russell King
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #include <linux/module.h>
  11 #include <linux/kernel.h>
  12 #include <linux/errno.h>
  13 #include <linux/init.h>
  14 #include <linux/bootmem.h>
  15 #include <linux/mman.h>
  16 #include <linux/nodemask.h>
  17
  18 #include <asm/cputype.h>
  19 #include <asm/mach-types.h>
  20 #include <asm/sections.h>
  21 #include <asm/cachetype.h>
  22 #include <asm/setup.h>
  23 #include <asm/sizes.h>
  24 #include <asm/smp_plat.h>
  25 #include <asm/tlb.h>
  26 #include <asm/highmem.h>
  27
  28 #include <asm/mach/arch.h>
  29 #include <asm/mach/map.h>
  30
  31 #include "mm.h"
  32
  33 DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
  34
  35 /*
  36  * empty_zero_page is a special page that is used for
  37  * zero-initialized data and COW.
  38  */
  39 struct page *empty_zero_page;
  40 EXPORT_SYMBOL(empty_zero_page);
  41
  42 /*
  43  * The pmd table for the upper-most set of pages.
  44  */
  45 pmd_t *top_pmd;
  46
  47 #define CPOLICY_UNCACHED        0
  48 #define CPOLICY_BUFFERED        1
  49 #define CPOLICY_WRITETHROUGH    2
  50 #define CPOLICY_WRITEBACK       3
  51 #define CPOLICY_WRITEALLOC      4
  52
  53 static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
  54 static unsigned int ecc_mask __initdata = 0;
  55 pgprot_t pgprot_user;
  56 pgprot_t pgprot_kernel;
  57
  58 EXPORT_SYMBOL(pgprot_user);
  59 EXPORT_SYMBOL(pgprot_kernel);
  60
  61 struct cachepolicy {
  62         const char      policy[16];
  63         unsigned int    cr_mask;
  64         unsigned int    pmd;
  65         unsigned int    pte;
  66 };
  67
  68 static struct cachepolicy cache_policies[] __initdata = {
  69         {
  70                 .policy         = "uncached",
  71                 .cr_mask        = CR_W|CR_C,
  72                 .pmd            = PMD_SECT_UNCACHED,
  73                 .pte            = L_PTE_MT_UNCACHED,
  74         }, {
  75                 .policy         = "buffered",
  76                 .cr_mask        = CR_C,
  77                 .pmd            = PMD_SECT_BUFFERED,
  78                 .pte            = L_PTE_MT_BUFFERABLE,
  79         }, {
  80                 .policy         = "writethrough",
  81                 .cr_mask        = 0,
  82                 .pmd            = PMD_SECT_WT,
  83                 .pte            = L_PTE_MT_WRITETHROUGH,
  84         }, {
  85                 .policy         = "writeback",
  86                 .cr_mask        = 0,
  87                 .pmd            = PMD_SECT_WB,
  88                 .pte            = L_PTE_MT_WRITEBACK,
  89         }, {
  90                 .policy         = "writealloc",
  91                 .cr_mask        = 0,
  92                 .pmd            = PMD_SECT_WBWA,
  93                 .pte            = L_PTE_MT_WRITEALLOC,
  94         }
  95 };
  96
  97 /*
  98  * These are useful for identifying cache coherency
  99  * problems by allowing the cache or the cache and
 100  * writebuffer to be turned off.  (Note: the write
 101  * buffer should not be on and the cache off).
 102  */
 103 static int __init early_cachepolicy(char *p)
 104 {
 105         int i;
 106
 107         for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
 108                 int len = strlen(cache_policies[i].policy);
 109
 110                 if (memcmp(p, cache_policies[i].policy, len) == 0) {
 111                         cachepolicy = i;
 112                         cr_alignment &= ~cache_policies[i].cr_mask;
 113                         cr_no_alignment &= ~cache_policies[i].cr_mask;
 114                         break;
 115                 }
 116         }
 117         if (i == ARRAY_SIZE(cache_policies))
 118                 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
 119         /*
 120          * This restriction is partly to do with the way we boot; it is
 121          * unpredictable to have memory mapped using two different sets of
 122          * memory attributes (shared, type, and cache attribs).  We can not
 123          * change these attributes once the initial assembly has setup the
 124          * page tables.
 125          */
 126         if (cpu_architecture() >= CPU_ARCH_ARMv6) {
 127                 printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
 128                 cachepolicy = CPOLICY_WRITEBACK;
 129         }
 130         flush_cache_all();
 131         set_cr(cr_alignment);
 132         return 0;
 133 }
 134 early_param("cachepolicy", early_cachepolicy);
 135
 136 static int __init early_nocache(char *__unused)
 137 {
 138         char *p = "buffered";
 139         printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
 140         early_cachepolicy(p);
 141         return 0;
 142 }
 143 early_param("nocache", early_nocache);
 144
 145 static int __init early_nowrite(char *__unused)
 146 {
 147         char *p = "uncached";
 148         printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
 149         early_cachepolicy(p);
 150         return 0;
 151 }
 152 early_param("nowb", early_nowrite);
 153
 154 static int __init early_ecc(char *p)
 155 {
 156         if (memcmp(p, "on", 2) == 0)
 157                 ecc_mask = PMD_PROTECTION;
 158         else if (memcmp(p, "off", 3) == 0)
 159                 ecc_mask = 0;
 160         return 0;
 161 }
 162 early_param("ecc", early_ecc);
 163
 164 static int __init noalign_setup(char *__unused)
 165 {
 166         cr_alignment &= ~CR_A;
 167         cr_no_alignment &= ~CR_A;
 168         set_cr(cr_alignment);
 169         return 1;
 170 }
 171 __setup("noalign", noalign_setup);
 172
 173 #ifndef CONFIG_SMP
 174 void adjust_cr(unsigned long mask, unsigned long set)
 175 {
 176         unsigned long flags;
 177
 178         mask &= ~CR_A;
 179
 180         set &= mask;
 181
 182         local_irq_save(flags);
 183
 184         cr_no_alignment = (cr_no_alignment & ~mask) | set;
 185         cr_alignment = (cr_alignment & ~mask) | set;
 186
 187         set_cr((get_cr() & ~mask) | set);
 188
 189         local_irq_restore(flags);
 190 }
 191 #endif
 192
 193 #define PROT_PTE_DEVICE         L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_WRITE
 194 #define PROT_SECT_DEVICE        PMD_TYPE_SECT|PMD_SECT_AP_WRITE
 195
 196 static struct mem_type mem_types[] = {
 197         [MT_DEVICE] = {           /* Strongly ordered / ARMv6 shared device */
 198                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
 199                                   L_PTE_SHARED,
 200                 .prot_l1        = PMD_TYPE_TABLE,
 201                 .prot_sect      = PROT_SECT_DEVICE | PMD_SECT_S,
 202                 .domain         = DOMAIN_IO,
 203         },
 204         [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
 205                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
 206                 .prot_l1        = PMD_TYPE_TABLE,
 207                 .prot_sect      = PROT_SECT_DEVICE,
 208                 .domain         = DOMAIN_IO,
 209         },
 210         [MT_DEVICE_CACHED] = {    /* ioremap_cached */
 211                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
 212                 .prot_l1        = PMD_TYPE_TABLE,
 213                 .prot_sect      = PROT_SECT_DEVICE | PMD_SECT_WB,
 214                 .domain         = DOMAIN_IO,
 215         },
 216         [MT_DEVICE_WC] = {      /* ioremap_wc */
 217                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
 218                 .prot_l1        = PMD_TYPE_TABLE,
 219                 .prot_sect      = PROT_SECT_DEVICE,
 220                 .domain         = DOMAIN_IO,
 221         },
 222         [MT_UNCACHED] = {
 223                 .prot_pte       = PROT_PTE_DEVICE,
 224                 .prot_l1        = PMD_TYPE_TABLE,
 225                 .prot_sect      = PMD_TYPE_SECT | PMD_SECT_XN,
 226                 .domain         = DOMAIN_IO,
 227         },
 228         [MT_CACHECLEAN] = {
 229                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
 230                 .domain    = DOMAIN_KERNEL,
 231         },
 232         [MT_MINICLEAN] = {
 233                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
 234                 .domain    = DOMAIN_KERNEL,
 235         },
 236         [MT_LOW_VECTORS] = {
 237                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 238                                 L_PTE_EXEC,
 239                 .prot_l1   = PMD_TYPE_TABLE,
 240                 .domain    = DOMAIN_USER,
 241         },
 242         [MT_HIGH_VECTORS] = {
 243                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 244                                 L_PTE_USER | L_PTE_EXEC,
 245                 .prot_l1   = PMD_TYPE_TABLE,
 246                 .domain    = DOMAIN_USER,
 247         },
 248         [MT_MEMORY] = {
 249                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
 250                 .domain    = DOMAIN_KERNEL,
 251         },
 252         [MT_ROM] = {
 253                 .prot_sect = PMD_TYPE_SECT,
 254                 .domain    = DOMAIN_KERNEL,
 255         },
 256         [MT_MEMORY_NONCACHED] = {
 257                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
 258                 .domain    = DOMAIN_KERNEL,
 259         },
 260 };
 261
 262 const struct mem_type *get_mem_type(unsigned int type)
 263 {
 264         return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
 265 }
 266 EXPORT_SYMBOL(get_mem_type);
 267
 268 /*
 269  * Adjust the PMD section entries according to the CPU in use.
 270  */
 271 static void __init build_mem_type_table(void)
 272 {
 273         struct cachepolicy *cp;
 274         unsigned int cr = get_cr();
 275         unsigned int user_pgprot, kern_pgprot, vecs_pgprot;
 276         int cpu_arch = cpu_architecture();
 277         int i;
 278
 279         if (cpu_arch < CPU_ARCH_ARMv6) {
 280 #if defined(CONFIG_CPU_DCACHE_DISABLE)
 281                 if (cachepolicy > CPOLICY_BUFFERED)
 282                         cachepolicy = CPOLICY_BUFFERED;
 283 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
 284                 if (cachepolicy > CPOLICY_WRITETHROUGH)
 285                         cachepolicy = CPOLICY_WRITETHROUGH;
 286 #endif
 287         }
 288         if (cpu_arch < CPU_ARCH_ARMv5) {
 289                 if (cachepolicy >= CPOLICY_WRITEALLOC)
 290                         cachepolicy = CPOLICY_WRITEBACK;
 291                 ecc_mask = 0;
 292         }
 293 #ifdef CONFIG_SMP
 294         cachepolicy = CPOLICY_WRITEALLOC;
 295 #endif
 296
 297         /*
 298          * Strip out features not present on earlier architectures.
 299          * Pre-ARMv5 CPUs don't have TEX bits.  Pre-ARMv6 CPUs or those
 300          * without extended page tables don't have the 'Shared' bit.
 301          */
 302         if (cpu_arch < CPU_ARCH_ARMv5)
 303                 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
 304                         mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
 305         if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
 306                 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
 307                         mem_types[i].prot_sect &= ~PMD_SECT_S;
 308
 309         /*
 310          * ARMv5 and lower, bit 4 must be set for page tables (was: cache
 311          * "update-able on write" bit on ARM610).  However, Xscale and
 312          * Xscale3 require this bit to be cleared.
 313          */
 314         if (cpu_is_xscale() || cpu_is_xsc3()) {
 315                 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
 316                         mem_types[i].prot_sect &= ~PMD_BIT4;
 317                         mem_types[i].prot_l1 &= ~PMD_BIT4;
 318                 }
 319         } else if (cpu_arch < CPU_ARCH_ARMv6) {
 320                 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
 321                         if (mem_types[i].prot_l1)
 322                                 mem_types[i].prot_l1 |= PMD_BIT4;
 323                         if (mem_types[i].prot_sect)
 324                                 mem_types[i].prot_sect |= PMD_BIT4;
 325                 }
 326         }
 327
 328         /*
 329          * Mark the device areas according to the CPU/architecture.
 330          */
 331         if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
 332                 if (!cpu_is_xsc3()) {
 333                         /*
 334                          * Mark device regions on ARMv6+ as execute-never
 335                          * to prevent speculative instruction fetches.
 336                          */
 337                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
 338                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
 339                         mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
 340                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
 341                 }
 342                 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
 343                         /*
 344                          * For ARMv7 with TEX remapping,
 345                          * - shared device is SXCB=1100
 346                          * - nonshared device is SXCB=0100
 347                          * - write combine device mem is SXCB=0001
 348                          * (Uncached Normal memory)
 349                          */
 350                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
 351                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
 352                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
 353                 } else if (cpu_is_xsc3()) {
 354                         /*
 355                          * For Xscale3,
 356                          * - shared device is TEXCB=00101
 357                          * - nonshared device is TEXCB=01000
 358                          * - write combine device mem is TEXCB=00100
 359                          * (Inner/Outer Uncacheable in xsc3 parlance)
 360                          */
 361                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
 362                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
 363                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
 364                 } else {
 365                         /*
 366                          * For ARMv6 and ARMv7 without TEX remapping,
 367                          * - shared device is TEXCB=00001
 368                          * - nonshared device is TEXCB=01000
 369                          * - write combine device mem is TEXCB=00100
 370                          * (Uncached Normal in ARMv6 parlance).
 371                          */
 372                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
 373                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
 374                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
 375                 }
 376         } else {
 377                 /*
 378                  * On others, write combining is "Uncached/Buffered"
 379                  */
 380                 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
 381         }
 382
 383         /*
 384          * Now deal with the memory-type mappings
 385          */
 386         cp = &cache_policies[cachepolicy];
 387         vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
 388
 389 #ifndef CONFIG_SMP
 390         /*
 391          * Only use write-through for non-SMP systems
 392          */
 393         if (cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH)
 394                 vecs_pgprot = cache_policies[CPOLICY_WRITETHROUGH].pte;
 395 #endif
 396
 397         /*
 398          * Enable CPU-specific coherency if supported.
 399          * (Only available on XSC3 at the moment.)
 400          */
 401         if (arch_is_coherent() && cpu_is_xsc3())
 402                 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
 403
 404         /*
 405          * ARMv6 and above have extended page tables.
 406          */
 407         if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
 408                 /*
 409                  * Mark cache clean areas and XIP ROM read only
 410                  * from SVC mode and no access from userspace.
 411                  */
 412                 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 413                 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 414                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 415
 416 #ifdef CONFIG_SMP
 417                 /*
 418                  * Mark memory with the "shared" attribute for SMP systems
 419                  */
 420                 user_pgprot |= L_PTE_SHARED;
 421                 kern_pgprot |= L_PTE_SHARED;
 422                 vecs_pgprot |= L_PTE_SHARED;
 423                 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
 424                 mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
 425                 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
 426                 mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
 427                 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
 428                 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
 429 #endif
 430         }
 431
 432         /*
 433          * Non-cacheable Normal - intended for memory areas that must
 434          * not cause dirty cache line writebacks when used
 435          */
 436         if (cpu_arch >= CPU_ARCH_ARMv6) {
 437                 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
 438                         /* Non-cacheable Normal is XCB = 001 */
 439                         mem_types[MT_MEMORY_NONCACHED].prot_sect |=
 440                                 PMD_SECT_BUFFERED;
 441                 } else {
 442                         /* For both ARMv6 and non-TEX-remapping ARMv7 */
 443                         mem_types[MT_MEMORY_NONCACHED].prot_sect |=
 444                                 PMD_SECT_TEX(1);
 445                 }
 446         } else {
 447                 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
 448         }
 449
 450         for (i = 0; i < 16; i++) {
 451                 unsigned long v = pgprot_val(protection_map[i]);
 452                 protection_map[i] = __pgprot(v | user_pgprot);
 453         }
 454
 455         mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
 456         mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
 457
 458         pgprot_user   = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
 459         pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
 460                                  L_PTE_DIRTY | L_PTE_WRITE | kern_pgprot);
 461
 462         mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
 463         mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
 464         mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
 465         mem_types[MT_ROM].prot_sect |= cp->pmd;
 466
 467         switch (cp->pmd) {
 468         case PMD_SECT_WT:
 469                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
 470                 break;
 471         case PMD_SECT_WB:
 472         case PMD_SECT_WBWA:
 473                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
 474                 break;
 475         }
 476         printk("Memory policy: ECC %sabled, Data cache %s\n",
 477                 ecc_mask ? "en" : "dis", cp->policy);
 478
 479         for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
 480                 struct mem_type *t = &mem_types[i];
 481                 if (t->prot_l1)
 482                         t->prot_l1 |= PMD_DOMAIN(t->domain);
 483                 if (t->prot_sect)
 484                         t->prot_sect |= PMD_DOMAIN(t->domain);
 485         }
 486 }
 487
 488 #define vectors_base()  (vectors_high() ? 0xffff0000 : 0)
 489
 490 static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
 491                                   unsigned long end, unsigned long pfn,
 492                                   const struct mem_type *type)
 493 {
 494         pte_t *pte;
 495
 496         if (pmd_none(*pmd)) {
 497                 pte = alloc_bootmem_low_pages(2 * PTRS_PER_PTE * sizeof(pte_t));
 498                 __pmd_populate(pmd, __pa(pte) | type->prot_l1);
 499         }
 500
 501         pte = pte_offset_kernel(pmd, addr);
 502         do {
 503                 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0);
 504                 pfn++;
 505         } while (pte++, addr += PAGE_SIZE, addr != end);
 506 }
 507
 508 static void __init alloc_init_section(pgd_t *pgd, unsigned long addr,
 509                                       unsigned long end, unsigned long phys,
 510                                       const struct mem_type *type)
 511 {
 512         pmd_t *pmd = pmd_offset(pgd, addr);
 513
 514         /*
 515          * Try a section mapping - end, addr and phys must all be aligned
 516          * to a section boundary.  Note that PMDs refer to the individual
 517          * L1 entries, whereas PGDs refer to a group of L1 entries making
 518          * up one logical pointer to an L2 table.
 519          */
 520         if (((addr | end | phys) & ~SECTION_MASK) == 0) {
 521                 pmd_t *p = pmd;
 522
 523                 if (addr & SECTION_SIZE)
 524                         pmd++;
 525
 526                 do {
 527                         *pmd = __pmd(phys | type->prot_sect);
 528                         phys += SECTION_SIZE;
 529                 } while (pmd++, addr += SECTION_SIZE, addr != end);
 530
 531                 flush_pmd_entry(p);
 532         } else {
 533                 /*
 534                  * No need to loop; pte's aren't interested in the
 535                  * individual L1 entries.
 536                  */
 537                 alloc_init_pte(pmd, addr, end, __phys_to_pfn(phys), type);
 538         }
 539 }
 540
 541 static void __init create_36bit_mapping(struct map_desc *md,
 542                                         const struct mem_type *type)
 543 {
 544         unsigned long phys, addr, length, end;
 545         pgd_t *pgd;
 546
 547         addr = md->virtual;
 548         phys = (unsigned long)__pfn_to_phys(md->pfn);
 549         length = PAGE_ALIGN(md->length);
 550
 551         if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
 552                 printk(KERN_ERR "MM: CPU does not support supersection "
 553                        "mapping for 0x%08llx at 0x%08lx\n",
 554                        __pfn_to_phys((u64)md->pfn), addr);
 555                 return;
 556         }
 557
 558         /* N.B. ARMv6 supersections are only defined to work with domain 0.
 559          *      Since domain assignments can in fact be arbitrary, the
 560          *      'domain == 0' check below is required to insure that ARMv6
 561          *      supersections are only allocated for domain 0 regardless
 562          *      of the actual domain assignments in use.
 563          */
 564         if (type->domain) {
 565                 printk(KERN_ERR "MM: invalid domain in supersection "
 566                        "mapping for 0x%08llx at 0x%08lx\n",
 567                        __pfn_to_phys((u64)md->pfn), addr);
 568                 return;
 569         }
 570
 571         if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
 572                 printk(KERN_ERR "MM: cannot create mapping for "
 573                        "0x%08llx at 0x%08lx invalid alignment\n",
 574                        __pfn_to_phys((u64)md->pfn), addr);
 575                 return;
 576         }
 577
 578         /*
 579          * Shift bits [35:32] of address into bits [23:20] of PMD
 580          * (See ARMv6 spec).
 581          */
 582         phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
 583
 584         pgd = pgd_offset_k(addr);
 585         end = addr + length;
 586         do {
 587                 pmd_t *pmd = pmd_offset(pgd, addr);
 588                 int i;
 589
 590                 for (i = 0; i < 16; i++)
 591                         *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER);
 592
 593                 addr += SUPERSECTION_SIZE;
 594                 phys += SUPERSECTION_SIZE;
 595                 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
 596         } while (addr != end);
 597 }
 598
 599 /*
 600  * Create the page directory entries and any necessary
 601  * page tables for the mapping specified by `md'.  We
 602  * are able to cope here with varying sizes and address
 603  * offsets, and we take full advantage of sections and
 604  * supersections.
 605  */
 606 void __init create_mapping(struct map_desc *md)
 607 {
 608         unsigned long phys, addr, length, end;
 609         const struct mem_type *type;
 610         pgd_t *pgd;
 611
 612         if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
 613                 printk(KERN_WARNING "BUG: not creating mapping for "
 614                        "0x%08llx at 0x%08lx in user region\n",
 615                        __pfn_to_phys((u64)md->pfn), md->virtual);
 616                 return;
 617         }
 618
 619         if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
 620             md->virtual >= PAGE_OFFSET && md->virtual < VMALLOC_END) {
 621                 printk(KERN_WARNING "BUG: mapping for 0x%08llx at 0x%08lx "
 622                        "overlaps vmalloc space\n",
 623                        __pfn_to_phys((u64)md->pfn), md->virtual);
 624         }
 625
 626         type = &mem_types[md->type];
 627
 628         /*
 629          * Catch 36-bit addresses
 630          */
 631         if (md->pfn >= 0x100000) {
 632                 create_36bit_mapping(md, type);
 633                 return;
 634         }
 635
 636         addr = md->virtual & PAGE_MASK;
 637         phys = (unsigned long)__pfn_to_phys(md->pfn);
 638         length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
 639
 640         if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
 641                 printk(KERN_WARNING "BUG: map for 0x%08lx at 0x%08lx can not "
 642                        "be mapped using pages, ignoring.\n",
 643                        __pfn_to_phys(md->pfn), addr);
 644                 return;
 645         }
 646
 647         pgd = pgd_offset_k(addr);
 648         end = addr + length;
 649         do {
 650                 unsigned long next = pgd_addr_end(addr, end);
 651
 652                 alloc_init_section(pgd, addr, next, phys, type);
 653
 654                 phys += next - addr;
 655                 addr = next;
 656         } while (pgd++, addr != end);
 657 }
 658
 659 /*
 660  * Create the architecture specific mappings
 661  */
 662 void __init iotable_init(struct map_desc *io_desc, int nr)
 663 {
 664         int i;
 665
 666         for (i = 0; i < nr; i++)
 667                 create_mapping(io_desc + i);
 668 }
 669
 670 static unsigned long __initdata vmalloc_reserve = SZ_128M;
 671
 672 /*
 673  * vmalloc=size forces the vmalloc area to be exactly 'size'
 674  * bytes. This can be used to increase (or decrease) the vmalloc
 675  * area - the default is 128m.
 676  */
 677 static int __init early_vmalloc(char *arg)
 678 {
 679         vmalloc_reserve = memparse(arg, NULL);
 680
 681         if (vmalloc_reserve < SZ_16M) {
 682                 vmalloc_reserve = SZ_16M;
 683                 printk(KERN_WARNING
 684                         "vmalloc area too small, limiting to %luMB\n",
 685                         vmalloc_reserve >> 20);
 686         }
 687
 688         if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) {
 689                 vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M);
 690                 printk(KERN_WARNING
 691                         "vmalloc area is too big, limiting to %luMB\n",
 692                         vmalloc_reserve >> 20);
 693         }
 694         return 0;
 695 }
 696 early_param("vmalloc", early_vmalloc);
 697
 698 #define VMALLOC_MIN     (void *)(VMALLOC_END - vmalloc_reserve)
 699
 700 static void __init sanity_check_meminfo(void)
 701 {
 702         int i, j, highmem = 0;
 703
 704         for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
 705                 struct membank *bank = &meminfo.bank[j];
 706                 *bank = meminfo.bank[i];
 707
 708 #ifdef CONFIG_HIGHMEM
 709                 if (__va(bank->start) > VMALLOC_MIN ||
 710                     __va(bank->start) < (void *)PAGE_OFFSET)
 711                         highmem = 1;
 712
 713                 bank->highmem = highmem;
 714
 715                 /*
 716                  * Split those memory banks which are partially overlapping
 717                  * the vmalloc area greatly simplifying things later.
 718                  */
 719                 if (__va(bank->start) < VMALLOC_MIN &&
 720                     bank->size > VMALLOC_MIN - __va(bank->start)) {
 721                         if (meminfo.nr_banks >= NR_BANKS) {
 722                                 printk(KERN_CRIT "NR_BANKS too low, "
 723                                                  "ignoring high memory\n");
 724                         } else {
 725                                 memmove(bank + 1, bank,
 726                                         (meminfo.nr_banks - i) * sizeof(*bank));
 727                                 meminfo.nr_banks++;
 728                                 i++;
 729                                 bank[1].size -= VMALLOC_MIN - __va(bank->start);
 730                                 bank[1].start = __pa(VMALLOC_MIN - 1) + 1;
 731                                 bank[1].highmem = highmem = 1;
 732                                 j++;
 733                         }
 734                         bank->size = VMALLOC_MIN - __va(bank->start);
 735                 }
 736 #else
 737                 bank->highmem = highmem;
 738
 739                 /*
 740                  * Check whether this memory bank would entirely overlap
 741                  * the vmalloc area.
 742                  */
 743                 if (__va(bank->start) >= VMALLOC_MIN ||
 744                     __va(bank->start) < (void *)PAGE_OFFSET) {
 745                         printk(KERN_NOTICE "Ignoring RAM at %.8lx-%.8lx "
 746                                "(vmalloc region overlap).\n",
 747                                bank->start, bank->start + bank->size - 1);
 748                         continue;
 749                 }
 750
 751                 /*
 752                  * Check whether this memory bank would partially overlap
 753                  * the vmalloc area.
 754                  */
 755                 if (__va(bank->start + bank->size) > VMALLOC_MIN ||
 756                     __va(bank->start + bank->size) < __va(bank->start)) {
 757                         unsigned long newsize = VMALLOC_MIN - __va(bank->start);
 758                         printk(KERN_NOTICE "Truncating RAM at %.8lx-%.8lx "
 759                                "to -%.8lx (vmalloc region overlap).\n",
 760                                bank->start, bank->start + bank->size - 1,
 761                                bank->start + newsize - 1);
 762                         bank->size = newsize;
 763                 }
 764 #endif
 765                 j++;
 766         }
 767 #ifdef CONFIG_HIGHMEM
 768         if (highmem) {
 769                 const char *reason = NULL;
 770
 771                 if (cache_is_vipt_aliasing()) {
 772                         /*
 773                          * Interactions between kmap and other mappings
 774                          * make highmem support with aliasing VIPT caches
 775                          * rather difficult.
 776                          */
 777                         reason = "with VIPT aliasing cache";
 778 #ifdef CONFIG_SMP
 779                 } else if (tlb_ops_need_broadcast()) {
 780                         /*
 781                          * kmap_high needs to occasionally flush TLB entries,
 782                          * however, if the TLB entries need to be broadcast
 783                          * we may deadlock:
 784                          *  kmap_high(irqs off)->flush_all_zero_pkmaps->
 785                          *  flush_tlb_kernel_range->smp_call_function_many
 786                          *   (must not be called with irqs off)
 787                          */
 788                         reason = "without hardware TLB ops broadcasting";
 789 #endif
 790                 }
 791                 if (reason) {
 792                         printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n",
 793                                 reason);
 794                         while (j > 0 && meminfo.bank[j - 1].highmem)
 795                                 j--;
 796                 }
 797         }
 798 #endif
 799         meminfo.nr_banks = j;
 800 }
 801
 802 static inline void prepare_page_table(void)
 803 {
 804         unsigned long addr;
 805
 806         /*
 807          * Clear out all the mappings below the kernel image.
 808          */
 809         for (addr = 0; addr < MODULES_VADDR; addr += PGDIR_SIZE)
 810                 pmd_clear(pmd_off_k(addr));
 811
 812 #ifdef CONFIG_XIP_KERNEL
 813         /* The XIP kernel is mapped in the module area -- skip over it */
 814         addr = ((unsigned long)_etext + PGDIR_SIZE - 1) & PGDIR_MASK;
 815 #endif
 816         for ( ; addr < PAGE_OFFSET; addr += PGDIR_SIZE)
 817                 pmd_clear(pmd_off_k(addr));
 818
 819         /*
 820          * Clear out all the kernel space mappings, except for the first
 821          * memory bank, up to the end of the vmalloc region.
 822          */
 823         for (addr = __phys_to_virt(bank_phys_end(&meminfo.bank[0]));
 824              addr < VMALLOC_END; addr += PGDIR_SIZE)
 825                 pmd_clear(pmd_off_k(addr));
 826 }
 827
 828 /*
 829  * Reserve the various regions of node 0
 830  */
 831 void __init reserve_node_zero(pg_data_t *pgdat)
 832 {
 833         unsigned long res_size = 0;
 834
 835         /*
 836          * Register the kernel text and data with bootmem.
 837          * Note that this can only be in node 0.
 838          */
 839 #ifdef CONFIG_XIP_KERNEL
 840         reserve_bootmem_node(pgdat, __pa(_data), _end - _data,
 841                         BOOTMEM_DEFAULT);
 842 #else
 843         reserve_bootmem_node(pgdat, __pa(_stext), _end - _stext,
 844                         BOOTMEM_DEFAULT);
 845 #endif
 846
 847         /*
 848          * Reserve the page tables.  These are already in use,
 849          * and can only be in node 0.
 850          */
 851         reserve_bootmem_node(pgdat, __pa(swapper_pg_dir),
 852                              PTRS_PER_PGD * sizeof(pgd_t), BOOTMEM_DEFAULT);
 853
 854         /*
 855          * Hmm... This should go elsewhere, but we really really need to
 856          * stop things allocating the low memory; ideally we need a better
 857          * implementation of GFP_DMA which does not assume that DMA-able
 858          * memory starts at zero.
 859          */
 860         if (machine_is_integrator() || machine_is_cintegrator())
 861                 res_size = __pa(swapper_pg_dir) - PHYS_OFFSET;
 862
 863         /*
 864          * These should likewise go elsewhere.  They pre-reserve the
 865          * screen memory region at the start of main system memory.
 866          */
 867         if (machine_is_edb7211())
 868                 res_size = 0x00020000;
 869         if (machine_is_p720t())
 870                 res_size = 0x00014000;
 871
 872         /* H1940 and RX3715 need to reserve this for suspend */
 873
 874         if (machine_is_h1940() || machine_is_rx3715()) {
 875                 reserve_bootmem_node(pgdat, 0x30003000, 0x1000,
 876                                 BOOTMEM_DEFAULT);
 877                 reserve_bootmem_node(pgdat, 0x30081000, 0x1000,
 878                                 BOOTMEM_DEFAULT);
 879         }
 880
 881         if (machine_is_palmld() || machine_is_palmtx()) {
 882                 reserve_bootmem_node(pgdat, 0xa0000000, 0x1000,
 883                                 BOOTMEM_EXCLUSIVE);
 884                 reserve_bootmem_node(pgdat, 0xa0200000, 0x1000,
 885                                 BOOTMEM_EXCLUSIVE);
 886         }
 887
 888         if (machine_is_treo680() || machine_is_centro()) {
 889                 reserve_bootmem_node(pgdat, 0xa0000000, 0x1000,
 890                                 BOOTMEM_EXCLUSIVE);
 891                 reserve_bootmem_node(pgdat, 0xa2000000, 0x1000,
 892                                 BOOTMEM_EXCLUSIVE);
 893         }
 894
 895         if (machine_is_palmt5())
 896                 reserve_bootmem_node(pgdat, 0xa0200000, 0x1000,
 897                                 BOOTMEM_EXCLUSIVE);
 898
 899         /*
 900          * U300 - This platform family can share physical memory
 901          * between two ARM cpus, one running Linux and the other
 902          * running another OS.
 903          */
 904         if (machine_is_u300()) {
 905 #ifdef CONFIG_MACH_U300_SINGLE_RAM
 906 #if ((CONFIG_MACH_U300_ACCESS_MEM_SIZE & 1) == 1) &&    \
 907         CONFIG_MACH_U300_2MB_ALIGNMENT_FIX
 908                 res_size = 0x00100000;
 909 #endif
 910 #endif
 911         }
 912
 913 #ifdef CONFIG_SA1111
 914         /*
 915          * Because of the SA1111 DMA bug, we want to preserve our
 916          * precious DMA-able memory...
 917          */
 918         res_size = __pa(swapper_pg_dir) - PHYS_OFFSET;
 919 #endif
 920         if (res_size)
 921                 reserve_bootmem_node(pgdat, PHYS_OFFSET, res_size,
 922                                 BOOTMEM_DEFAULT);
 923 }
 924
 925 /*
 926  * Set up device the mappings.  Since we clear out the page tables for all
 927  * mappings above VMALLOC_END, we will remove any debug device mappings.
 928  * This means you have to be careful how you debug this function, or any
 929  * called function.  This means you can't use any function or debugging
 930  * method which may touch any device, otherwise the kernel _will_ crash.
 931  */
 932 static void __init devicemaps_init(struct machine_desc *mdesc)
 933 {
 934         struct map_desc map;
 935         unsigned long addr;
 936         void *vectors;
 937
 938         /*
 939          * Allocate the vector page early.
 940          */
 941         vectors = alloc_bootmem_low_pages(PAGE_SIZE);
 942
 943         for (addr = VMALLOC_END; addr; addr += PGDIR_SIZE)
 944                 pmd_clear(pmd_off_k(addr));
 945
 946         /*
 947          * Map the kernel if it is XIP.
 948          * It is always first in the modulearea.
 949          */
 950 #ifdef CONFIG_XIP_KERNEL
 951         map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
 952         map.virtual = MODULES_VADDR;
 953         map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK;
 954         map.type = MT_ROM;
 955         create_mapping(&map);
 956 #endif
 957
 958         /*
 959          * Map the cache flushing regions.
 960          */
 961 #ifdef FLUSH_BASE
 962         map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
 963         map.virtual = FLUSH_BASE;
 964         map.length = SZ_1M;
 965         map.type = MT_CACHECLEAN;
 966         create_mapping(&map);
 967 #endif
 968 #ifdef FLUSH_BASE_MINICACHE
 969         map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
 970         map.virtual = FLUSH_BASE_MINICACHE;
 971         map.length = SZ_1M;
 972         map.type = MT_MINICLEAN;
 973         create_mapping(&map);
 974 #endif
 975
 976         /*
 977          * Create a mapping for the machine vectors at the high-vectors
 978          * location (0xffff0000).  If we aren't using high-vectors, also
 979          * create a mapping at the low-vectors virtual address.
 980          */
 981         map.pfn = __phys_to_pfn(virt_to_phys(vectors));
 982         map.virtual = 0xffff0000;
 983         map.length = PAGE_SIZE;
 984         map.type = MT_HIGH_VECTORS;
 985         create_mapping(&map);
 986
 987         if (!vectors_high()) {
 988                 map.virtual = 0;
 989                 map.type = MT_LOW_VECTORS;
 990                 create_mapping(&map);
 991         }
 992
 993         /*
 994          * Ask the machine support to map in the statically mapped devices.
 995          */
 996         if (mdesc->map_io)
 997                 mdesc->map_io();
 998
 999         /*
1000          * Finally flush the caches and tlb to ensure that we're in a
1001          * consistent state wrt the writebuffer.  This also ensures that
1002          * any write-allocated cache lines in the vector page are written
1003          * back.  After this point, we can start to touch devices again.
1004          */
1005         local_flush_tlb_all();
1006         flush_cache_all();
1007 }
1008
1009 static void __init kmap_init(void)
1010 {
1011 #ifdef CONFIG_HIGHMEM
1012         pmd_t *pmd = pmd_off_k(PKMAP_BASE);
1013         pte_t *pte = alloc_bootmem_low_pages(2 * PTRS_PER_PTE * sizeof(pte_t));
1014         BUG_ON(!pmd_none(*pmd) || !pte);
1015         __pmd_populate(pmd, __pa(pte) | _PAGE_KERNEL_TABLE);
1016         pkmap_page_table = pte + PTRS_PER_PTE;
1017 #endif
1018 }
1019
1020 /*
1021  * paging_init() sets up the page tables, initialises the zone memory
1022  * maps, and sets up the zero page, bad page and bad page tables.
1023  */
1024 void __init paging_init(struct machine_desc *mdesc)
1025 {
1026         void *zero_page;
1027
1028         build_mem_type_table();
1029         sanity_check_meminfo();
1030         prepare_page_table();
1031         bootmem_init();
1032         devicemaps_init(mdesc);
1033         kmap_init();
1034
1035         top_pmd = pmd_off_k(0xffff0000);
1036
1037         /*
1038          * allocate the zero page.  Note that this always succeeds and
1039          * returns a zeroed result.
1040          */
1041         zero_page = alloc_bootmem_low_pages(PAGE_SIZE);
1042         empty_zero_page = virt_to_page(zero_page);
1043         __flush_dcache_page(NULL, empty_zero_page);
1044 }
1045
1046 /*
1047  * In order to soft-boot, we need to insert a 1:1 mapping in place of
1048  * the user-mode pages.  This will then ensure that we have predictable
1049  * results when turning the mmu off
1050  */
1051 void setup_mm_for_reboot(char mode)
1052 {
1053         unsigned long base_pmdval;
1054         pgd_t *pgd;
1055         int i;
1056
1057         /*
1058          * We need to access to user-mode page tables here. For kernel threads
1059          * we don't have any user-mode mappings so we use the context that we
1060          * "borrowed".
1061          */
1062         pgd = current->active_mm->pgd;
1063
1064         base_pmdval = PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT;
1065         if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale())
1066                 base_pmdval |= PMD_BIT4;
1067
1068         for (i = 0; i < FIRST_USER_PGD_NR + USER_PTRS_PER_PGD; i++, pgd++) {
1069                 unsigned long pmdval = (i << PGDIR_SHIFT) | base_pmdval;
1070                 pmd_t *pmd;
1071
1072                 pmd = pmd_off(pgd, i << PGDIR_SHIFT);
1073                 pmd[0] = __pmd(pmdval);
1074                 pmd[1] = __pmd(pmdval + (1 << (PGDIR_SHIFT - 1)));
1075                 flush_pmd_entry(pmd);
1076         }
1077
1078         local_flush_tlb_all();
1079 }