arch/arm/mm/mmu.c

   1 /*
   2  *  linux/arch/arm/mm/mmu.c
   3  *
   4  *  Copyright (C) 1995-2005 Russell King
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #include <linux/module.h>
  11 #include <linux/kernel.h>
  12 #include <linux/errno.h>
  13 #include <linux/init.h>
  14 #include <linux/mman.h>
  15 #include <linux/nodemask.h>
  16 #include <linux/memblock.h>
  17 #include <linux/fs.h>
  18 #include <linux/vmalloc.h>
  19
  20 #include <asm/cputype.h>
  21 #include <asm/sections.h>
  22 #include <asm/cachetype.h>
  23 #include <asm/setup.h>
  24 #include <asm/sizes.h>
  25 #include <asm/smp_plat.h>
  26 #include <asm/tlb.h>
  27 #include <asm/highmem.h>
  28 #include <asm/traps.h>
  29
  30 #include <asm/mach/arch.h>
  31 #include <asm/mach/map.h>
  32
  33 #include "mm.h"
  34
  35 /*
  36  * empty_zero_page is a special page that is used for
  37  * zero-initialized data and COW.
  38  */
  39 struct page *empty_zero_page;
  40 EXPORT_SYMBOL(empty_zero_page);
  41
  42 /*
  43  * The pmd table for the upper-most set of pages.
  44  */
  45 pmd_t *top_pmd;
  46
  47 #define CPOLICY_UNCACHED        0
  48 #define CPOLICY_BUFFERED        1
  49 #define CPOLICY_WRITETHROUGH    2
  50 #define CPOLICY_WRITEBACK       3
  51 #define CPOLICY_WRITEALLOC      4
  52
  53 static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
  54 static unsigned int ecc_mask __initdata = 0;
  55 pgprot_t pgprot_user;
  56 pgprot_t pgprot_kernel;
  57
  58 EXPORT_SYMBOL(pgprot_user);
  59 EXPORT_SYMBOL(pgprot_kernel);
  60
  61 struct cachepolicy {
  62         const char      policy[16];
  63         unsigned int    cr_mask;
  64         pmdval_t        pmd;
  65         pteval_t        pte;
  66 };
  67
  68 static struct cachepolicy cache_policies[] __initdata = {
  69         {
  70                 .policy         = "uncached",
  71                 .cr_mask        = CR_W|CR_C,
  72                 .pmd            = PMD_SECT_UNCACHED,
  73                 .pte            = L_PTE_MT_UNCACHED,
  74         }, {
  75                 .policy         = "buffered",
  76                 .cr_mask        = CR_C,
  77                 .pmd            = PMD_SECT_BUFFERED,
  78                 .pte            = L_PTE_MT_BUFFERABLE,
  79         }, {
  80                 .policy         = "writethrough",
  81                 .cr_mask        = 0,
  82                 .pmd            = PMD_SECT_WT,
  83                 .pte            = L_PTE_MT_WRITETHROUGH,
  84         }, {
  85                 .policy         = "writeback",
  86                 .cr_mask        = 0,
  87                 .pmd            = PMD_SECT_WB,
  88                 .pte            = L_PTE_MT_WRITEBACK,
  89         }, {
  90                 .policy         = "writealloc",
  91                 .cr_mask        = 0,
  92                 .pmd            = PMD_SECT_WBWA,
  93                 .pte            = L_PTE_MT_WRITEALLOC,
  94         }
  95 };
  96
  97 /*
  98  * These are useful for identifying cache coherency
  99  * problems by allowing the cache or the cache and
 100  * writebuffer to be turned off.  (Note: the write
 101  * buffer should not be on and the cache off).
 102  */
 103 static int __init early_cachepolicy(char *p)
 104 {
 105         int i;
 106
 107         for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
 108                 int len = strlen(cache_policies[i].policy);
 109
 110                 if (memcmp(p, cache_policies[i].policy, len) == 0) {
 111                         cachepolicy = i;
 112                         cr_alignment &= ~cache_policies[i].cr_mask;
 113                         cr_no_alignment &= ~cache_policies[i].cr_mask;
 114                         break;
 115                 }
 116         }
 117         if (i == ARRAY_SIZE(cache_policies))
 118                 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
 119         /*
 120          * This restriction is partly to do with the way we boot; it is
 121          * unpredictable to have memory mapped using two different sets of
 122          * memory attributes (shared, type, and cache attribs).  We can not
 123          * change these attributes once the initial assembly has setup the
 124          * page tables.
 125          */
 126         if (cpu_architecture() >= CPU_ARCH_ARMv6) {
 127                 printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
 128                 cachepolicy = CPOLICY_WRITEBACK;
 129         }
 130         flush_cache_all();
 131         set_cr(cr_alignment);
 132         return 0;
 133 }
 134 early_param("cachepolicy", early_cachepolicy);
 135
 136 static int __init early_nocache(char *__unused)
 137 {
 138         char *p = "buffered";
 139         printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
 140         early_cachepolicy(p);
 141         return 0;
 142 }
 143 early_param("nocache", early_nocache);
 144
 145 static int __init early_nowrite(char *__unused)
 146 {
 147         char *p = "uncached";
 148         printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
 149         early_cachepolicy(p);
 150         return 0;
 151 }
 152 early_param("nowb", early_nowrite);
 153
 154 #ifndef CONFIG_ARM_LPAE
 155 static int __init early_ecc(char *p)
 156 {
 157         if (memcmp(p, "on", 2) == 0)
 158                 ecc_mask = PMD_PROTECTION;
 159         else if (memcmp(p, "off", 3) == 0)
 160                 ecc_mask = 0;
 161         return 0;
 162 }
 163 early_param("ecc", early_ecc);
 164 #endif
 165
 166 static int __init noalign_setup(char *__unused)
 167 {
 168         cr_alignment &= ~CR_A;
 169         cr_no_alignment &= ~CR_A;
 170         set_cr(cr_alignment);
 171         return 1;
 172 }
 173 __setup("noalign", noalign_setup);
 174
 175 #ifndef CONFIG_SMP
 176 void adjust_cr(unsigned long mask, unsigned long set)
 177 {
 178         unsigned long flags;
 179
 180         mask &= ~CR_A;
 181
 182         set &= mask;
 183
 184         local_irq_save(flags);
 185
 186         cr_no_alignment = (cr_no_alignment & ~mask) | set;
 187         cr_alignment = (cr_alignment & ~mask) | set;
 188
 189         set_cr((get_cr() & ~mask) | set);
 190
 191         local_irq_restore(flags);
 192 }
 193 #endif
 194
 195 #define PROT_PTE_DEVICE         L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
 196 #define PROT_SECT_DEVICE        PMD_TYPE_SECT|PMD_SECT_AP_WRITE
 197
 198 static struct mem_type mem_types[] = {
 199         [MT_DEVICE] = {           /* Strongly ordered / ARMv6 shared device */
 200                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
 201                                   L_PTE_SHARED,
 202                 .prot_l1        = PMD_TYPE_TABLE,
 203                 .prot_sect      = PROT_SECT_DEVICE | PMD_SECT_S,
 204                 .domain         = DOMAIN_IO,
 205         },
 206         [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
 207                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
 208                 .prot_l1        = PMD_TYPE_TABLE,
 209                 .prot_sect      = PROT_SECT_DEVICE,
 210                 .domain         = DOMAIN_IO,
 211         },
 212         [MT_DEVICE_CACHED] = {    /* ioremap_cached */
 213                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
 214                 .prot_l1        = PMD_TYPE_TABLE,
 215                 .prot_sect      = PROT_SECT_DEVICE | PMD_SECT_WB,
 216                 .domain         = DOMAIN_IO,
 217         },
 218         [MT_DEVICE_WC] = {      /* ioremap_wc */
 219                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
 220                 .prot_l1        = PMD_TYPE_TABLE,
 221                 .prot_sect      = PROT_SECT_DEVICE,
 222                 .domain         = DOMAIN_IO,
 223         },
 224         [MT_UNCACHED] = {
 225                 .prot_pte       = PROT_PTE_DEVICE,
 226                 .prot_l1        = PMD_TYPE_TABLE,
 227                 .prot_sect      = PMD_TYPE_SECT | PMD_SECT_XN,
 228                 .domain         = DOMAIN_IO,
 229         },
 230         [MT_CACHECLEAN] = {
 231                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
 232                 .domain    = DOMAIN_KERNEL,
 233         },
 234 #ifndef CONFIG_ARM_LPAE
 235         [MT_MINICLEAN] = {
 236                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
 237                 .domain    = DOMAIN_KERNEL,
 238         },
 239 #endif
 240         [MT_LOW_VECTORS] = {
 241                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 242                                 L_PTE_RDONLY,
 243                 .prot_l1   = PMD_TYPE_TABLE,
 244                 .domain    = DOMAIN_USER,
 245         },
 246         [MT_HIGH_VECTORS] = {
 247                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 248                                 L_PTE_USER | L_PTE_RDONLY,
 249                 .prot_l1   = PMD_TYPE_TABLE,
 250                 .domain    = DOMAIN_USER,
 251         },
 252         [MT_MEMORY] = {
 253                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
 254                 .prot_l1   = PMD_TYPE_TABLE,
 255                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
 256                 .domain    = DOMAIN_KERNEL,
 257         },
 258         [MT_ROM] = {
 259                 .prot_sect = PMD_TYPE_SECT,
 260                 .domain    = DOMAIN_KERNEL,
 261         },
 262         [MT_MEMORY_NONCACHED] = {
 263                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 264                                 L_PTE_MT_BUFFERABLE,
 265                 .prot_l1   = PMD_TYPE_TABLE,
 266                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
 267                 .domain    = DOMAIN_KERNEL,
 268         },
 269         [MT_MEMORY_DTCM] = {
 270                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 271                                 L_PTE_XN,
 272                 .prot_l1   = PMD_TYPE_TABLE,
 273                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
 274                 .domain    = DOMAIN_KERNEL,
 275         },
 276         [MT_MEMORY_ITCM] = {
 277                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
 278                 .prot_l1   = PMD_TYPE_TABLE,
 279                 .domain    = DOMAIN_KERNEL,
 280         },
 281         [MT_MEMORY_SO] = {
 282                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 283                                 L_PTE_MT_UNCACHED,
 284                 .prot_l1   = PMD_TYPE_TABLE,
 285                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S |
 286                                 PMD_SECT_UNCACHED | PMD_SECT_XN,
 287                 .domain    = DOMAIN_KERNEL,
 288         },
 289         [MT_MEMORY_DMA_READY] = {
 290                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
 291                 .prot_l1   = PMD_TYPE_TABLE,
 292                 .domain    = DOMAIN_KERNEL,
 293         },
 294 };
 295
 296 const struct mem_type *get_mem_type(unsigned int type)
 297 {
 298         return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
 299 }
 300 EXPORT_SYMBOL(get_mem_type);
 301
 302 /*
 303  * Adjust the PMD section entries according to the CPU in use.
 304  */
 305 static void __init build_mem_type_table(void)
 306 {
 307         struct cachepolicy *cp;
 308         unsigned int cr = get_cr();
 309         pteval_t user_pgprot, kern_pgprot, vecs_pgprot;
 310         int cpu_arch = cpu_architecture();
 311         int i;
 312
 313         if (cpu_arch < CPU_ARCH_ARMv6) {
 314 #if defined(CONFIG_CPU_DCACHE_DISABLE)
 315                 if (cachepolicy > CPOLICY_BUFFERED)
 316                         cachepolicy = CPOLICY_BUFFERED;
 317 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
 318                 if (cachepolicy > CPOLICY_WRITETHROUGH)
 319                         cachepolicy = CPOLICY_WRITETHROUGH;
 320 #endif
 321         }
 322         if (cpu_arch < CPU_ARCH_ARMv5) {
 323                 if (cachepolicy >= CPOLICY_WRITEALLOC)
 324                         cachepolicy = CPOLICY_WRITEBACK;
 325                 ecc_mask = 0;
 326         }
 327         if (is_smp())
 328                 cachepolicy = CPOLICY_WRITEALLOC;
 329
 330         /*
 331          * Strip out features not present on earlier architectures.
 332          * Pre-ARMv5 CPUs don't have TEX bits.  Pre-ARMv6 CPUs or those
 333          * without extended page tables don't have the 'Shared' bit.
 334          */
 335         if (cpu_arch < CPU_ARCH_ARMv5)
 336                 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
 337                         mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
 338         if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
 339                 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
 340                         mem_types[i].prot_sect &= ~PMD_SECT_S;
 341
 342         /*
 343          * ARMv5 and lower, bit 4 must be set for page tables (was: cache
 344          * "update-able on write" bit on ARM610).  However, Xscale and
 345          * Xscale3 require this bit to be cleared.
 346          */
 347         if (cpu_is_xscale() || cpu_is_xsc3()) {
 348                 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
 349                         mem_types[i].prot_sect &= ~PMD_BIT4;
 350                         mem_types[i].prot_l1 &= ~PMD_BIT4;
 351                 }
 352         } else if (cpu_arch < CPU_ARCH_ARMv6) {
 353                 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
 354                         if (mem_types[i].prot_l1)
 355                                 mem_types[i].prot_l1 |= PMD_BIT4;
 356                         if (mem_types[i].prot_sect)
 357                                 mem_types[i].prot_sect |= PMD_BIT4;
 358                 }
 359         }
 360
 361         /*
 362          * Mark the device areas according to the CPU/architecture.
 363          */
 364         if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
 365                 if (!cpu_is_xsc3()) {
 366                         /*
 367                          * Mark device regions on ARMv6+ as execute-never
 368                          * to prevent speculative instruction fetches.
 369                          */
 370                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
 371                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
 372                         mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
 373                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
 374                 }
 375                 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
 376                         /*
 377                          * For ARMv7 with TEX remapping,
 378                          * - shared device is SXCB=1100
 379                          * - nonshared device is SXCB=0100
 380                          * - write combine device mem is SXCB=0001
 381                          * (Uncached Normal memory)
 382                          */
 383                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
 384                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
 385                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
 386                 } else if (cpu_is_xsc3()) {
 387                         /*
 388                          * For Xscale3,
 389                          * - shared device is TEXCB=00101
 390                          * - nonshared device is TEXCB=01000
 391                          * - write combine device mem is TEXCB=00100
 392                          * (Inner/Outer Uncacheable in xsc3 parlance)
 393                          */
 394                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
 395                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
 396                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
 397                 } else {
 398                         /*
 399                          * For ARMv6 and ARMv7 without TEX remapping,
 400                          * - shared device is TEXCB=00001
 401                          * - nonshared device is TEXCB=01000
 402                          * - write combine device mem is TEXCB=00100
 403                          * (Uncached Normal in ARMv6 parlance).
 404                          */
 405                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
 406                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
 407                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
 408                 }
 409         } else {
 410                 /*
 411                  * On others, write combining is "Uncached/Buffered"
 412                  */
 413                 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
 414         }
 415
 416         /*
 417          * Now deal with the memory-type mappings
 418          */
 419         cp = &cache_policies[cachepolicy];
 420         vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
 421
 422         /*
 423          * Only use write-through for non-SMP systems
 424          */
 425         if (!is_smp() && cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH)
 426                 vecs_pgprot = cache_policies[CPOLICY_WRITETHROUGH].pte;
 427
 428         /*
 429          * Enable CPU-specific coherency if supported.
 430          * (Only available on XSC3 at the moment.)
 431          */
 432         if (arch_is_coherent() && cpu_is_xsc3()) {
 433                 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
 434                 mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
 435                 mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED;
 436                 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
 437                 mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
 438         }
 439         /*
 440          * We don't use domains on ARMv6 (since this causes problems with
 441          * v6/v7 kernels), so we must use a separate memory type for user
 442          * r/o, kernel r/w to map the vectors page.
 443          */
 444         if (cpu_arch == CPU_ARCH_ARMv6)
 445                 vecs_pgprot |= L_PTE_MT_VECTORS;
 446
 447         /*
 448          * ARMv6 and above have extended page tables.
 449          */
 450         if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
 451 #ifndef CONFIG_ARM_LPAE
 452                 /*
 453                  * Mark cache clean areas and XIP ROM read only
 454                  * from SVC mode and no access from userspace.
 455                  */
 456                 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 457                 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 458                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 459 #endif
 460
 461                 if (is_smp()) {
 462                         /*
 463                          * Mark memory with the "shared" attribute
 464                          * for SMP systems
 465                          */
 466                         user_pgprot |= L_PTE_SHARED;
 467                         kern_pgprot |= L_PTE_SHARED;
 468                         vecs_pgprot |= L_PTE_SHARED;
 469                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
 470                         mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
 471                         mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
 472                         mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
 473                         mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
 474                         mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
 475                         mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED;
 476                         mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
 477                         mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
 478                 }
 479         }
 480
 481         /*
 482          * Non-cacheable Normal - intended for memory areas that must
 483          * not cause dirty cache line writebacks when used
 484          */
 485         if (cpu_arch >= CPU_ARCH_ARMv6) {
 486                 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
 487                         /* Non-cacheable Normal is XCB = 001 */
 488                         mem_types[MT_MEMORY_NONCACHED].prot_sect |=
 489                                 PMD_SECT_BUFFERED;
 490                 } else {
 491                         /* For both ARMv6 and non-TEX-remapping ARMv7 */
 492                         mem_types[MT_MEMORY_NONCACHED].prot_sect |=
 493                                 PMD_SECT_TEX(1);
 494                 }
 495         } else {
 496                 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
 497         }
 498
 499 #ifdef CONFIG_ARM_LPAE
 500         /*
 501          * Do not generate access flag faults for the kernel mappings.
 502          */
 503         for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
 504                 mem_types[i].prot_pte |= PTE_EXT_AF;
 505                 mem_types[i].prot_sect |= PMD_SECT_AF;
 506         }
 507         kern_pgprot |= PTE_EXT_AF;
 508         vecs_pgprot |= PTE_EXT_AF;
 509 #endif
 510
 511         for (i = 0; i < 16; i++) {
 512                 pteval_t v = pgprot_val(protection_map[i]);
 513                 protection_map[i] = __pgprot(v | user_pgprot);
 514         }
 515
 516         mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
 517         mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
 518
 519         pgprot_user   = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
 520         pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
 521                                  L_PTE_DIRTY | kern_pgprot);
 522
 523         mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
 524         mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
 525         mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
 526         mem_types[MT_MEMORY].prot_pte |= kern_pgprot;
 527         mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot;
 528         mem_types[MT_MEMORY_NONCACHED].prot_sect |= ecc_mask;
 529         mem_types[MT_ROM].prot_sect |= cp->pmd;
 530
 531         switch (cp->pmd) {
 532         case PMD_SECT_WT:
 533                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
 534                 break;
 535         case PMD_SECT_WB:
 536         case PMD_SECT_WBWA:
 537                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
 538                 break;
 539         }
 540         printk("Memory policy: ECC %sabled, Data cache %s\n",
 541                 ecc_mask ? "en" : "dis", cp->policy);
 542
 543         for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
 544                 struct mem_type *t = &mem_types[i];
 545                 if (t->prot_l1)
 546                         t->prot_l1 |= PMD_DOMAIN(t->domain);
 547                 if (t->prot_sect)
 548                         t->prot_sect |= PMD_DOMAIN(t->domain);
 549         }
 550 }
 551
 552 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
 553 pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
 554                               unsigned long size, pgprot_t vma_prot)
 555 {
 556         if (!pfn_valid(pfn))
 557                 return pgprot_noncached(vma_prot);
 558         else if (file->f_flags & O_SYNC)
 559                 return pgprot_writecombine(vma_prot);
 560         return vma_prot;
 561 }
 562 EXPORT_SYMBOL(phys_mem_access_prot);
 563 #endif
 564
 565 #define vectors_base()  (vectors_high() ? 0xffff0000 : 0)
 566
 567 static void __init *early_alloc_aligned(unsigned long sz, unsigned long align)
 568 {
 569         void *ptr = __va(memblock_alloc(sz, align));
 570         memset(ptr, 0, sz);
 571         return ptr;
 572 }
 573
 574 static void __init *early_alloc(unsigned long sz)
 575 {
 576         return early_alloc_aligned(sz, sz);
 577 }
 578
 579 static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot)
 580 {
 581         if (pmd_none(*pmd)) {
 582                 pte_t *pte = early_alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE);
 583                 __pmd_populate(pmd, __pa(pte), prot);
 584         }
 585         BUG_ON(pmd_bad(*pmd));
 586         return pte_offset_kernel(pmd, addr);
 587 }
 588
 589 static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
 590                                   unsigned long end, unsigned long pfn,
 591                                   const struct mem_type *type)
 592 {
 593         pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1);
 594         do {
 595                 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0);
 596                 pfn++;
 597         } while (pte++, addr += PAGE_SIZE, addr != end);
 598 }
 599
 600 static void __init alloc_init_section(pud_t *pud, unsigned long addr,
 601                                       unsigned long end, phys_addr_t phys,
 602                                       const struct mem_type *type)
 603 {
 604         pmd_t *pmd = pmd_offset(pud, addr);
 605
 606         /*
 607          * Try a section mapping - end, addr and phys must all be aligned
 608          * to a section boundary.  Note that PMDs refer to the individual
 609          * L1 entries, whereas PGDs refer to a group of L1 entries making
 610          * up one logical pointer to an L2 table.
 611          */
 612         if (type->prot_sect && ((addr | end | phys) & ~SECTION_MASK) == 0) {
 613                 pmd_t *p = pmd;
 614
 615 #ifndef CONFIG_ARM_LPAE
 616                 if (addr & SECTION_SIZE)
 617                         pmd++;
 618 #endif
 619
 620                 do {
 621                         *pmd = __pmd(phys | type->prot_sect);
 622                         phys += SECTION_SIZE;
 623                 } while (pmd++, addr += SECTION_SIZE, addr != end);
 624
 625                 flush_pmd_entry(p);
 626         } else {
 627                 /*
 628                  * No need to loop; pte's aren't interested in the
 629                  * individual L1 entries.
 630                  */
 631                 alloc_init_pte(pmd, addr, end, __phys_to_pfn(phys), type);
 632         }
 633 }
 634
 635 static void alloc_init_pud(pgd_t *pgd, unsigned long addr, unsigned long end,
 636         unsigned long phys, const struct mem_type *type)
 637 {
 638         pud_t *pud = pud_offset(pgd, addr);
 639         unsigned long next;
 640
 641         do {
 642                 next = pud_addr_end(addr, end);
 643                 alloc_init_section(pud, addr, next, phys, type);
 644                 phys += next - addr;
 645         } while (pud++, addr = next, addr != end);
 646 }
 647
 648 #ifndef CONFIG_ARM_LPAE
 649 static void __init create_36bit_mapping(struct map_desc *md,
 650                                         const struct mem_type *type)
 651 {
 652         unsigned long addr, length, end;
 653         phys_addr_t phys;
 654         pgd_t *pgd;
 655
 656         addr = md->virtual;
 657         phys = __pfn_to_phys(md->pfn);
 658         length = PAGE_ALIGN(md->length);
 659
 660         if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
 661                 printk(KERN_ERR "MM: CPU does not support supersection "
 662                        "mapping for 0x%08llx at 0x%08lx\n",
 663                        (long long)__pfn_to_phys((u64)md->pfn), addr);
 664                 return;
 665         }
 666
 667         /* N.B. ARMv6 supersections are only defined to work with domain 0.
 668          *      Since domain assignments can in fact be arbitrary, the
 669          *      'domain == 0' check below is required to insure that ARMv6
 670          *      supersections are only allocated for domain 0 regardless
 671          *      of the actual domain assignments in use.
 672          */
 673         if (type->domain) {
 674                 printk(KERN_ERR "MM: invalid domain in supersection "
 675                        "mapping for 0x%08llx at 0x%08lx\n",
 676                        (long long)__pfn_to_phys((u64)md->pfn), addr);
 677                 return;
 678         }
 679
 680         if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
 681                 printk(KERN_ERR "MM: cannot create mapping for 0x%08llx"
 682                        " at 0x%08lx invalid alignment\n",
 683                        (long long)__pfn_to_phys((u64)md->pfn), addr);
 684                 return;
 685         }
 686
 687         /*
 688          * Shift bits [35:32] of address into bits [23:20] of PMD
 689          * (See ARMv6 spec).
 690          */
 691         phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
 692
 693         pgd = pgd_offset_k(addr);
 694         end = addr + length;
 695         do {
 696                 pud_t *pud = pud_offset(pgd, addr);
 697                 pmd_t *pmd = pmd_offset(pud, addr);
 698                 int i;
 699
 700                 for (i = 0; i < 16; i++)
 701                         *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER);
 702
 703                 addr += SUPERSECTION_SIZE;
 704                 phys += SUPERSECTION_SIZE;
 705                 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
 706         } while (addr != end);
 707 }
 708 #endif  /* !CONFIG_ARM_LPAE */
 709
 710 /*
 711  * Create the page directory entries and any necessary
 712  * page tables for the mapping specified by `md'.  We
 713  * are able to cope here with varying sizes and address
 714  * offsets, and we take full advantage of sections and
 715  * supersections.
 716  */
 717 static void __init create_mapping(struct map_desc *md)
 718 {
 719         unsigned long addr, length, end;
 720         phys_addr_t phys;
 721         const struct mem_type *type;
 722         pgd_t *pgd;
 723
 724         if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
 725                 printk(KERN_WARNING "BUG: not creating mapping for 0x%08llx"
 726                        " at 0x%08lx in user region\n",
 727                        (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
 728                 return;
 729         }
 730
 731         if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
 732             md->virtual >= PAGE_OFFSET &&
 733             (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) {
 734                 printk(KERN_WARNING "BUG: mapping for 0x%08llx"
 735                        " at 0x%08lx out of vmalloc space\n",
 736                        (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
 737         }
 738
 739         type = &mem_types[md->type];
 740
 741 #ifndef CONFIG_ARM_LPAE
 742         /*
 743          * Catch 36-bit addresses
 744          */
 745         if (md->pfn >= 0x100000) {
 746                 create_36bit_mapping(md, type);
 747                 return;
 748         }
 749 #endif
 750
 751         addr = md->virtual & PAGE_MASK;
 752         phys = __pfn_to_phys(md->pfn);
 753         length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
 754
 755         if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
 756                 printk(KERN_WARNING "BUG: map for 0x%08llx at 0x%08lx can not "
 757                        "be mapped using pages, ignoring.\n",
 758                        (long long)__pfn_to_phys(md->pfn), addr);
 759                 return;
 760         }
 761
 762         pgd = pgd_offset_k(addr);
 763         end = addr + length;
 764         do {
 765                 unsigned long next = pgd_addr_end(addr, end);
 766
 767                 alloc_init_pud(pgd, addr, next, phys, type);
 768
 769                 phys += next - addr;
 770                 addr = next;
 771         } while (pgd++, addr != end);
 772 }
 773
 774 /*
 775  * Create the architecture specific mappings
 776  */
 777 void __init iotable_init(struct map_desc *io_desc, int nr)
 778 {
 779         struct map_desc *md;
 780         struct vm_struct *vm;
 781
 782         if (!nr)
 783                 return;
 784
 785         vm = early_alloc_aligned(sizeof(*vm) * nr, __alignof__(*vm));
 786
 787         for (md = io_desc; nr; md++, nr--) {
 788                 create_mapping(md);
 789                 vm->addr = (void *)(md->virtual & PAGE_MASK);
 790                 vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
 791                 vm->phys_addr = __pfn_to_phys(md->pfn);
 792                 vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING;
 793                 vm->flags |= VM_ARM_MTYPE(md->type);
 794                 vm->caller = iotable_init;
 795                 vm_area_add_early(vm++);
 796         }
 797 }
 798
 799 static void * __initdata vmalloc_min =
 800         (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET);
 801
 802 /*
 803  * vmalloc=size forces the vmalloc area to be exactly 'size'
 804  * bytes. This can be used to increase (or decrease) the vmalloc
 805  * area - the default is 240m.
 806  */
 807 static int __init early_vmalloc(char *arg)
 808 {
 809         unsigned long vmalloc_reserve = memparse(arg, NULL);
 810
 811         if (vmalloc_reserve < SZ_16M) {
 812                 vmalloc_reserve = SZ_16M;
 813                 printk(KERN_WARNING
 814                         "vmalloc area too small, limiting to %luMB\n",
 815                         vmalloc_reserve >> 20);
 816         }
 817
 818         if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) {
 819                 vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M);
 820                 printk(KERN_WARNING
 821                         "vmalloc area is too big, limiting to %luMB\n",
 822                         vmalloc_reserve >> 20);
 823         }
 824
 825         vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve);
 826         return 0;
 827 }
 828 early_param("vmalloc", early_vmalloc);
 829
 830 phys_addr_t arm_lowmem_limit __initdata = 0;
 831
 832 void __init sanity_check_meminfo(void)
 833 {
 834         int i, j, highmem = 0;
 835
 836         for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
 837                 struct membank *bank = &meminfo.bank[j];
 838                 *bank = meminfo.bank[i];
 839
 840                 if (bank->start > ULONG_MAX)
 841                         highmem = 1;
 842
 843 #ifdef CONFIG_HIGHMEM
 844                 if (__va(bank->start) >= vmalloc_min ||
 845                     __va(bank->start) < (void *)PAGE_OFFSET)
 846                         highmem = 1;
 847
 848                 bank->highmem = highmem;
 849
 850                 /*
 851                  * Split those memory banks which are partially overlapping
 852                  * the vmalloc area greatly simplifying things later.
 853                  */
 854                 if (!highmem && __va(bank->start) < vmalloc_min &&
 855                     bank->size > vmalloc_min - __va(bank->start)) {
 856                         if (meminfo.nr_banks >= NR_BANKS) {
 857                                 printk(KERN_CRIT "NR_BANKS too low, "
 858                                                  "ignoring high memory\n");
 859                         } else {
 860                                 memmove(bank + 1, bank,
 861                                         (meminfo.nr_banks - i) * sizeof(*bank));
 862                                 meminfo.nr_banks++;
 863                                 i++;
 864                                 bank[1].size -= vmalloc_min - __va(bank->start);
 865                                 bank[1].start = __pa(vmalloc_min - 1) + 1;
 866                                 bank[1].highmem = highmem = 1;
 867                                 j++;
 868                         }
 869                         bank->size = vmalloc_min - __va(bank->start);
 870                 }
 871 #else
 872                 bank->highmem = highmem;
 873
 874                 /*
 875                  * Highmem banks not allowed with !CONFIG_HIGHMEM.
 876                  */
 877                 if (highmem) {
 878                         printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
 879                                "(!CONFIG_HIGHMEM).\n",
 880                                (unsigned long long)bank->start,
 881                                (unsigned long long)bank->start + bank->size - 1);
 882                         continue;
 883                 }
 884
 885                 /*
 886                  * Check whether this memory bank would entirely overlap
 887                  * the vmalloc area.
 888                  */
 889                 if (__va(bank->start) >= vmalloc_min ||
 890                     __va(bank->start) < (void *)PAGE_OFFSET) {
 891                         printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
 892                                "(vmalloc region overlap).\n",
 893                                (unsigned long long)bank->start,
 894                                (unsigned long long)bank->start + bank->size - 1);
 895                         continue;
 896                 }
 897
 898                 /*
 899                  * Check whether this memory bank would partially overlap
 900                  * the vmalloc area.
 901                  */
 902                 if (__va(bank->start + bank->size) > vmalloc_min ||
 903                     __va(bank->start + bank->size) < __va(bank->start)) {
 904                         unsigned long newsize = vmalloc_min - __va(bank->start);
 905                         printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx "
 906                                "to -%.8llx (vmalloc region overlap).\n",
 907                                (unsigned long long)bank->start,
 908                                (unsigned long long)bank->start + bank->size - 1,
 909                                (unsigned long long)bank->start + newsize - 1);
 910                         bank->size = newsize;
 911                 }
 912 #endif
 913                 if (!bank->highmem && bank->start + bank->size > arm_lowmem_limit)
 914                         arm_lowmem_limit = bank->start + bank->size;
 915
 916                 j++;
 917         }
 918 #ifdef CONFIG_HIGHMEM
 919         if (highmem) {
 920                 const char *reason = NULL;
 921
 922                 if (cache_is_vipt_aliasing()) {
 923                         /*
 924                          * Interactions between kmap and other mappings
 925                          * make highmem support with aliasing VIPT caches
 926                          * rather difficult.
 927                          */
 928                         reason = "with VIPT aliasing cache";
 929                 }
 930                 if (reason) {
 931                         printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n",
 932                                 reason);
 933                         while (j > 0 && meminfo.bank[j - 1].highmem)
 934                                 j--;
 935                 }
 936         }
 937 #endif
 938         meminfo.nr_banks = j;
 939         high_memory = __va(arm_lowmem_limit - 1) + 1;
 940         memblock_set_current_limit(arm_lowmem_limit);
 941 }
 942
 943 static inline void prepare_page_table(void)
 944 {
 945         unsigned long addr;
 946         phys_addr_t end;
 947
 948         /*
 949          * Clear out all the mappings below the kernel image.
 950          */
 951         for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE)
 952                 pmd_clear(pmd_off_k(addr));
 953
 954 #ifdef CONFIG_XIP_KERNEL
 955         /* The XIP kernel is mapped in the module area -- skip over it */
 956         addr = ((unsigned long)_etext + PMD_SIZE - 1) & PMD_MASK;
 957 #endif
 958         for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE)
 959                 pmd_clear(pmd_off_k(addr));
 960
 961         /*
 962          * Find the end of the first block of lowmem.
 963          */
 964         end = memblock.memory.regions[0].base + memblock.memory.regions[0].size;
 965         if (end >= arm_lowmem_limit)
 966                 end = arm_lowmem_limit;
 967
 968         /*
 969          * Clear out all the kernel space mappings, except for the first
 970          * memory bank, up to the vmalloc region.
 971          */
 972         for (addr = __phys_to_virt(end);
 973              addr < VMALLOC_START; addr += PMD_SIZE)
 974                 pmd_clear(pmd_off_k(addr));
 975 }
 976
 977 #ifdef CONFIG_ARM_LPAE
 978 /* the first page is reserved for pgd */
 979 #define SWAPPER_PG_DIR_SIZE     (PAGE_SIZE + \
 980                                  PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t))
 981 #else
 982 #define SWAPPER_PG_DIR_SIZE     (PTRS_PER_PGD * sizeof(pgd_t))
 983 #endif
 984
 985 /*
 986  * Reserve the special regions of memory
 987  */
 988 void __init arm_mm_memblock_reserve(void)
 989 {
 990         /*
 991          * Reserve the page tables.  These are already in use,
 992          * and can only be in node 0.
 993          */
 994         memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE);
 995
 996 #ifdef CONFIG_SA1111
 997         /*
 998          * Because of the SA1111 DMA bug, we want to preserve our
 999          * precious DMA-able memory...
1000          */
1001         memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
1002 #endif
1003 }
1004
1005 /*
1006  * Set up the device mappings.  Since we clear out the page tables for all
1007  * mappings above VMALLOC_START, we will remove any debug device mappings.
1008  * This means you have to be careful how you debug this function, or any
1009  * called function.  This means you can't use any function or debugging
1010  * method which may touch any device, otherwise the kernel _will_ crash.
1011  */
1012 static void __init devicemaps_init(struct machine_desc *mdesc)
1013 {
1014         struct map_desc map;
1015         unsigned long addr;
1016
1017         /*
1018          * Allocate the vector page early.
1019          */
1020         vectors_page = early_alloc(PAGE_SIZE);
1021
1022         for (addr = VMALLOC_START; addr; addr += PMD_SIZE)
1023                 pmd_clear(pmd_off_k(addr));
1024
1025         /*
1026          * Map the kernel if it is XIP.
1027          * It is always first in the modulearea.
1028          */
1029 #ifdef CONFIG_XIP_KERNEL
1030         map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
1031         map.virtual = MODULES_VADDR;
1032         map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK;
1033         map.type = MT_ROM;
1034         create_mapping(&map);
1035 #endif
1036
1037         /*
1038          * Map the cache flushing regions.
1039          */
1040 #ifdef FLUSH_BASE
1041         map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
1042         map.virtual = FLUSH_BASE;
1043         map.length = SZ_1M;
1044         map.type = MT_CACHECLEAN;
1045         create_mapping(&map);
1046 #endif
1047 #ifdef FLUSH_BASE_MINICACHE
1048         map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
1049         map.virtual = FLUSH_BASE_MINICACHE;
1050         map.length = SZ_1M;
1051         map.type = MT_MINICLEAN;
1052         create_mapping(&map);
1053 #endif
1054
1055         /*
1056          * Create a mapping for the machine vectors at the high-vectors
1057          * location (0xffff0000).  If we aren't using high-vectors, also
1058          * create a mapping at the low-vectors virtual address.
1059          */
1060         map.pfn = __phys_to_pfn(virt_to_phys(vectors_page));
1061         map.virtual = 0xffff0000;
1062         map.length = PAGE_SIZE;
1063         map.type = MT_HIGH_VECTORS;
1064         create_mapping(&map);
1065
1066         if (!vectors_high()) {
1067                 map.virtual = 0;
1068                 map.type = MT_LOW_VECTORS;
1069                 create_mapping(&map);
1070         }
1071
1072         /*
1073          * Ask the machine support to map in the statically mapped devices.
1074          */
1075         if (mdesc->map_io)
1076                 mdesc->map_io();
1077
1078         /*
1079          * Finally flush the caches and tlb to ensure that we're in a
1080          * consistent state wrt the writebuffer.  This also ensures that
1081          * any write-allocated cache lines in the vector page are written
1082          * back.  After this point, we can start to touch devices again.
1083          */
1084         local_flush_tlb_all();
1085         flush_cache_all();
1086 }
1087
1088 static void __init kmap_init(void)
1089 {
1090 #ifdef CONFIG_HIGHMEM
1091         pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE),
1092                 PKMAP_BASE, _PAGE_KERNEL_TABLE);
1093 #endif
1094 }
1095
1096 static void __init map_lowmem(void)
1097 {
1098         struct memblock_region *reg;
1099
1100         /* Map all the lowmem memory banks. */
1101         for_each_memblock(memory, reg) {
1102                 phys_addr_t start = reg->base;
1103                 phys_addr_t end = start + reg->size;
1104                 struct map_desc map;
1105
1106                 if (end > arm_lowmem_limit)
1107                         end = arm_lowmem_limit;
1108                 if (start >= end)
1109                         break;
1110
1111                 map.pfn = __phys_to_pfn(start);
1112                 map.virtual = __phys_to_virt(start);
1113                 map.length = end - start;
1114                 map.type = MT_MEMORY;
1115
1116                 create_mapping(&map);
1117         }
1118 }
1119
1120 /*
1121  * paging_init() sets up the page tables, initialises the zone memory
1122  * maps, and sets up the zero page, bad page and bad page tables.
1123  */
1124 void __init paging_init(struct machine_desc *mdesc)
1125 {
1126         void *zero_page;
1127
1128         memblock_set_current_limit(arm_lowmem_limit);
1129
1130         build_mem_type_table();
1131         prepare_page_table();
1132         map_lowmem();
1133         dma_contiguous_remap();
1134         devicemaps_init(mdesc);
1135         kmap_init();
1136
1137         top_pmd = pmd_off_k(0xffff0000);
1138
1139         /* allocate the zero page. */
1140         zero_page = early_alloc(PAGE_SIZE);
1141
1142         bootmem_init();
1143
1144         empty_zero_page = virt_to_page(zero_page);
1145         __flush_dcache_page(NULL, empty_zero_page);
1146 }