1ca732f9322454176eff6eb7fc9ee32ae2b849e6
[pandora-kernel.git] / arch / arm / mm / mmu.c
1 /*
2  *  linux/arch/arm/mm/mmu.c
3  *
4  *  Copyright (C) 1995-2005 Russell King
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  */
10 #include <linux/module.h>
11 #include <linux/kernel.h>
12 #include <linux/errno.h>
13 #include <linux/init.h>
14 #include <linux/mman.h>
15 #include <linux/nodemask.h>
16 #include <linux/memblock.h>
17 #include <linux/fs.h>
18 #include <linux/vmalloc.h>
19
20 #include <asm/cputype.h>
21 #include <asm/sections.h>
22 #include <asm/cachetype.h>
23 #include <asm/setup.h>
24 #include <asm/sizes.h>
25 #include <asm/smp_plat.h>
26 #include <asm/tlb.h>
27 #include <asm/highmem.h>
28 #include <asm/traps.h>
29
30 #include <asm/mach/arch.h>
31 #include <asm/mach/map.h>
32
33 #include "mm.h"
34
35 /*
36  * empty_zero_page is a special page that is used for
37  * zero-initialized data and COW.
38  */
39 struct page *empty_zero_page;
40 EXPORT_SYMBOL(empty_zero_page);
41
42 /*
43  * The pmd table for the upper-most set of pages.
44  */
45 pmd_t *top_pmd;
46
47 #define CPOLICY_UNCACHED        0
48 #define CPOLICY_BUFFERED        1
49 #define CPOLICY_WRITETHROUGH    2
50 #define CPOLICY_WRITEBACK       3
51 #define CPOLICY_WRITEALLOC      4
52
53 static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
54 static unsigned int ecc_mask __initdata = 0;
55 pgprot_t pgprot_user;
56 pgprot_t pgprot_kernel;
57
58 EXPORT_SYMBOL(pgprot_user);
59 EXPORT_SYMBOL(pgprot_kernel);
60
61 struct cachepolicy {
62         const char      policy[16];
63         unsigned int    cr_mask;
64         pmdval_t        pmd;
65         pteval_t        pte;
66 };
67
68 static struct cachepolicy cache_policies[] __initdata = {
69         {
70                 .policy         = "uncached",
71                 .cr_mask        = CR_W|CR_C,
72                 .pmd            = PMD_SECT_UNCACHED,
73                 .pte            = L_PTE_MT_UNCACHED,
74         }, {
75                 .policy         = "buffered",
76                 .cr_mask        = CR_C,
77                 .pmd            = PMD_SECT_BUFFERED,
78                 .pte            = L_PTE_MT_BUFFERABLE,
79         }, {
80                 .policy         = "writethrough",
81                 .cr_mask        = 0,
82                 .pmd            = PMD_SECT_WT,
83                 .pte            = L_PTE_MT_WRITETHROUGH,
84         }, {
85                 .policy         = "writeback",
86                 .cr_mask        = 0,
87                 .pmd            = PMD_SECT_WB,
88                 .pte            = L_PTE_MT_WRITEBACK,
89         }, {
90                 .policy         = "writealloc",
91                 .cr_mask        = 0,
92                 .pmd            = PMD_SECT_WBWA,
93                 .pte            = L_PTE_MT_WRITEALLOC,
94         }
95 };
96
97 /*
98  * These are useful for identifying cache coherency
99  * problems by allowing the cache or the cache and
100  * writebuffer to be turned off.  (Note: the write
101  * buffer should not be on and the cache off).
102  */
103 static int __init early_cachepolicy(char *p)
104 {
105         int i;
106
107         for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
108                 int len = strlen(cache_policies[i].policy);
109
110                 if (memcmp(p, cache_policies[i].policy, len) == 0) {
111                         cachepolicy = i;
112                         cr_alignment &= ~cache_policies[i].cr_mask;
113                         cr_no_alignment &= ~cache_policies[i].cr_mask;
114                         break;
115                 }
116         }
117         if (i == ARRAY_SIZE(cache_policies))
118                 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
119         /*
120          * This restriction is partly to do with the way we boot; it is
121          * unpredictable to have memory mapped using two different sets of
122          * memory attributes (shared, type, and cache attribs).  We can not
123          * change these attributes once the initial assembly has setup the
124          * page tables.
125          */
126         if (cpu_architecture() >= CPU_ARCH_ARMv6) {
127                 printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
128                 cachepolicy = CPOLICY_WRITEBACK;
129         }
130         flush_cache_all();
131         set_cr(cr_alignment);
132         return 0;
133 }
134 early_param("cachepolicy", early_cachepolicy);
135
136 static int __init early_nocache(char *__unused)
137 {
138         char *p = "buffered";
139         printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
140         early_cachepolicy(p);
141         return 0;
142 }
143 early_param("nocache", early_nocache);
144
145 static int __init early_nowrite(char *__unused)
146 {
147         char *p = "uncached";
148         printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
149         early_cachepolicy(p);
150         return 0;
151 }
152 early_param("nowb", early_nowrite);
153
154 #ifndef CONFIG_ARM_LPAE
155 static int __init early_ecc(char *p)
156 {
157         if (memcmp(p, "on", 2) == 0)
158                 ecc_mask = PMD_PROTECTION;
159         else if (memcmp(p, "off", 3) == 0)
160                 ecc_mask = 0;
161         return 0;
162 }
163 early_param("ecc", early_ecc);
164 #endif
165
166 static int __init noalign_setup(char *__unused)
167 {
168         cr_alignment &= ~CR_A;
169         cr_no_alignment &= ~CR_A;
170         set_cr(cr_alignment);
171         return 1;
172 }
173 __setup("noalign", noalign_setup);
174
175 #ifndef CONFIG_SMP
176 void adjust_cr(unsigned long mask, unsigned long set)
177 {
178         unsigned long flags;
179
180         mask &= ~CR_A;
181
182         set &= mask;
183
184         local_irq_save(flags);
185
186         cr_no_alignment = (cr_no_alignment & ~mask) | set;
187         cr_alignment = (cr_alignment & ~mask) | set;
188
189         set_cr((get_cr() & ~mask) | set);
190
191         local_irq_restore(flags);
192 }
193 #endif
194
195 #define PROT_PTE_DEVICE         L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
196 #define PROT_SECT_DEVICE        PMD_TYPE_SECT|PMD_SECT_AP_WRITE
197
198 static struct mem_type mem_types[] = {
199         [MT_DEVICE] = {           /* Strongly ordered / ARMv6 shared device */
200                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
201                                   L_PTE_SHARED,
202                 .prot_l1        = PMD_TYPE_TABLE,
203                 .prot_sect      = PROT_SECT_DEVICE | PMD_SECT_S,
204                 .domain         = DOMAIN_IO,
205         },
206         [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
207                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
208                 .prot_l1        = PMD_TYPE_TABLE,
209                 .prot_sect      = PROT_SECT_DEVICE,
210                 .domain         = DOMAIN_IO,
211         },
212         [MT_DEVICE_CACHED] = {    /* ioremap_cached */
213                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
214                 .prot_l1        = PMD_TYPE_TABLE,
215                 .prot_sect      = PROT_SECT_DEVICE | PMD_SECT_WB,
216                 .domain         = DOMAIN_IO,
217         },      
218         [MT_DEVICE_WC] = {      /* ioremap_wc */
219                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
220                 .prot_l1        = PMD_TYPE_TABLE,
221                 .prot_sect      = PROT_SECT_DEVICE,
222                 .domain         = DOMAIN_IO,
223         },
224         [MT_UNCACHED] = {
225                 .prot_pte       = PROT_PTE_DEVICE,
226                 .prot_l1        = PMD_TYPE_TABLE,
227                 .prot_sect      = PMD_TYPE_SECT | PMD_SECT_XN,
228                 .domain         = DOMAIN_IO,
229         },
230         [MT_CACHECLEAN] = {
231                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
232                 .domain    = DOMAIN_KERNEL,
233         },
234 #ifndef CONFIG_ARM_LPAE
235         [MT_MINICLEAN] = {
236                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
237                 .domain    = DOMAIN_KERNEL,
238         },
239 #endif
240         [MT_LOW_VECTORS] = {
241                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
242                                 L_PTE_RDONLY,
243                 .prot_l1   = PMD_TYPE_TABLE,
244                 .domain    = DOMAIN_USER,
245         },
246         [MT_HIGH_VECTORS] = {
247                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
248                                 L_PTE_USER | L_PTE_RDONLY,
249                 .prot_l1   = PMD_TYPE_TABLE,
250                 .domain    = DOMAIN_USER,
251         },
252         [MT_MEMORY] = {
253                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
254                 .prot_l1   = PMD_TYPE_TABLE,
255                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
256                 .domain    = DOMAIN_KERNEL,
257         },
258         [MT_ROM] = {
259                 .prot_sect = PMD_TYPE_SECT,
260                 .domain    = DOMAIN_KERNEL,
261         },
262         [MT_MEMORY_NONCACHED] = {
263                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
264                                 L_PTE_MT_BUFFERABLE,
265                 .prot_l1   = PMD_TYPE_TABLE,
266                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
267                 .domain    = DOMAIN_KERNEL,
268         },
269         [MT_MEMORY_DTCM] = {
270                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
271                                 L_PTE_XN,
272                 .prot_l1   = PMD_TYPE_TABLE,
273                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
274                 .domain    = DOMAIN_KERNEL,
275         },
276         [MT_MEMORY_ITCM] = {
277                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
278                 .prot_l1   = PMD_TYPE_TABLE,
279                 .domain    = DOMAIN_KERNEL,
280         },
281         [MT_MEMORY_SO] = {
282                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
283                                 L_PTE_MT_UNCACHED,
284                 .prot_l1   = PMD_TYPE_TABLE,
285                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S |
286                                 PMD_SECT_UNCACHED | PMD_SECT_XN,
287                 .domain    = DOMAIN_KERNEL,
288         },
289         [MT_MEMORY_DMA_READY] = {
290                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
291                 .prot_l1   = PMD_TYPE_TABLE,
292                 .domain    = DOMAIN_KERNEL,
293         },
294 };
295
296 const struct mem_type *get_mem_type(unsigned int type)
297 {
298         return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
299 }
300 EXPORT_SYMBOL(get_mem_type);
301
302 /*
303  * If the system supports huge pages and we are running with short descriptors,
304  * then compute the pmd and linux pte prot values for a huge page.
305  *
306  * These values are used by both the HugeTLB and THP code.
307  */
308 #if defined(CONFIG_SYS_SUPPORTS_HUGETLBFS) && !defined(CONFIG_ARM_LPAE)
309 pmdval_t arm_hugepmdprotval;
310 EXPORT_SYMBOL(arm_hugepmdprotval);
311
312 pteval_t arm_hugepteprotval;
313 EXPORT_SYMBOL(arm_hugepteprotval);
314 #endif
315
316
317 /*
318  * Adjust the PMD section entries according to the CPU in use.
319  */
320 static void __init build_mem_type_table(void)
321 {
322         struct cachepolicy *cp;
323         unsigned int cr = get_cr();
324         pteval_t user_pgprot, kern_pgprot, vecs_pgprot;
325         int cpu_arch = cpu_architecture();
326         int i;
327
328         if (cpu_arch < CPU_ARCH_ARMv6) {
329 #if defined(CONFIG_CPU_DCACHE_DISABLE)
330                 if (cachepolicy > CPOLICY_BUFFERED)
331                         cachepolicy = CPOLICY_BUFFERED;
332 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
333                 if (cachepolicy > CPOLICY_WRITETHROUGH)
334                         cachepolicy = CPOLICY_WRITETHROUGH;
335 #endif
336         }
337         if (cpu_arch < CPU_ARCH_ARMv5) {
338                 if (cachepolicy >= CPOLICY_WRITEALLOC)
339                         cachepolicy = CPOLICY_WRITEBACK;
340                 ecc_mask = 0;
341         }
342         if (is_smp())
343                 cachepolicy = CPOLICY_WRITEALLOC;
344
345         /*
346          * Strip out features not present on earlier architectures.
347          * Pre-ARMv5 CPUs don't have TEX bits.  Pre-ARMv6 CPUs or those
348          * without extended page tables don't have the 'Shared' bit.
349          */
350         if (cpu_arch < CPU_ARCH_ARMv5)
351                 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
352                         mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
353         if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
354                 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
355                         mem_types[i].prot_sect &= ~PMD_SECT_S;
356
357         /*
358          * ARMv5 and lower, bit 4 must be set for page tables (was: cache
359          * "update-able on write" bit on ARM610).  However, Xscale and
360          * Xscale3 require this bit to be cleared.
361          */
362         if (cpu_is_xscale() || cpu_is_xsc3()) {
363                 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
364                         mem_types[i].prot_sect &= ~PMD_BIT4;
365                         mem_types[i].prot_l1 &= ~PMD_BIT4;
366                 }
367         } else if (cpu_arch < CPU_ARCH_ARMv6) {
368                 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
369                         if (mem_types[i].prot_l1)
370                                 mem_types[i].prot_l1 |= PMD_BIT4;
371                         if (mem_types[i].prot_sect)
372                                 mem_types[i].prot_sect |= PMD_BIT4;
373                 }
374         }
375
376         /*
377          * Mark the device areas according to the CPU/architecture.
378          */
379         if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
380                 if (!cpu_is_xsc3()) {
381                         /*
382                          * Mark device regions on ARMv6+ as execute-never
383                          * to prevent speculative instruction fetches.
384                          */
385                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
386                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
387                         mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
388                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
389                 }
390                 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
391                         /*
392                          * For ARMv7 with TEX remapping,
393                          * - shared device is SXCB=1100
394                          * - nonshared device is SXCB=0100
395                          * - write combine device mem is SXCB=0001
396                          * (Uncached Normal memory)
397                          */
398                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
399                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
400                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
401                 } else if (cpu_is_xsc3()) {
402                         /*
403                          * For Xscale3,
404                          * - shared device is TEXCB=00101
405                          * - nonshared device is TEXCB=01000
406                          * - write combine device mem is TEXCB=00100
407                          * (Inner/Outer Uncacheable in xsc3 parlance)
408                          */
409                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
410                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
411                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
412                 } else {
413                         /*
414                          * For ARMv6 and ARMv7 without TEX remapping,
415                          * - shared device is TEXCB=00001
416                          * - nonshared device is TEXCB=01000
417                          * - write combine device mem is TEXCB=00100
418                          * (Uncached Normal in ARMv6 parlance).
419                          */
420                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
421                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
422                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
423                 }
424         } else {
425                 /*
426                  * On others, write combining is "Uncached/Buffered"
427                  */
428                 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
429         }
430
431         /*
432          * Now deal with the memory-type mappings
433          */
434         cp = &cache_policies[cachepolicy];
435         vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
436
437         /*
438          * Only use write-through for non-SMP systems
439          */
440         if (!is_smp() && cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH)
441                 vecs_pgprot = cache_policies[CPOLICY_WRITETHROUGH].pte;
442
443         /*
444          * Enable CPU-specific coherency if supported.
445          * (Only available on XSC3 at the moment.)
446          */
447         if (arch_is_coherent() && cpu_is_xsc3()) {
448                 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
449                 mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
450                 mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED;
451                 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
452                 mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
453         }
454         /*
455          * We don't use domains on ARMv6 (since this causes problems with
456          * v6/v7 kernels), so we must use a separate memory type for user
457          * r/o, kernel r/w to map the vectors page.
458          */
459         if (cpu_arch == CPU_ARCH_ARMv6)
460                 vecs_pgprot |= L_PTE_MT_VECTORS;
461
462         /*
463          * ARMv6 and above have extended page tables.
464          */
465         if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
466 #ifndef CONFIG_ARM_LPAE
467                 /*
468                  * Mark cache clean areas and XIP ROM read only
469                  * from SVC mode and no access from userspace.
470                  */
471                 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
472                 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
473                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
474 #endif
475
476                 if (is_smp()) {
477                         /*
478                          * Mark memory with the "shared" attribute
479                          * for SMP systems
480                          */
481                         user_pgprot |= L_PTE_SHARED;
482                         kern_pgprot |= L_PTE_SHARED;
483                         vecs_pgprot |= L_PTE_SHARED;
484                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
485                         mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
486                         mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
487                         mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
488                         mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
489                         mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
490                         mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED;
491                         mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
492                         mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
493                 }
494         }
495
496         /*
497          * Non-cacheable Normal - intended for memory areas that must
498          * not cause dirty cache line writebacks when used
499          */
500         if (cpu_arch >= CPU_ARCH_ARMv6) {
501                 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
502                         /* Non-cacheable Normal is XCB = 001 */
503                         mem_types[MT_MEMORY_NONCACHED].prot_sect |=
504                                 PMD_SECT_BUFFERED;
505                 } else {
506                         /* For both ARMv6 and non-TEX-remapping ARMv7 */
507                         mem_types[MT_MEMORY_NONCACHED].prot_sect |=
508                                 PMD_SECT_TEX(1);
509                 }
510         } else {
511                 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
512         }
513
514 #ifdef CONFIG_ARM_LPAE
515         /*
516          * Do not generate access flag faults for the kernel mappings.
517          */
518         for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
519                 mem_types[i].prot_pte |= PTE_EXT_AF;
520                 mem_types[i].prot_sect |= PMD_SECT_AF;
521         }
522         kern_pgprot |= PTE_EXT_AF;
523         vecs_pgprot |= PTE_EXT_AF;
524 #endif
525
526         for (i = 0; i < 16; i++) {
527                 pteval_t v = pgprot_val(protection_map[i]);
528                 protection_map[i] = __pgprot(v | user_pgprot);
529         }
530
531         mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
532         mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
533
534         pgprot_user   = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
535         pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
536                                  L_PTE_DIRTY | kern_pgprot);
537
538         mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
539         mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
540         mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
541         mem_types[MT_MEMORY].prot_pte |= kern_pgprot;
542         mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot;
543         mem_types[MT_MEMORY_NONCACHED].prot_sect |= ecc_mask;
544         mem_types[MT_ROM].prot_sect |= cp->pmd;
545
546         switch (cp->pmd) {
547         case PMD_SECT_WT:
548                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
549                 break;
550         case PMD_SECT_WB:
551         case PMD_SECT_WBWA:
552                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
553                 break;
554         }
555         printk("Memory policy: ECC %sabled, Data cache %s\n",
556                 ecc_mask ? "en" : "dis", cp->policy);
557
558         for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
559                 struct mem_type *t = &mem_types[i];
560                 if (t->prot_l1)
561                         t->prot_l1 |= PMD_DOMAIN(t->domain);
562                 if (t->prot_sect)
563                         t->prot_sect |= PMD_DOMAIN(t->domain);
564         }
565
566 #if defined(CONFIG_SYS_SUPPORTS_HUGETLBFS) && !defined(CONFIG_ARM_LPAE)
567         /*
568          * we assume all huge pages are user pages and that hardware access
569          * flag updates are disabled (i.e. SCTLR.AFE == 0b).
570          */
571         arm_hugepteprotval = mem_types[MT_MEMORY].prot_pte | L_PTE_USER | L_PTE_VALID;
572
573         arm_hugepmdprotval = mem_types[MT_MEMORY].prot_sect | PMD_SECT_AP_READ
574                                 | PMD_SECT_nG;
575
576         /* HACK: make huge pages WT
577          * XXX: mm will not know nothing about this..
578          * FIXME: should only do it on Cortex-A8 or below */
579         arm_hugepmdprotval &= ~(PMD_SECT_WB | PMD_SECT_TEX(1));
580         arm_hugepmdprotval |= PMD_SECT_WT;
581 #endif
582
583 }
584
585 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
586 pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
587                               unsigned long size, pgprot_t vma_prot)
588 {
589         if (!pfn_valid(pfn))
590                 return pgprot_noncached(vma_prot);
591         else if (file->f_flags & O_SYNC)
592                 return pgprot_writecombine(vma_prot);
593         return vma_prot;
594 }
595 EXPORT_SYMBOL(phys_mem_access_prot);
596 #endif
597
598 #define vectors_base()  (vectors_high() ? 0xffff0000 : 0)
599
600 static void __init *early_alloc_aligned(unsigned long sz, unsigned long align)
601 {
602         void *ptr = __va(memblock_alloc(sz, align));
603         memset(ptr, 0, sz);
604         return ptr;
605 }
606
607 static void __init *early_alloc(unsigned long sz)
608 {
609         return early_alloc_aligned(sz, sz);
610 }
611
612 static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot)
613 {
614         if (pmd_none(*pmd)) {
615                 pte_t *pte = early_alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE);
616                 __pmd_populate(pmd, __pa(pte), prot);
617         }
618         BUG_ON(pmd_bad(*pmd));
619         return pte_offset_kernel(pmd, addr);
620 }
621
622 static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
623                                   unsigned long end, unsigned long pfn,
624                                   const struct mem_type *type)
625 {
626         pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1);
627         do {
628                 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0);
629                 pfn++;
630         } while (pte++, addr += PAGE_SIZE, addr != end);
631 }
632
633 static void __init alloc_init_section(pud_t *pud, unsigned long addr,
634                                       unsigned long end, phys_addr_t phys,
635                                       const struct mem_type *type)
636 {
637         pmd_t *pmd = pmd_offset(pud, addr);
638
639         /*
640          * Try a section mapping - end, addr and phys must all be aligned
641          * to a section boundary.  Note that PMDs refer to the individual
642          * L1 entries, whereas PGDs refer to a group of L1 entries making
643          * up one logical pointer to an L2 table.
644          */
645         if (type->prot_sect && ((addr | end | phys) & ~SECTION_MASK) == 0) {
646                 pmd_t *p = pmd;
647
648 #ifndef CONFIG_ARM_LPAE
649                 if (addr & SECTION_SIZE)
650                         pmd++;
651 #endif
652
653                 do {
654                         *pmd = __pmd(phys | type->prot_sect);
655                         phys += SECTION_SIZE;
656                 } while (pmd++, addr += SECTION_SIZE, addr != end);
657
658                 flush_pmd_entry(p);
659         } else {
660                 /*
661                  * No need to loop; pte's aren't interested in the
662                  * individual L1 entries.
663                  */
664                 alloc_init_pte(pmd, addr, end, __phys_to_pfn(phys), type);
665         }
666 }
667
668 static void alloc_init_pud(pgd_t *pgd, unsigned long addr, unsigned long end,
669         unsigned long phys, const struct mem_type *type)
670 {
671         pud_t *pud = pud_offset(pgd, addr);
672         unsigned long next;
673
674         do {
675                 next = pud_addr_end(addr, end);
676                 alloc_init_section(pud, addr, next, phys, type);
677                 phys += next - addr;
678         } while (pud++, addr = next, addr != end);
679 }
680
681 #ifndef CONFIG_ARM_LPAE
682 static void __init create_36bit_mapping(struct map_desc *md,
683                                         const struct mem_type *type)
684 {
685         unsigned long addr, length, end;
686         phys_addr_t phys;
687         pgd_t *pgd;
688
689         addr = md->virtual;
690         phys = __pfn_to_phys(md->pfn);
691         length = PAGE_ALIGN(md->length);
692
693         if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
694                 printk(KERN_ERR "MM: CPU does not support supersection "
695                        "mapping for 0x%08llx at 0x%08lx\n",
696                        (long long)__pfn_to_phys((u64)md->pfn), addr);
697                 return;
698         }
699
700         /* N.B. ARMv6 supersections are only defined to work with domain 0.
701          *      Since domain assignments can in fact be arbitrary, the
702          *      'domain == 0' check below is required to insure that ARMv6
703          *      supersections are only allocated for domain 0 regardless
704          *      of the actual domain assignments in use.
705          */
706         if (type->domain) {
707                 printk(KERN_ERR "MM: invalid domain in supersection "
708                        "mapping for 0x%08llx at 0x%08lx\n",
709                        (long long)__pfn_to_phys((u64)md->pfn), addr);
710                 return;
711         }
712
713         if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
714                 printk(KERN_ERR "MM: cannot create mapping for 0x%08llx"
715                        " at 0x%08lx invalid alignment\n",
716                        (long long)__pfn_to_phys((u64)md->pfn), addr);
717                 return;
718         }
719
720         /*
721          * Shift bits [35:32] of address into bits [23:20] of PMD
722          * (See ARMv6 spec).
723          */
724         phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
725
726         pgd = pgd_offset_k(addr);
727         end = addr + length;
728         do {
729                 pud_t *pud = pud_offset(pgd, addr);
730                 pmd_t *pmd = pmd_offset(pud, addr);
731                 int i;
732
733                 for (i = 0; i < 16; i++)
734                         *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER);
735
736                 addr += SUPERSECTION_SIZE;
737                 phys += SUPERSECTION_SIZE;
738                 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
739         } while (addr != end);
740 }
741 #endif  /* !CONFIG_ARM_LPAE */
742
743 /*
744  * Create the page directory entries and any necessary
745  * page tables for the mapping specified by `md'.  We
746  * are able to cope here with varying sizes and address
747  * offsets, and we take full advantage of sections and
748  * supersections.
749  */
750 static void __init create_mapping(struct map_desc *md)
751 {
752         unsigned long addr, length, end;
753         phys_addr_t phys;
754         const struct mem_type *type;
755         pgd_t *pgd;
756
757         if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
758                 printk(KERN_WARNING "BUG: not creating mapping for 0x%08llx"
759                        " at 0x%08lx in user region\n",
760                        (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
761                 return;
762         }
763
764         if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
765             md->virtual >= PAGE_OFFSET &&
766             (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) {
767                 printk(KERN_WARNING "BUG: mapping for 0x%08llx"
768                        " at 0x%08lx out of vmalloc space\n",
769                        (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
770         }
771
772         type = &mem_types[md->type];
773
774 #ifndef CONFIG_ARM_LPAE
775         /*
776          * Catch 36-bit addresses
777          */
778         if (md->pfn >= 0x100000) {
779                 create_36bit_mapping(md, type);
780                 return;
781         }
782 #endif
783
784         addr = md->virtual & PAGE_MASK;
785         phys = __pfn_to_phys(md->pfn);
786         length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
787
788         if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
789                 printk(KERN_WARNING "BUG: map for 0x%08llx at 0x%08lx can not "
790                        "be mapped using pages, ignoring.\n",
791                        (long long)__pfn_to_phys(md->pfn), addr);
792                 return;
793         }
794
795         pgd = pgd_offset_k(addr);
796         end = addr + length;
797         do {
798                 unsigned long next = pgd_addr_end(addr, end);
799
800                 alloc_init_pud(pgd, addr, next, phys, type);
801
802                 phys += next - addr;
803                 addr = next;
804         } while (pgd++, addr != end);
805 }
806
807 /*
808  * Create the architecture specific mappings
809  */
810 void __init iotable_init(struct map_desc *io_desc, int nr)
811 {
812         struct map_desc *md;
813         struct vm_struct *vm;
814
815         if (!nr)
816                 return;
817
818         vm = early_alloc_aligned(sizeof(*vm) * nr, __alignof__(*vm));
819
820         for (md = io_desc; nr; md++, nr--) {
821                 create_mapping(md);
822                 vm->addr = (void *)(md->virtual & PAGE_MASK);
823                 vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
824                 vm->phys_addr = __pfn_to_phys(md->pfn); 
825                 vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING; 
826                 vm->flags |= VM_ARM_MTYPE(md->type);
827                 vm->caller = iotable_init;
828                 vm_area_add_early(vm++);
829         }
830 }
831
832 static void * __initdata vmalloc_min =
833         (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET);
834
835 /*
836  * vmalloc=size forces the vmalloc area to be exactly 'size'
837  * bytes. This can be used to increase (or decrease) the vmalloc
838  * area - the default is 240m.
839  */
840 static int __init early_vmalloc(char *arg)
841 {
842         unsigned long vmalloc_reserve = memparse(arg, NULL);
843
844         if (vmalloc_reserve < SZ_16M) {
845                 vmalloc_reserve = SZ_16M;
846                 printk(KERN_WARNING
847                         "vmalloc area too small, limiting to %luMB\n",
848                         vmalloc_reserve >> 20);
849         }
850
851         if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) {
852                 vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M);
853                 printk(KERN_WARNING
854                         "vmalloc area is too big, limiting to %luMB\n",
855                         vmalloc_reserve >> 20);
856         }
857
858         vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve);
859         return 0;
860 }
861 early_param("vmalloc", early_vmalloc);
862
863 phys_addr_t arm_lowmem_limit __initdata = 0;
864
865 void __init sanity_check_meminfo(void)
866 {
867         int i, j, highmem = 0;
868
869         for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
870                 struct membank *bank = &meminfo.bank[j];
871                 *bank = meminfo.bank[i];
872
873                 if (bank->start > ULONG_MAX)
874                         highmem = 1;
875
876 #ifdef CONFIG_HIGHMEM
877                 if (__va(bank->start) >= vmalloc_min ||
878                     __va(bank->start) < (void *)PAGE_OFFSET)
879                         highmem = 1;
880
881                 bank->highmem = highmem;
882
883                 /*
884                  * Split those memory banks which are partially overlapping
885                  * the vmalloc area greatly simplifying things later.
886                  */
887                 if (!highmem && __va(bank->start) < vmalloc_min &&
888                     bank->size > vmalloc_min - __va(bank->start)) {
889                         if (meminfo.nr_banks >= NR_BANKS) {
890                                 printk(KERN_CRIT "NR_BANKS too low, "
891                                                  "ignoring high memory\n");
892                         } else {
893                                 memmove(bank + 1, bank,
894                                         (meminfo.nr_banks - i) * sizeof(*bank));
895                                 meminfo.nr_banks++;
896                                 i++;
897                                 bank[1].size -= vmalloc_min - __va(bank->start);
898                                 bank[1].start = __pa(vmalloc_min - 1) + 1;
899                                 bank[1].highmem = highmem = 1;
900                                 j++;
901                         }
902                         bank->size = vmalloc_min - __va(bank->start);
903                 }
904 #else
905                 bank->highmem = highmem;
906
907                 /*
908                  * Highmem banks not allowed with !CONFIG_HIGHMEM.
909                  */
910                 if (highmem) {
911                         printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
912                                "(!CONFIG_HIGHMEM).\n",
913                                (unsigned long long)bank->start,
914                                (unsigned long long)bank->start + bank->size - 1);
915                         continue;
916                 }
917
918                 /*
919                  * Check whether this memory bank would entirely overlap
920                  * the vmalloc area.
921                  */
922                 if (__va(bank->start) >= vmalloc_min ||
923                     __va(bank->start) < (void *)PAGE_OFFSET) {
924                         printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
925                                "(vmalloc region overlap).\n",
926                                (unsigned long long)bank->start,
927                                (unsigned long long)bank->start + bank->size - 1);
928                         continue;
929                 }
930
931                 /*
932                  * Check whether this memory bank would partially overlap
933                  * the vmalloc area.
934                  */
935                 if (__va(bank->start + bank->size) > vmalloc_min ||
936                     __va(bank->start + bank->size) < __va(bank->start)) {
937                         unsigned long newsize = vmalloc_min - __va(bank->start);
938                         printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx "
939                                "to -%.8llx (vmalloc region overlap).\n",
940                                (unsigned long long)bank->start,
941                                (unsigned long long)bank->start + bank->size - 1,
942                                (unsigned long long)bank->start + newsize - 1);
943                         bank->size = newsize;
944                 }
945 #endif
946                 if (!bank->highmem && bank->start + bank->size > arm_lowmem_limit)
947                         arm_lowmem_limit = bank->start + bank->size;
948
949                 j++;
950         }
951 #ifdef CONFIG_HIGHMEM
952         if (highmem) {
953                 const char *reason = NULL;
954
955                 if (cache_is_vipt_aliasing()) {
956                         /*
957                          * Interactions between kmap and other mappings
958                          * make highmem support with aliasing VIPT caches
959                          * rather difficult.
960                          */
961                         reason = "with VIPT aliasing cache";
962                 }
963                 if (reason) {
964                         printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n",
965                                 reason);
966                         while (j > 0 && meminfo.bank[j - 1].highmem)
967                                 j--;
968                 }
969         }
970 #endif
971         meminfo.nr_banks = j;
972         high_memory = __va(arm_lowmem_limit - 1) + 1;
973         memblock_set_current_limit(arm_lowmem_limit);
974 }
975
976 static inline void prepare_page_table(void)
977 {
978         unsigned long addr;
979         phys_addr_t end;
980
981         /*
982          * Clear out all the mappings below the kernel image.
983          */
984         for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE)
985                 pmd_clear(pmd_off_k(addr));
986
987 #ifdef CONFIG_XIP_KERNEL
988         /* The XIP kernel is mapped in the module area -- skip over it */
989         addr = ((unsigned long)_etext + PMD_SIZE - 1) & PMD_MASK;
990 #endif
991         for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE)
992                 pmd_clear(pmd_off_k(addr));
993
994         /*
995          * Find the end of the first block of lowmem.
996          */
997         end = memblock.memory.regions[0].base + memblock.memory.regions[0].size;
998         if (end >= arm_lowmem_limit)
999                 end = arm_lowmem_limit;
1000
1001         /*
1002          * Clear out all the kernel space mappings, except for the first
1003          * memory bank, up to the vmalloc region.
1004          */
1005         for (addr = __phys_to_virt(end);
1006              addr < VMALLOC_START; addr += PMD_SIZE)
1007                 pmd_clear(pmd_off_k(addr));
1008 }
1009
1010 #ifdef CONFIG_ARM_LPAE
1011 /* the first page is reserved for pgd */
1012 #define SWAPPER_PG_DIR_SIZE     (PAGE_SIZE + \
1013                                  PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t))
1014 #else
1015 #define SWAPPER_PG_DIR_SIZE     (PTRS_PER_PGD * sizeof(pgd_t))
1016 #endif
1017
1018 /*
1019  * Reserve the special regions of memory
1020  */
1021 void __init arm_mm_memblock_reserve(void)
1022 {
1023         /*
1024          * Reserve the page tables.  These are already in use,
1025          * and can only be in node 0.
1026          */
1027         memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE);
1028
1029 #ifdef CONFIG_SA1111
1030         /*
1031          * Because of the SA1111 DMA bug, we want to preserve our
1032          * precious DMA-able memory...
1033          */
1034         memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
1035 #endif
1036 }
1037
1038 /*
1039  * Set up the device mappings.  Since we clear out the page tables for all
1040  * mappings above VMALLOC_START, we will remove any debug device mappings.
1041  * This means you have to be careful how you debug this function, or any
1042  * called function.  This means you can't use any function or debugging
1043  * method which may touch any device, otherwise the kernel _will_ crash.
1044  */
1045 static void __init devicemaps_init(struct machine_desc *mdesc)
1046 {
1047         struct map_desc map;
1048         unsigned long addr;
1049
1050         /*
1051          * Allocate the vector page early.
1052          */
1053         vectors_page = early_alloc(PAGE_SIZE);
1054
1055         for (addr = VMALLOC_START; addr; addr += PMD_SIZE)
1056                 pmd_clear(pmd_off_k(addr));
1057
1058         /*
1059          * Map the kernel if it is XIP.
1060          * It is always first in the modulearea.
1061          */
1062 #ifdef CONFIG_XIP_KERNEL
1063         map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
1064         map.virtual = MODULES_VADDR;
1065         map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK;
1066         map.type = MT_ROM;
1067         create_mapping(&map);
1068 #endif
1069
1070         /*
1071          * Map the cache flushing regions.
1072          */
1073 #ifdef FLUSH_BASE
1074         map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
1075         map.virtual = FLUSH_BASE;
1076         map.length = SZ_1M;
1077         map.type = MT_CACHECLEAN;
1078         create_mapping(&map);
1079 #endif
1080 #ifdef FLUSH_BASE_MINICACHE
1081         map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
1082         map.virtual = FLUSH_BASE_MINICACHE;
1083         map.length = SZ_1M;
1084         map.type = MT_MINICLEAN;
1085         create_mapping(&map);
1086 #endif
1087
1088         /*
1089          * Create a mapping for the machine vectors at the high-vectors
1090          * location (0xffff0000).  If we aren't using high-vectors, also
1091          * create a mapping at the low-vectors virtual address.
1092          */
1093         map.pfn = __phys_to_pfn(virt_to_phys(vectors_page));
1094         map.virtual = 0xffff0000;
1095         map.length = PAGE_SIZE;
1096         map.type = MT_HIGH_VECTORS;
1097         create_mapping(&map);
1098
1099         if (!vectors_high()) {
1100                 map.virtual = 0;
1101                 map.type = MT_LOW_VECTORS;
1102                 create_mapping(&map);
1103         }
1104
1105         /*
1106          * Ask the machine support to map in the statically mapped devices.
1107          */
1108         if (mdesc->map_io)
1109                 mdesc->map_io();
1110
1111         /*
1112          * Finally flush the caches and tlb to ensure that we're in a
1113          * consistent state wrt the writebuffer.  This also ensures that
1114          * any write-allocated cache lines in the vector page are written
1115          * back.  After this point, we can start to touch devices again.
1116          */
1117         local_flush_tlb_all();
1118         flush_cache_all();
1119 }
1120
1121 static void __init kmap_init(void)
1122 {
1123 #ifdef CONFIG_HIGHMEM
1124         pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE),
1125                 PKMAP_BASE, _PAGE_KERNEL_TABLE);
1126 #endif
1127 }
1128
1129 static void __init map_lowmem(void)
1130 {
1131         struct memblock_region *reg;
1132
1133         /* Map all the lowmem memory banks. */
1134         for_each_memblock(memory, reg) {
1135                 phys_addr_t start = reg->base;
1136                 phys_addr_t end = start + reg->size;
1137                 struct map_desc map;
1138
1139                 if (end > arm_lowmem_limit)
1140                         end = arm_lowmem_limit;
1141                 if (start >= end)
1142                         break;
1143
1144                 map.pfn = __phys_to_pfn(start);
1145                 map.virtual = __phys_to_virt(start);
1146                 map.length = end - start;
1147                 map.type = MT_MEMORY;
1148
1149                 create_mapping(&map);
1150         }
1151 }
1152
1153 /*
1154  * paging_init() sets up the page tables, initialises the zone memory
1155  * maps, and sets up the zero page, bad page and bad page tables.
1156  */
1157 void __init paging_init(struct machine_desc *mdesc)
1158 {
1159         void *zero_page;
1160
1161         memblock_set_current_limit(arm_lowmem_limit);
1162
1163         build_mem_type_table();
1164         prepare_page_table();
1165         map_lowmem();
1166         dma_contiguous_remap();
1167         devicemaps_init(mdesc);
1168         kmap_init();
1169
1170         top_pmd = pmd_off_k(0xffff0000);
1171
1172         /* allocate the zero page. */
1173         zero_page = early_alloc(PAGE_SIZE);
1174
1175         bootmem_init();
1176
1177         empty_zero_page = virt_to_page(zero_page);
1178         __flush_dcache_page(NULL, empty_zero_page);
1179 }