arch/arm/mm/alignment.c

   1 /*
   2  *  linux/arch/arm/mm/alignment.c
   3  *
   4  *  Copyright (C) 1995  Linus Torvalds
   5  *  Modifications for ARM processor (c) 1995-2001 Russell King
   6  *  Thumb alignment fault fixups (c) 2004 MontaVista Software, Inc.
   7  *  - Adapted from gdb/sim/arm/thumbemu.c -- Thumb instruction emulation.
   8  *    Copyright (C) 1996, Cygnus Software Technologies Ltd.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14 #include <linux/moduleparam.h>
  15 #include <linux/compiler.h>
  16 #include <linux/kernel.h>
  17 #include <linux/errno.h>
  18 #include <linux/string.h>
  19 #include <linux/proc_fs.h>
  20 #include <linux/seq_file.h>
  21 #include <linux/init.h>
  22 #include <linux/sched.h>
  23 #include <linux/uaccess.h>
  24
  25 #include <asm/cp15.h>
  26 #include <asm/system_info.h>
  27 #include <asm/unaligned.h>
  28 #include <asm/opcodes.h>
  29
  30 #include "fault.h"
  31 #include "mm.h"
  32
  33 /*
  34  * 32-bit misaligned trap handler (c) 1998 San Mehat (CCC) -July 1998
  35  * /proc/sys/debug/alignment, modified and integrated into
  36  * Linux 2.1 by Russell King
  37  *
  38  * Speed optimisations and better fault handling by Russell King.
  39  *
  40  * *** NOTE ***
  41  * This code is not portable to processors with late data abort handling.
  42  */
  43 #define CODING_BITS(i)  (i & 0x0e000000)
  44
  45 #define LDST_I_BIT(i)   (i & (1 << 26))         /* Immediate constant   */
  46 #define LDST_P_BIT(i)   (i & (1 << 24))         /* Preindex             */
  47 #define LDST_U_BIT(i)   (i & (1 << 23))         /* Add offset           */
  48 #define LDST_W_BIT(i)   (i & (1 << 21))         /* Writeback            */
  49 #define LDST_L_BIT(i)   (i & (1 << 20))         /* Load                 */
  50
  51 #define LDST_P_EQ_U(i)  ((((i) ^ ((i) >> 1)) & (1 << 23)) == 0)
  52
  53 #define LDSTHD_I_BIT(i) (i & (1 << 22))         /* double/half-word immed */
  54 #define LDM_S_BIT(i)    (i & (1 << 22))         /* write CPSR from SPSR */
  55
  56 #define RN_BITS(i)      ((i >> 16) & 15)        /* Rn                   */
  57 #define RD_BITS(i)      ((i >> 12) & 15)        /* Rd                   */
  58 #define RM_BITS(i)      (i & 15)                /* Rm                   */
  59
  60 #define REGMASK_BITS(i) (i & 0xffff)
  61 #define OFFSET_BITS(i)  (i & 0x0fff)
  62
  63 #define IS_SHIFT(i)     (i & 0x0ff0)
  64 #define SHIFT_BITS(i)   ((i >> 7) & 0x1f)
  65 #define SHIFT_TYPE(i)   (i & 0x60)
  66 #define SHIFT_LSL       0x00
  67 #define SHIFT_LSR       0x20
  68 #define SHIFT_ASR       0x40
  69 #define SHIFT_RORRRX    0x60
  70
  71 #define BAD_INSTR       0xdeadc0de
  72
  73 /* Thumb-2 32 bit format per ARMv7 DDI0406A A6.3, either f800h,e800h,f800h */
  74 #define IS_T32(hi16) \
  75         (((hi16) & 0xe000) == 0xe000 && ((hi16) & 0x1800))
  76
  77 static unsigned long ai_user;
  78 static unsigned long ai_sys;
  79 static void *ai_sys_last_pc;
  80 static unsigned long ai_skipped;
  81 static unsigned long ai_half;
  82 static unsigned long ai_word;
  83 static unsigned long ai_dword;
  84 static unsigned long ai_multi;
  85 static int ai_usermode;
  86 static unsigned long cr_no_alignment;
  87
  88 core_param(alignment, ai_usermode, int, 0600);
  89
  90 #define UM_WARN         (1 << 0)
  91 #define UM_FIXUP        (1 << 1)
  92 #define UM_SIGNAL       (1 << 2)
  93
  94 /* Return true if and only if the ARMv6 unaligned access model is in use. */
  95 static bool cpu_is_v6_unaligned(void)
  96 {
  97         return cpu_architecture() >= CPU_ARCH_ARMv6 && get_cr() & CR_U;
  98 }
  99
 100 static int safe_usermode(int new_usermode, bool warn)
 101 {
 102         /*
 103          * ARMv6 and later CPUs can perform unaligned accesses for
 104          * most single load and store instructions up to word size.
 105          * LDM, STM, LDRD and STRD still need to be handled.
 106          *
 107          * Ignoring the alignment fault is not an option on these
 108          * CPUs since we spin re-faulting the instruction without
 109          * making any progress.
 110          */
 111         if (cpu_is_v6_unaligned() && !(new_usermode & (UM_FIXUP | UM_SIGNAL))) {
 112                 new_usermode |= UM_FIXUP;
 113
 114                 if (warn)
 115                         printk(KERN_WARNING "alignment: ignoring faults is unsafe on this CPU.  Defaulting to fixup mode.\n");
 116         }
 117
 118         return new_usermode;
 119 }
 120
 121 #ifdef CONFIG_PROC_FS
 122 static const char *usermode_action[] = {
 123         "ignored",
 124         "warn",
 125         "fixup",
 126         "fixup+warn",
 127         "signal",
 128         "signal+warn"
 129 };
 130
 131 static int alignment_proc_show(struct seq_file *m, void *v)
 132 {
 133         seq_printf(m, "User:\t\t%lu\n", ai_user);
 134         seq_printf(m, "System:\t\t%lu (%pF)\n", ai_sys, ai_sys_last_pc);
 135         seq_printf(m, "Skipped:\t%lu\n", ai_skipped);
 136         seq_printf(m, "Half:\t\t%lu\n", ai_half);
 137         seq_printf(m, "Word:\t\t%lu\n", ai_word);
 138         if (cpu_architecture() >= CPU_ARCH_ARMv5TE)
 139                 seq_printf(m, "DWord:\t\t%lu\n", ai_dword);
 140         seq_printf(m, "Multi:\t\t%lu\n", ai_multi);
 141         seq_printf(m, "User faults:\t%i (%s)\n", ai_usermode,
 142                         usermode_action[ai_usermode]);
 143
 144         return 0;
 145 }
 146
 147 static int alignment_proc_open(struct inode *inode, struct file *file)
 148 {
 149         return single_open(file, alignment_proc_show, NULL);
 150 }
 151
 152 static ssize_t alignment_proc_write(struct file *file, const char __user *buffer,
 153                                     size_t count, loff_t *pos)
 154 {
 155         char mode;
 156
 157         if (count > 0) {
 158                 if (get_user(mode, buffer))
 159                         return -EFAULT;
 160                 if (mode >= '0' && mode <= '5')
 161                         ai_usermode = safe_usermode(mode - '0', true);
 162         }
 163         return count;
 164 }
 165
 166 static const struct file_operations alignment_proc_fops = {
 167         .open           = alignment_proc_open,
 168         .read           = seq_read,
 169         .llseek         = seq_lseek,
 170         .release        = single_release,
 171         .write          = alignment_proc_write,
 172 };
 173 #endif /* CONFIG_PROC_FS */
 174
 175 union offset_union {
 176         unsigned long un;
 177           signed long sn;
 178 };
 179
 180 #define TYPE_ERROR      0
 181 #define TYPE_FAULT      1
 182 #define TYPE_LDST       2
 183 #define TYPE_DONE       3
 184
 185 #ifdef __ARMEB__
 186 #define BE              1
 187 #define FIRST_BYTE_16   "mov    %1, %1, ror #8\n"
 188 #define FIRST_BYTE_32   "mov    %1, %1, ror #24\n"
 189 #define NEXT_BYTE       "ror #24"
 190 #else
 191 #define BE              0
 192 #define FIRST_BYTE_16
 193 #define FIRST_BYTE_32
 194 #define NEXT_BYTE       "lsr #8"
 195 #endif
 196
 197 #define __get8_unaligned_check(ins,val,addr,err)        \
 198         __asm__(                                        \
 199  ARM(   "1:     "ins"   %1, [%2], #1\n" )               \
 200  THUMB( "1:     "ins"   %1, [%2]\n"     )               \
 201  THUMB( "       add     %2, %2, #1\n"   )               \
 202         "2:\n"                                          \
 203         "       .pushsection .fixup,\"ax\"\n"           \
 204         "       .align  2\n"                            \
 205         "3:     mov     %0, #1\n"                       \
 206         "       b       2b\n"                           \
 207         "       .popsection\n"                          \
 208         "       .pushsection __ex_table,\"a\"\n"        \
 209         "       .align  3\n"                            \
 210         "       .long   1b, 3b\n"                       \
 211         "       .popsection\n"                          \
 212         : "=r" (err), "=&r" (val), "=r" (addr)          \
 213         : "0" (err), "2" (addr))
 214
 215 #define __get16_unaligned_check(ins,val,addr)                   \
 216         do {                                                    \
 217                 unsigned int err = 0, v, a = addr;              \
 218                 __get8_unaligned_check(ins,v,a,err);            \
 219                 val =  v << ((BE) ? 8 : 0);                     \
 220                 __get8_unaligned_check(ins,v,a,err);            \
 221                 val |= v << ((BE) ? 0 : 8);                     \
 222                 if (err)                                        \
 223                         goto fault;                             \
 224         } while (0)
 225
 226 #define get16_unaligned_check(val,addr) \
 227         __get16_unaligned_check("ldrb",val,addr)
 228
 229 #define get16t_unaligned_check(val,addr) \
 230         __get16_unaligned_check("ldrbt",val,addr)
 231
 232 #define __get32_unaligned_check(ins,val,addr)                   \
 233         do {                                                    \
 234                 unsigned int err = 0, v, a = addr;              \
 235                 __get8_unaligned_check(ins,v,a,err);            \
 236                 val =  v << ((BE) ? 24 :  0);                   \
 237                 __get8_unaligned_check(ins,v,a,err);            \
 238                 val |= v << ((BE) ? 16 :  8);                   \
 239                 __get8_unaligned_check(ins,v,a,err);            \
 240                 val |= v << ((BE) ?  8 : 16);                   \
 241                 __get8_unaligned_check(ins,v,a,err);            \
 242                 val |= v << ((BE) ?  0 : 24);                   \
 243                 if (err)                                        \
 244                         goto fault;                             \
 245         } while (0)
 246
 247 #define get32_unaligned_check(val,addr) \
 248         __get32_unaligned_check("ldrb",val,addr)
 249
 250 #define get32t_unaligned_check(val,addr) \
 251         __get32_unaligned_check("ldrbt",val,addr)
 252
 253 #define __put16_unaligned_check(ins,val,addr)                   \
 254         do {                                                    \
 255                 unsigned int err = 0, v = val, a = addr;        \
 256                 __asm__( FIRST_BYTE_16                          \
 257          ARM(   "1:     "ins"   %1, [%2], #1\n" )               \
 258          THUMB( "1:     "ins"   %1, [%2]\n"     )               \
 259          THUMB( "       add     %2, %2, #1\n"   )               \
 260                 "       mov     %1, %1, "NEXT_BYTE"\n"          \
 261                 "2:     "ins"   %1, [%2]\n"                     \
 262                 "3:\n"                                          \
 263                 "       .pushsection .fixup,\"ax\"\n"           \
 264                 "       .align  2\n"                            \
 265                 "4:     mov     %0, #1\n"                       \
 266                 "       b       3b\n"                           \
 267                 "       .popsection\n"                          \
 268                 "       .pushsection __ex_table,\"a\"\n"        \
 269                 "       .align  3\n"                            \
 270                 "       .long   1b, 4b\n"                       \
 271                 "       .long   2b, 4b\n"                       \
 272                 "       .popsection\n"                          \
 273                 : "=r" (err), "=&r" (v), "=&r" (a)              \
 274                 : "0" (err), "1" (v), "2" (a));                 \
 275                 if (err)                                        \
 276                         goto fault;                             \
 277         } while (0)
 278
 279 #define put16_unaligned_check(val,addr)  \
 280         __put16_unaligned_check("strb",val,addr)
 281
 282 #define put16t_unaligned_check(val,addr) \
 283         __put16_unaligned_check("strbt",val,addr)
 284
 285 #define __put32_unaligned_check(ins,val,addr)                   \
 286         do {                                                    \
 287                 unsigned int err = 0, v = val, a = addr;        \
 288                 __asm__( FIRST_BYTE_32                          \
 289          ARM(   "1:     "ins"   %1, [%2], #1\n" )               \
 290          THUMB( "1:     "ins"   %1, [%2]\n"     )               \
 291          THUMB( "       add     %2, %2, #1\n"   )               \
 292                 "       mov     %1, %1, "NEXT_BYTE"\n"          \
 293          ARM(   "2:     "ins"   %1, [%2], #1\n" )               \
 294          THUMB( "2:     "ins"   %1, [%2]\n"     )               \
 295          THUMB( "       add     %2, %2, #1\n"   )               \
 296                 "       mov     %1, %1, "NEXT_BYTE"\n"          \
 297          ARM(   "3:     "ins"   %1, [%2], #1\n" )               \
 298          THUMB( "3:     "ins"   %1, [%2]\n"     )               \
 299          THUMB( "       add     %2, %2, #1\n"   )               \
 300                 "       mov     %1, %1, "NEXT_BYTE"\n"          \
 301                 "4:     "ins"   %1, [%2]\n"                     \
 302                 "5:\n"                                          \
 303                 "       .pushsection .fixup,\"ax\"\n"           \
 304                 "       .align  2\n"                            \
 305                 "6:     mov     %0, #1\n"                       \
 306                 "       b       5b\n"                           \
 307                 "       .popsection\n"                          \
 308                 "       .pushsection __ex_table,\"a\"\n"        \
 309                 "       .align  3\n"                            \
 310                 "       .long   1b, 6b\n"                       \
 311                 "       .long   2b, 6b\n"                       \
 312                 "       .long   3b, 6b\n"                       \
 313                 "       .long   4b, 6b\n"                       \
 314                 "       .popsection\n"                          \
 315                 : "=r" (err), "=&r" (v), "=&r" (a)              \
 316                 : "0" (err), "1" (v), "2" (a));                 \
 317                 if (err)                                        \
 318                         goto fault;                             \
 319         } while (0)
 320
 321 #define put32_unaligned_check(val,addr) \
 322         __put32_unaligned_check("strb", val, addr)
 323
 324 #define put32t_unaligned_check(val,addr) \
 325         __put32_unaligned_check("strbt", val, addr)
 326
 327 static void
 328 do_alignment_finish_ldst(unsigned long addr, unsigned long instr, struct pt_regs *regs, union offset_union offset)
 329 {
 330         if (!LDST_U_BIT(instr))
 331                 offset.un = -offset.un;
 332
 333         if (!LDST_P_BIT(instr))
 334                 addr += offset.un;
 335
 336         if (!LDST_P_BIT(instr) || LDST_W_BIT(instr))
 337                 regs->uregs[RN_BITS(instr)] = addr;
 338 }
 339
 340 static int
 341 do_alignment_ldrhstrh(unsigned long addr, unsigned long instr, struct pt_regs *regs)
 342 {
 343         unsigned int rd = RD_BITS(instr);
 344
 345         ai_half += 1;
 346
 347         if (user_mode(regs))
 348                 goto user;
 349
 350         if (LDST_L_BIT(instr)) {
 351                 unsigned long val;
 352                 get16_unaligned_check(val, addr);
 353
 354                 /* signed half-word? */
 355                 if (instr & 0x40)
 356                         val = (signed long)((signed short) val);
 357
 358                 regs->uregs[rd] = val;
 359         } else
 360                 put16_unaligned_check(regs->uregs[rd], addr);
 361
 362         return TYPE_LDST;
 363
 364  user:
 365         if (LDST_L_BIT(instr)) {
 366                 unsigned long val;
 367                 get16t_unaligned_check(val, addr);
 368
 369                 /* signed half-word? */
 370                 if (instr & 0x40)
 371                         val = (signed long)((signed short) val);
 372
 373                 regs->uregs[rd] = val;
 374         } else
 375                 put16t_unaligned_check(regs->uregs[rd], addr);
 376
 377         return TYPE_LDST;
 378
 379  fault:
 380         return TYPE_FAULT;
 381 }
 382
 383 static int
 384 do_alignment_ldrdstrd(unsigned long addr, unsigned long instr,
 385                       struct pt_regs *regs)
 386 {
 387         unsigned int rd = RD_BITS(instr);
 388         unsigned int rd2;
 389         int load;
 390
 391         if ((instr & 0xfe000000) == 0xe8000000) {
 392                 /* ARMv7 Thumb-2 32-bit LDRD/STRD */
 393                 rd2 = (instr >> 8) & 0xf;
 394                 load = !!(LDST_L_BIT(instr));
 395         } else if (((rd & 1) == 1) || (rd == 14))
 396                 goto bad;
 397         else {
 398                 load = ((instr & 0xf0) == 0xd0);
 399                 rd2 = rd + 1;
 400         }
 401
 402         ai_dword += 1;
 403
 404         if (user_mode(regs))
 405                 goto user;
 406
 407         if (load) {
 408                 unsigned long val;
 409                 get32_unaligned_check(val, addr);
 410                 regs->uregs[rd] = val;
 411                 get32_unaligned_check(val, addr + 4);
 412                 regs->uregs[rd2] = val;
 413         } else {
 414                 put32_unaligned_check(regs->uregs[rd], addr);
 415                 put32_unaligned_check(regs->uregs[rd2], addr + 4);
 416         }
 417
 418         return TYPE_LDST;
 419
 420  user:
 421         if (load) {
 422                 unsigned long val;
 423                 get32t_unaligned_check(val, addr);
 424                 regs->uregs[rd] = val;
 425                 get32t_unaligned_check(val, addr + 4);
 426                 regs->uregs[rd2] = val;
 427         } else {
 428                 put32t_unaligned_check(regs->uregs[rd], addr);
 429                 put32t_unaligned_check(regs->uregs[rd2], addr + 4);
 430         }
 431
 432         return TYPE_LDST;
 433  bad:
 434         return TYPE_ERROR;
 435  fault:
 436         return TYPE_FAULT;
 437 }
 438
 439 static int
 440 do_alignment_ldrstr(unsigned long addr, unsigned long instr, struct pt_regs *regs)
 441 {
 442         unsigned int rd = RD_BITS(instr);
 443
 444         ai_word += 1;
 445
 446         if ((!LDST_P_BIT(instr) && LDST_W_BIT(instr)) || user_mode(regs))
 447                 goto trans;
 448
 449         if (LDST_L_BIT(instr)) {
 450                 unsigned int val;
 451                 get32_unaligned_check(val, addr);
 452                 regs->uregs[rd] = val;
 453         } else
 454                 put32_unaligned_check(regs->uregs[rd], addr);
 455         return TYPE_LDST;
 456
 457  trans:
 458         if (LDST_L_BIT(instr)) {
 459                 unsigned int val;
 460                 get32t_unaligned_check(val, addr);
 461                 regs->uregs[rd] = val;
 462         } else
 463                 put32t_unaligned_check(regs->uregs[rd], addr);
 464         return TYPE_LDST;
 465
 466  fault:
 467         return TYPE_FAULT;
 468 }
 469
 470 /*
 471  * LDM/STM alignment handler.
 472  *
 473  * There are 4 variants of this instruction:
 474  *
 475  * B = rn pointer before instruction, A = rn pointer after instruction
 476  *              ------ increasing address ----->
 477  *              |    | r0 | r1 | ... | rx |    |
 478  * PU = 01             B                    A
 479  * PU = 11        B                    A
 480  * PU = 00        A                    B
 481  * PU = 10             A                    B
 482  */
 483 static int
 484 do_alignment_ldmstm(unsigned long addr, unsigned long instr, struct pt_regs *regs)
 485 {
 486         unsigned int rd, rn, correction, nr_regs, regbits;
 487         unsigned long eaddr, newaddr;
 488
 489         if (LDM_S_BIT(instr))
 490                 goto bad;
 491
 492         correction = 4; /* processor implementation defined */
 493         regs->ARM_pc += correction;
 494
 495         ai_multi += 1;
 496
 497         /* count the number of registers in the mask to be transferred */
 498         nr_regs = hweight16(REGMASK_BITS(instr)) * 4;
 499
 500         rn = RN_BITS(instr);
 501         newaddr = eaddr = regs->uregs[rn];
 502
 503         if (!LDST_U_BIT(instr))
 504                 nr_regs = -nr_regs;
 505         newaddr += nr_regs;
 506         if (!LDST_U_BIT(instr))
 507                 eaddr = newaddr;
 508
 509         if (LDST_P_EQ_U(instr)) /* U = P */
 510                 eaddr += 4;
 511
 512         /*
 513          * For alignment faults on the ARM922T/ARM920T the MMU  makes
 514          * the FSR (and hence addr) equal to the updated base address
 515          * of the multiple access rather than the restored value.
 516          * Switch this message off if we've got a ARM92[02], otherwise
 517          * [ls]dm alignment faults are noisy!
 518          */
 519 #if !(defined CONFIG_CPU_ARM922T)  && !(defined CONFIG_CPU_ARM920T)
 520         /*
 521          * This is a "hint" - we already have eaddr worked out by the
 522          * processor for us.
 523          */
 524         if (addr != eaddr) {
 525                 printk(KERN_ERR "LDMSTM: PC = %08lx, instr = %08lx, "
 526                         "addr = %08lx, eaddr = %08lx\n",
 527                          instruction_pointer(regs), instr, addr, eaddr);
 528                 show_regs(regs);
 529         }
 530 #endif
 531
 532         if (user_mode(regs)) {
 533                 for (regbits = REGMASK_BITS(instr), rd = 0; regbits;
 534                      regbits >>= 1, rd += 1)
 535                         if (regbits & 1) {
 536                                 if (LDST_L_BIT(instr)) {
 537                                         unsigned int val;
 538                                         get32t_unaligned_check(val, eaddr);
 539                                         regs->uregs[rd] = val;
 540                                 } else
 541                                         put32t_unaligned_check(regs->uregs[rd], eaddr);
 542                                 eaddr += 4;
 543                         }
 544         } else {
 545                 for (regbits = REGMASK_BITS(instr), rd = 0; regbits;
 546                      regbits >>= 1, rd += 1)
 547                         if (regbits & 1) {
 548                                 if (LDST_L_BIT(instr)) {
 549                                         unsigned int val;
 550                                         get32_unaligned_check(val, eaddr);
 551                                         regs->uregs[rd] = val;
 552                                 } else
 553                                         put32_unaligned_check(regs->uregs[rd], eaddr);
 554                                 eaddr += 4;
 555                         }
 556         }
 557
 558         if (LDST_W_BIT(instr))
 559                 regs->uregs[rn] = newaddr;
 560         if (!LDST_L_BIT(instr) || !(REGMASK_BITS(instr) & (1 << 15)))
 561                 regs->ARM_pc -= correction;
 562         return TYPE_DONE;
 563
 564 fault:
 565         regs->ARM_pc -= correction;
 566         return TYPE_FAULT;
 567
 568 bad:
 569         printk(KERN_ERR "Alignment trap: not handling ldm with s-bit set\n");
 570         return TYPE_ERROR;
 571 }
 572
 573 /*
 574  * Convert Thumb ld/st instruction forms to equivalent ARM instructions so
 575  * we can reuse ARM userland alignment fault fixups for Thumb.
 576  *
 577  * This implementation was initially based on the algorithm found in
 578  * gdb/sim/arm/thumbemu.c. It is basically just a code reduction of same
 579  * to convert only Thumb ld/st instruction forms to equivalent ARM forms.
 580  *
 581  * NOTES:
 582  * 1. Comments below refer to ARM ARM DDI0100E Thumb Instruction sections.
 583  * 2. If for some reason we're passed an non-ld/st Thumb instruction to
 584  *    decode, we return 0xdeadc0de. This should never happen under normal
 585  *    circumstances but if it does, we've got other problems to deal with
 586  *    elsewhere and we obviously can't fix those problems here.
 587  */
 588
 589 static unsigned long
 590 thumb2arm(u16 tinstr)
 591 {
 592         u32 L = (tinstr & (1<<11)) >> 11;
 593
 594         switch ((tinstr & 0xf800) >> 11) {
 595         /* 6.5.1 Format 1: */
 596         case 0x6000 >> 11:                              /* 7.1.52 STR(1) */
 597         case 0x6800 >> 11:                              /* 7.1.26 LDR(1) */
 598         case 0x7000 >> 11:                              /* 7.1.55 STRB(1) */
 599         case 0x7800 >> 11:                              /* 7.1.30 LDRB(1) */
 600                 return 0xe5800000 |
 601                         ((tinstr & (1<<12)) << (22-12)) |       /* fixup */
 602                         (L<<20) |                               /* L==1? */
 603                         ((tinstr & (7<<0)) << (12-0)) |         /* Rd */
 604                         ((tinstr & (7<<3)) << (16-3)) |         /* Rn */
 605                         ((tinstr & (31<<6)) >>                  /* immed_5 */
 606                                 (6 - ((tinstr & (1<<12)) ? 0 : 2)));
 607         case 0x8000 >> 11:                              /* 7.1.57 STRH(1) */
 608         case 0x8800 >> 11:                              /* 7.1.32 LDRH(1) */
 609                 return 0xe1c000b0 |
 610                         (L<<20) |                               /* L==1? */
 611                         ((tinstr & (7<<0)) << (12-0)) |         /* Rd */
 612                         ((tinstr & (7<<3)) << (16-3)) |         /* Rn */
 613                         ((tinstr & (7<<6)) >> (6-1)) |   /* immed_5[2:0] */
 614                         ((tinstr & (3<<9)) >> (9-8));    /* immed_5[4:3] */
 615
 616         /* 6.5.1 Format 2: */
 617         case 0x5000 >> 11:
 618         case 0x5800 >> 11:
 619                 {
 620                         static const u32 subset[8] = {
 621                                 0xe7800000,             /* 7.1.53 STR(2) */
 622                                 0xe18000b0,             /* 7.1.58 STRH(2) */
 623                                 0xe7c00000,             /* 7.1.56 STRB(2) */
 624                                 0xe19000d0,             /* 7.1.34 LDRSB */
 625                                 0xe7900000,             /* 7.1.27 LDR(2) */
 626                                 0xe19000b0,             /* 7.1.33 LDRH(2) */
 627                                 0xe7d00000,             /* 7.1.31 LDRB(2) */
 628                                 0xe19000f0              /* 7.1.35 LDRSH */
 629                         };
 630                         return subset[(tinstr & (7<<9)) >> 9] |
 631                             ((tinstr & (7<<0)) << (12-0)) |     /* Rd */
 632                             ((tinstr & (7<<3)) << (16-3)) |     /* Rn */
 633                             ((tinstr & (7<<6)) >> (6-0));       /* Rm */
 634                 }
 635
 636         /* 6.5.1 Format 3: */
 637         case 0x4800 >> 11:                              /* 7.1.28 LDR(3) */
 638                 /* NOTE: This case is not technically possible. We're
 639                  *       loading 32-bit memory data via PC relative
 640                  *       addressing mode. So we can and should eliminate
 641                  *       this case. But I'll leave it here for now.
 642                  */
 643                 return 0xe59f0000 |
 644                     ((tinstr & (7<<8)) << (12-8)) |             /* Rd */
 645                     ((tinstr & 255) << (2-0));                  /* immed_8 */
 646
 647         /* 6.5.1 Format 4: */
 648         case 0x9000 >> 11:                              /* 7.1.54 STR(3) */
 649         case 0x9800 >> 11:                              /* 7.1.29 LDR(4) */
 650                 return 0xe58d0000 |
 651                         (L<<20) |                               /* L==1? */
 652                         ((tinstr & (7<<8)) << (12-8)) |         /* Rd */
 653                         ((tinstr & 255) << 2);                  /* immed_8 */
 654
 655         /* 6.6.1 Format 1: */
 656         case 0xc000 >> 11:                              /* 7.1.51 STMIA */
 657         case 0xc800 >> 11:                              /* 7.1.25 LDMIA */
 658                 {
 659                         u32 Rn = (tinstr & (7<<8)) >> 8;
 660                         u32 W = ((L<<Rn) & (tinstr&255)) ? 0 : 1<<21;
 661
 662                         return 0xe8800000 | W | (L<<20) | (Rn<<16) |
 663                                 (tinstr&255);
 664                 }
 665
 666         /* 6.6.1 Format 2: */
 667         case 0xb000 >> 11:                              /* 7.1.48 PUSH */
 668         case 0xb800 >> 11:                              /* 7.1.47 POP */
 669                 if ((tinstr & (3 << 9)) == 0x0400) {
 670                         static const u32 subset[4] = {
 671                                 0xe92d0000,     /* STMDB sp!,{registers} */
 672                                 0xe92d4000,     /* STMDB sp!,{registers,lr} */
 673                                 0xe8bd0000,     /* LDMIA sp!,{registers} */
 674                                 0xe8bd8000      /* LDMIA sp!,{registers,pc} */
 675                         };
 676                         return subset[(L<<1) | ((tinstr & (1<<8)) >> 8)] |
 677                             (tinstr & 255);             /* register_list */
 678                 }
 679                 /* Else fall through for illegal instruction case */
 680
 681         default:
 682                 return BAD_INSTR;
 683         }
 684 }
 685
 686 /*
 687  * Convert Thumb-2 32 bit LDM, STM, LDRD, STRD to equivalent instruction
 688  * handlable by ARM alignment handler, also find the corresponding handler,
 689  * so that we can reuse ARM userland alignment fault fixups for Thumb.
 690  *
 691  * @pinstr: original Thumb-2 instruction; returns new handlable instruction
 692  * @regs: register context.
 693  * @poffset: return offset from faulted addr for later writeback
 694  *
 695  * NOTES:
 696  * 1. Comments below refer to ARMv7 DDI0406A Thumb Instruction sections.
 697  * 2. Register name Rt from ARMv7 is same as Rd from ARMv6 (Rd is Rt)
 698  */
 699 static void *
 700 do_alignment_t32_to_handler(unsigned long *pinstr, struct pt_regs *regs,
 701                             union offset_union *poffset)
 702 {
 703         unsigned long instr = *pinstr;
 704         u16 tinst1 = (instr >> 16) & 0xffff;
 705         u16 tinst2 = instr & 0xffff;
 706
 707         switch (tinst1 & 0xffe0) {
 708         /* A6.3.5 Load/Store multiple */
 709         case 0xe880:            /* STM/STMIA/STMEA,LDM/LDMIA, PUSH/POP T2 */
 710         case 0xe8a0:            /* ...above writeback version */
 711         case 0xe900:            /* STMDB/STMFD, LDMDB/LDMEA */
 712         case 0xe920:            /* ...above writeback version */
 713                 /* no need offset decision since handler calculates it */
 714                 return do_alignment_ldmstm;
 715
 716         case 0xf840:            /* POP/PUSH T3 (single register) */
 717                 if (RN_BITS(instr) == 13 && (tinst2 & 0x09ff) == 0x0904) {
 718                         u32 L = !!(LDST_L_BIT(instr));
 719                         const u32 subset[2] = {
 720                                 0xe92d0000,     /* STMDB sp!,{registers} */
 721                                 0xe8bd0000,     /* LDMIA sp!,{registers} */
 722                         };
 723                         *pinstr = subset[L] | (1<<RD_BITS(instr));
 724                         return do_alignment_ldmstm;
 725                 }
 726                 /* Else fall through for illegal instruction case */
 727                 break;
 728
 729         /* A6.3.6 Load/store double, STRD/LDRD(immed, lit, reg) */
 730         case 0xe860:
 731         case 0xe960:
 732         case 0xe8e0:
 733         case 0xe9e0:
 734                 poffset->un = (tinst2 & 0xff) << 2;
 735         case 0xe940:
 736         case 0xe9c0:
 737                 return do_alignment_ldrdstrd;
 738
 739         /*
 740          * No need to handle load/store instructions up to word size
 741          * since ARMv6 and later CPUs can perform unaligned accesses.
 742          */
 743         default:
 744                 break;
 745         }
 746         return NULL;
 747 }
 748
 749 static int
 750 do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
 751 {
 752         union offset_union uninitialized_var(offset);
 753         unsigned long instr = 0, instrptr;
 754         int (*handler)(unsigned long addr, unsigned long instr, struct pt_regs *regs);
 755         unsigned int type;
 756         unsigned int fault;
 757         u16 tinstr = 0;
 758         int isize = 4;
 759         int thumb2_32b = 0;
 760
 761         if (interrupts_enabled(regs))
 762                 local_irq_enable();
 763
 764         instrptr = instruction_pointer(regs);
 765
 766         if (thumb_mode(regs)) {
 767                 u16 *ptr = (u16 *)(instrptr & ~1);
 768                 fault = probe_kernel_address(ptr, tinstr);
 769                 tinstr = __mem_to_opcode_thumb16(tinstr);
 770                 if (!fault) {
 771                         if (cpu_architecture() >= CPU_ARCH_ARMv7 &&
 772                             IS_T32(tinstr)) {
 773                                 /* Thumb-2 32-bit */
 774                                 u16 tinst2 = 0;
 775                                 fault = probe_kernel_address(ptr + 1, tinst2);
 776                                 tinst2 = __mem_to_opcode_thumb16(tinst2);
 777                                 instr = __opcode_thumb32_compose(tinstr, tinst2);
 778                                 thumb2_32b = 1;
 779                         } else {
 780                                 isize = 2;
 781                                 instr = thumb2arm(tinstr);
 782                         }
 783                 }
 784         } else {
 785                 fault = probe_kernel_address(instrptr, instr);
 786                 instr = __mem_to_opcode_arm(instr);
 787         }
 788
 789         if (fault) {
 790                 type = TYPE_FAULT;
 791                 goto bad_or_fault;
 792         }
 793
 794         if (user_mode(regs))
 795                 goto user;
 796
 797         ai_sys += 1;
 798         ai_sys_last_pc = (void *)instruction_pointer(regs);
 799
 800  fixup:
 801
 802         regs->ARM_pc += isize;
 803
 804         switch (CODING_BITS(instr)) {
 805         case 0x00000000:        /* 3.13.4 load/store instruction extensions */
 806                 if (LDSTHD_I_BIT(instr))
 807                         offset.un = (instr & 0xf00) >> 4 | (instr & 15);
 808                 else
 809                         offset.un = regs->uregs[RM_BITS(instr)];
 810
 811                 if ((instr & 0x000000f0) == 0x000000b0 || /* LDRH, STRH */
 812                     (instr & 0x001000f0) == 0x001000f0)   /* LDRSH */
 813                         handler = do_alignment_ldrhstrh;
 814                 else if ((instr & 0x001000f0) == 0x000000d0 || /* LDRD */
 815                          (instr & 0x001000f0) == 0x000000f0)   /* STRD */
 816                         handler = do_alignment_ldrdstrd;
 817                 else if ((instr & 0x01f00ff0) == 0x01000090) /* SWP */
 818                         goto swp;
 819                 else
 820                         goto bad;
 821                 break;
 822
 823         case 0x04000000:        /* ldr or str immediate */
 824                 offset.un = OFFSET_BITS(instr);
 825                 handler = do_alignment_ldrstr;
 826                 break;
 827
 828         case 0x06000000:        /* ldr or str register */
 829                 offset.un = regs->uregs[RM_BITS(instr)];
 830
 831                 if (IS_SHIFT(instr)) {
 832                         unsigned int shiftval = SHIFT_BITS(instr);
 833
 834                         switch(SHIFT_TYPE(instr)) {
 835                         case SHIFT_LSL:
 836                                 offset.un <<= shiftval;
 837                                 break;
 838
 839                         case SHIFT_LSR:
 840                                 offset.un >>= shiftval;
 841                                 break;
 842
 843                         case SHIFT_ASR:
 844                                 offset.sn >>= shiftval;
 845                                 break;
 846
 847                         case SHIFT_RORRRX:
 848                                 if (shiftval == 0) {
 849                                         offset.un >>= 1;
 850                                         if (regs->ARM_cpsr & PSR_C_BIT)
 851                                                 offset.un |= 1 << 31;
 852                                 } else
 853                                         offset.un = offset.un >> shiftval |
 854                                                           offset.un << (32 - shiftval);
 855                                 break;
 856                         }
 857                 }
 858                 handler = do_alignment_ldrstr;
 859                 break;
 860
 861         case 0x08000000:        /* ldm or stm, or thumb-2 32bit instruction */
 862                 if (thumb2_32b) {
 863                         offset.un = 0;
 864                         handler = do_alignment_t32_to_handler(&instr, regs, &offset);
 865                 } else {
 866                         offset.un = 0;
 867                         handler = do_alignment_ldmstm;
 868                 }
 869                 break;
 870
 871         default:
 872                 goto bad;
 873         }
 874
 875         if (!handler)
 876                 goto bad;
 877         type = handler(addr, instr, regs);
 878
 879         if (type == TYPE_ERROR || type == TYPE_FAULT) {
 880                 regs->ARM_pc -= isize;
 881                 goto bad_or_fault;
 882         }
 883
 884         if (type == TYPE_LDST)
 885                 do_alignment_finish_ldst(addr, instr, regs, offset);
 886
 887         return 0;
 888
 889  bad_or_fault:
 890         if (type == TYPE_ERROR)
 891                 goto bad;
 892         /*
 893          * We got a fault - fix it up, or die.
 894          */
 895         do_bad_area(addr, fsr, regs);
 896         return 0;
 897
 898  swp:
 899         printk(KERN_ERR "Alignment trap: not handling swp instruction\n");
 900
 901  bad:
 902         /*
 903          * Oops, we didn't handle the instruction.
 904          */
 905         printk(KERN_ERR "Alignment trap: not handling instruction "
 906                 "%0*lx at [<%08lx>]\n",
 907                 isize << 1,
 908                 isize == 2 ? tinstr : instr, instrptr);
 909         ai_skipped += 1;
 910         return 1;
 911
 912  user:
 913         ai_user += 1;
 914
 915         if (ai_usermode & UM_WARN)
 916                 printk("Alignment trap: %s (%d) PC=0x%08lx Instr=0x%0*lx "
 917                        "Address=0x%08lx FSR 0x%03x\n", current->comm,
 918                         task_pid_nr(current), instrptr,
 919                         isize << 1,
 920                         isize == 2 ? tinstr : instr,
 921                         addr, fsr);
 922
 923         if (ai_usermode & UM_FIXUP)
 924                 goto fixup;
 925
 926         if (ai_usermode & UM_SIGNAL) {
 927                 siginfo_t si;
 928
 929                 si.si_signo = SIGBUS;
 930                 si.si_errno = 0;
 931                 si.si_code = BUS_ADRALN;
 932                 si.si_addr = (void __user *)addr;
 933
 934                 force_sig_info(si.si_signo, &si, current);
 935         } else {
 936                 /*
 937                  * We're about to disable the alignment trap and return to
 938                  * user space.  But if an interrupt occurs before actually
 939                  * reaching user space, then the IRQ vector entry code will
 940                  * notice that we were still in kernel space and therefore
 941                  * the alignment trap won't be re-enabled in that case as it
 942                  * is presumed to be always on from kernel space.
 943                  * Let's prevent that race by disabling interrupts here (they
 944                  * are disabled on the way back to user space anyway in
 945                  * entry-common.S) and disable the alignment trap only if
 946                  * there is no work pending for this thread.
 947                  */
 948                 raw_local_irq_disable();
 949                 if (!(current_thread_info()->flags & _TIF_WORK_MASK))
 950                         set_cr(cr_no_alignment);
 951         }
 952
 953         return 0;
 954 }
 955
 956 static int __init noalign_setup(char *__unused)
 957 {
 958         set_cr(__clear_cr(CR_A));
 959         return 1;
 960 }
 961 __setup("noalign", noalign_setup);
 962
 963 /*
 964  * This needs to be done after sysctl_init, otherwise sys/ will be
 965  * overwritten.  Actually, this shouldn't be in sys/ at all since
 966  * it isn't a sysctl, and it doesn't contain sysctl information.
 967  * We now locate it in /proc/cpu/alignment instead.
 968  */
 969 static int __init alignment_init(void)
 970 {
 971 #ifdef CONFIG_PROC_FS
 972         struct proc_dir_entry *res;
 973
 974         res = proc_create("cpu/alignment", S_IWUSR | S_IRUGO, NULL,
 975                           &alignment_proc_fops);
 976         if (!res)
 977                 return -ENOMEM;
 978 #endif
 979
 980         if (cpu_is_v6_unaligned()) {
 981                 set_cr(__clear_cr(CR_A));
 982                 ai_usermode = safe_usermode(ai_usermode, false);
 983         }
 984
 985         cr_no_alignment = get_cr() & ~CR_A;
 986
 987         hook_fault_code(FAULT_CODE_ALIGNMENT, do_alignment, SIGBUS, BUS_ADRALN,
 988                         "alignment exception");
 989
 990         /*
 991          * ARMv6K and ARMv7 use fault status 3 (0b00011) as Access Flag section
 992          * fault, not as alignment error.
 993          *
 994          * TODO: handle ARMv6K properly. Runtime check for 'K' extension is
 995          * needed.
 996          */
 997         if (cpu_architecture() <= CPU_ARCH_ARMv6) {
 998                 hook_fault_code(3, do_alignment, SIGBUS, BUS_ADRALN,
 999                                 "alignment exception");
1000         }
1001
1002         return 0;
1003 }
1004
1005 fs_initcall(alignment_init);