Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mszeredi...
[pandora-kernel.git] / arch / arm / mach-vt8500 / timer.c
1 /*
2  *  arch/arm/mach-vt8500/timer.c
3  *
4  *  Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
19  */
20
21 #include <linux/io.h>
22 #include <linux/irq.h>
23 #include <linux/interrupt.h>
24 #include <linux/clocksource.h>
25 #include <linux/clockchips.h>
26 #include <linux/delay.h>
27
28 #include <asm/mach/time.h>
29
30 #include "devices.h"
31
32 #define VT8500_TIMER_OFFSET     0x0100
33 #define TIMER_MATCH_VAL         0x0000
34 #define TIMER_COUNT_VAL         0x0010
35 #define TIMER_STATUS_VAL        0x0014
36 #define TIMER_IER_VAL           0x001c          /* interrupt enable */
37 #define TIMER_CTRL_VAL          0x0020
38 #define TIMER_AS_VAL            0x0024          /* access status */
39 #define TIMER_COUNT_R_ACTIVE    (1 << 5)        /* not ready for read */
40 #define TIMER_COUNT_W_ACTIVE    (1 << 4)        /* not ready for write */
41 #define TIMER_MATCH_W_ACTIVE    (1 << 0)        /* not ready for write */
42 #define VT8500_TIMER_HZ         3000000
43
44 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
45
46 static void __iomem *regbase;
47
48 static cycle_t vt8500_timer_read(struct clocksource *cs)
49 {
50         int loops = msecs_to_loops(10);
51         writel(3, regbase + TIMER_CTRL_VAL);
52         while ((readl((regbase + TIMER_AS_VAL)) & TIMER_COUNT_R_ACTIVE)
53                                                 && --loops)
54                 cpu_relax();
55         return readl(regbase + TIMER_COUNT_VAL);
56 }
57
58 struct clocksource clocksource = {
59         .name           = "vt8500_timer",
60         .rating         = 200,
61         .read           = vt8500_timer_read,
62         .mask           = CLOCKSOURCE_MASK(32),
63         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
64 };
65
66 static int vt8500_timer_set_next_event(unsigned long cycles,
67                                     struct clock_event_device *evt)
68 {
69         int loops = msecs_to_loops(10);
70         cycle_t alarm = clocksource.read(&clocksource) + cycles;
71         while ((readl(regbase + TIMER_AS_VAL) & TIMER_MATCH_W_ACTIVE)
72                                                 && --loops)
73                 cpu_relax();
74         writel((unsigned long)alarm, regbase + TIMER_MATCH_VAL);
75
76         if ((signed)(alarm - clocksource.read(&clocksource)) <= 16)
77                 return -ETIME;
78
79         writel(1, regbase + TIMER_IER_VAL);
80
81         return 0;
82 }
83
84 static void vt8500_timer_set_mode(enum clock_event_mode mode,
85                               struct clock_event_device *evt)
86 {
87         switch (mode) {
88         case CLOCK_EVT_MODE_RESUME:
89         case CLOCK_EVT_MODE_PERIODIC:
90                 break;
91         case CLOCK_EVT_MODE_ONESHOT:
92         case CLOCK_EVT_MODE_UNUSED:
93         case CLOCK_EVT_MODE_SHUTDOWN:
94                 writel(readl(regbase + TIMER_CTRL_VAL) | 1,
95                         regbase + TIMER_CTRL_VAL);
96                 writel(0, regbase + TIMER_IER_VAL);
97                 break;
98         }
99 }
100
101 struct clock_event_device clockevent = {
102         .name           = "vt8500_timer",
103         .features       = CLOCK_EVT_FEAT_ONESHOT,
104         .rating         = 200,
105         .set_next_event = vt8500_timer_set_next_event,
106         .set_mode       = vt8500_timer_set_mode,
107 };
108
109 static irqreturn_t vt8500_timer_interrupt(int irq, void *dev_id)
110 {
111         struct clock_event_device *evt = dev_id;
112         writel(0xf, regbase + TIMER_STATUS_VAL);
113         evt->event_handler(evt);
114
115         return IRQ_HANDLED;
116 }
117
118 struct irqaction irq = {
119         .name    = "vt8500_timer",
120         .flags   = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
121         .handler = vt8500_timer_interrupt,
122         .dev_id  = &clockevent,
123 };
124
125 static void __init vt8500_timer_init(void)
126 {
127         regbase = ioremap(wmt_pmc_base + VT8500_TIMER_OFFSET, 0x28);
128         if (!regbase)
129                 printk(KERN_ERR "vt8500_timer_init: failed to map MMIO registers\n");
130
131         writel(1, regbase + TIMER_CTRL_VAL);
132         writel(0xf, regbase + TIMER_STATUS_VAL);
133         writel(~0, regbase + TIMER_MATCH_VAL);
134
135         if (clocksource_register_hz(&clocksource, VT8500_TIMER_HZ))
136                 printk(KERN_ERR "vt8500_timer_init: clocksource_register failed for %s\n",
137                                         clocksource.name);
138
139         clockevents_calc_mult_shift(&clockevent, VT8500_TIMER_HZ, 4);
140
141         /* copy-pasted from mach-msm; no idea */
142         clockevent.max_delta_ns =
143                 clockevent_delta2ns(0xf0000000, &clockevent);
144         clockevent.min_delta_ns = clockevent_delta2ns(4, &clockevent);
145         clockevent.cpumask = cpumask_of(0);
146
147         if (setup_irq(wmt_timer_irq, &irq))
148                 printk(KERN_ERR "vt8500_timer_init: setup_irq failed for %s\n",
149                                         clockevent.name);
150         clockevents_register_device(&clockevent);
151 }
152
153 struct sys_timer vt8500_timer = {
154         .init = vt8500_timer_init
155 };