arch/arm/mach-vt8500/irq.c

   1 /*
   2  *  arch/arm/mach-vt8500/irq.c
   3  *
   4  *  Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20
  21 #include <linux/io.h>
  22 #include <linux/irq.h>
  23 #include <linux/interrupt.h>
  24
  25 #include <asm/irq.h>
  26
  27 #include "devices.h"
  28
  29 #define VT8500_IC_DCTR          0x40            /* Destination control
  30                                                 register, 64*u8 */
  31 #define VT8500_INT_ENABLE       (1 << 3)
  32 #define VT8500_TRIGGER_HIGH     (0 << 4)
  33 #define VT8500_TRIGGER_RISING   (1 << 4)
  34 #define VT8500_TRIGGER_FALLING  (2 << 4)
  35 #define VT8500_EDGE             ( VT8500_TRIGGER_RISING \
  36                                 | VT8500_TRIGGER_FALLING)
  37 #define VT8500_IC_STATUS        0x80            /* Interrupt status, 2*u32 */
  38
  39 static void __iomem *ic_regbase;
  40 static void __iomem *sic_regbase;
  41
  42 static void vt8500_irq_mask(unsigned int irq)
  43 {
  44         void __iomem *base = ic_regbase;
  45         u8 edge;
  46
  47         if (irq >= 64) {
  48                 base = sic_regbase;
  49                 irq -= 64;
  50         }
  51         edge = readb(base + VT8500_IC_DCTR + irq) & VT8500_EDGE;
  52         if (edge) {
  53                 void __iomem *stat_reg = base + VT8500_IC_STATUS
  54                                                 + (irq < 32 ? 0 : 4);
  55                 unsigned status = readl(stat_reg);
  56
  57                 status |= (1 << (irq & 0x1f));
  58                 writel(status, stat_reg);
  59         } else {
  60                 u8 dctr = readb(base + VT8500_IC_DCTR + irq);
  61
  62                 dctr &= ~VT8500_INT_ENABLE;
  63                 writeb(dctr, base + VT8500_IC_DCTR + irq);
  64         }
  65 }
  66
  67 static void vt8500_irq_unmask(unsigned int irq)
  68 {
  69         void __iomem *base = ic_regbase;
  70         u8 dctr;
  71
  72         if (irq >= 64) {
  73                 base = sic_regbase;
  74                 irq -= 64;
  75         }
  76         dctr = readb(base + VT8500_IC_DCTR + irq);
  77         dctr |= VT8500_INT_ENABLE;
  78         writeb(dctr, base + VT8500_IC_DCTR + irq);
  79 }
  80
  81 static int vt8500_irq_set_type(unsigned int irq, unsigned int flow_type)
  82 {
  83         void __iomem *base = ic_regbase;
  84         unsigned int orig_irq = irq;
  85         u8 dctr;
  86
  87         if (irq >= 64) {
  88                 base = sic_regbase;
  89                 irq -= 64;
  90         }
  91
  92         dctr = readb(base + VT8500_IC_DCTR + irq);
  93         dctr &= ~VT8500_EDGE;
  94
  95         switch (flow_type) {
  96         case IRQF_TRIGGER_LOW:
  97                 return -EINVAL;
  98         case IRQF_TRIGGER_HIGH:
  99                 dctr |= VT8500_TRIGGER_HIGH;
 100                 __irq_set_handler_locked(orig_irq, handle_level_irq);
 101                 break;
 102         case IRQF_TRIGGER_FALLING:
 103                 dctr |= VT8500_TRIGGER_FALLING;
 104                 __irq_set_handler_locked(orig_irq, handle_edge_irq);
 105                 break;
 106         case IRQF_TRIGGER_RISING:
 107                 dctr |= VT8500_TRIGGER_RISING;
 108                 __irq_set_handler_locked(orig_irq, handle_edge_irq);
 109                 break;
 110         }
 111         writeb(dctr, base + VT8500_IC_DCTR + irq);
 112
 113         return 0;
 114 }
 115
 116 static struct irq_chip vt8500_irq_chip = {
 117         .name      = "vt8500",
 118         .ack       = vt8500_irq_mask,
 119         .mask      = vt8500_irq_mask,
 120         .unmask    = vt8500_irq_unmask,
 121         .set_type  = vt8500_irq_set_type,
 122 };
 123
 124 void __init vt8500_init_irq(void)
 125 {
 126         unsigned int i;
 127
 128         ic_regbase = ioremap(wmt_ic_base, SZ_64K);
 129
 130         if (ic_regbase) {
 131                 /* Enable rotating priority for IRQ */
 132                 writel((1 << 6), ic_regbase + 0x20);
 133                 writel(0, ic_regbase + 0x24);
 134
 135                 for (i = 0; i < wmt_nr_irqs; i++) {
 136                         /* Disable all interrupts and route them to IRQ */
 137                         writeb(0x00, ic_regbase + VT8500_IC_DCTR + i);
 138
 139                         irq_set_chip_and_handler(i, &vt8500_irq_chip,
 140                                                  handle_level_irq);
 141                         set_irq_flags(i, IRQF_VALID);
 142                 }
 143         } else {
 144                 printk(KERN_ERR "Unable to remap the Interrupt Controller registers, not enabling IRQs!\n");
 145         }
 146 }
 147
 148 void __init wm8505_init_irq(void)
 149 {
 150         unsigned int i;
 151
 152         ic_regbase = ioremap(wmt_ic_base, SZ_64K);
 153         sic_regbase = ioremap(wmt_sic_base, SZ_64K);
 154
 155         if (ic_regbase && sic_regbase) {
 156                 /* Enable rotating priority for IRQ */
 157                 writel((1 << 6), ic_regbase + 0x20);
 158                 writel(0, ic_regbase + 0x24);
 159                 writel((1 << 6), sic_regbase + 0x20);
 160                 writel(0, sic_regbase + 0x24);
 161
 162                 for (i = 0; i < wmt_nr_irqs; i++) {
 163                         /* Disable all interrupts and route them to IRQ */
 164                         if (i < 64)
 165                                 writeb(0x00, ic_regbase + VT8500_IC_DCTR + i);
 166                         else
 167                                 writeb(0x00, sic_regbase + VT8500_IC_DCTR
 168                                                                 + i - 64);
 169
 170                         irq_set_chip_and_handler(i, &vt8500_irq_chip,
 171                                                  handle_level_irq);
 172                         set_irq_flags(i, IRQF_VALID);
 173                 }
 174         } else {
 175                 printk(KERN_ERR "Unable to remap the Interrupt Controller registers, not enabling IRQs!\n");
 176         }
 177 }