arch/arm/mach-vexpress/ct-ca9x4.c

   1 /*
   2  * Versatile Express Core Tile Cortex A9x4 Support
   3  */
   4 #include <linux/init.h>
   5 #include <linux/gfp.h>
   6 #include <linux/device.h>
   7 #include <linux/dma-mapping.h>
   8 #include <linux/platform_device.h>
   9 #include <linux/amba/bus.h>
  10 #include <linux/amba/clcd.h>
  11
  12 #include <asm/clkdev.h>
  13 #include <asm/pgtable.h>
  14 #include <asm/hardware/arm_timer.h>
  15 #include <asm/hardware/cache-l2x0.h>
  16 #include <asm/hardware/gic.h>
  17 #include <asm/mach-types.h>
  18 #include <asm/pmu.h>
  19 #include <asm/smp_twd.h>
  20
  21 #include <mach/clkdev.h>
  22 #include <mach/ct-ca9x4.h>
  23
  24 #include <plat/timer-sp.h>
  25
  26 #include <asm/mach/arch.h>
  27 #include <asm/mach/map.h>
  28 #include <asm/mach/time.h>
  29
  30 #include "core.h"
  31
  32 #include <mach/motherboard.h>
  33
  34 #define V2M_PA_CS7      0x10000000
  35
  36 static struct map_desc ct_ca9x4_io_desc[] __initdata = {
  37         {
  38                 .virtual        = __MMIO_P2V(CT_CA9X4_MPIC),
  39                 .pfn            = __phys_to_pfn(CT_CA9X4_MPIC),
  40                 .length         = SZ_16K,
  41                 .type           = MT_DEVICE,
  42         }, {
  43                 .virtual        = __MMIO_P2V(CT_CA9X4_SP804_TIMER),
  44                 .pfn            = __phys_to_pfn(CT_CA9X4_SP804_TIMER),
  45                 .length         = SZ_4K,
  46                 .type           = MT_DEVICE,
  47         }, {
  48                 .virtual        = __MMIO_P2V(CT_CA9X4_L2CC),
  49                 .pfn            = __phys_to_pfn(CT_CA9X4_L2CC),
  50                 .length         = SZ_4K,
  51                 .type           = MT_DEVICE,
  52         },
  53 };
  54
  55 static void __init ct_ca9x4_map_io(void)
  56 {
  57 #ifdef CONFIG_LOCAL_TIMERS
  58         twd_base = MMIO_P2V(A9_MPCORE_TWD);
  59 #endif
  60         v2m_map_io(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
  61 }
  62
  63 void __iomem *gic_cpu_base_addr;
  64
  65 static void __init ct_ca9x4_init_irq(void)
  66 {
  67         gic_cpu_base_addr = MMIO_P2V(A9_MPCORE_GIC_CPU);
  68         gic_dist_init(0, MMIO_P2V(A9_MPCORE_GIC_DIST), 29);
  69         gic_cpu_init(0, gic_cpu_base_addr);
  70 }
  71
  72 #if 0
  73 static void __init ct_ca9x4_timer_init(void)
  74 {
  75         writel(0, MMIO_P2V(CT_CA9X4_TIMER0) + TIMER_CTRL);
  76         writel(0, MMIO_P2V(CT_CA9X4_TIMER1) + TIMER_CTRL);
  77
  78         sp804_clocksource_init(MMIO_P2V(CT_CA9X4_TIMER1));
  79         sp804_clockevents_init(MMIO_P2V(CT_CA9X4_TIMER0), IRQ_CT_CA9X4_TIMER0);
  80 }
  81
  82 static struct sys_timer ct_ca9x4_timer = {
  83         .init   = ct_ca9x4_timer_init,
  84 };
  85 #endif
  86
  87 static struct clcd_panel xvga_panel = {
  88         .mode           = {
  89                 .name           = "XVGA",
  90                 .refresh        = 60,
  91                 .xres           = 1024,
  92                 .yres           = 768,
  93                 .pixclock       = 15384,
  94                 .left_margin    = 168,
  95                 .right_margin   = 8,
  96                 .upper_margin   = 29,
  97                 .lower_margin   = 3,
  98                 .hsync_len      = 144,
  99                 .vsync_len      = 6,
 100                 .sync           = 0,
 101                 .vmode          = FB_VMODE_NONINTERLACED,
 102         },
 103         .width          = -1,
 104         .height         = -1,
 105         .tim2           = TIM2_BCD | TIM2_IPC,
 106         .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
 107         .bpp            = 16,
 108 };
 109
 110 static void ct_ca9x4_clcd_enable(struct clcd_fb *fb)
 111 {
 112         v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE_DB1, 0);
 113         v2m_cfg_write(SYS_CFG_DVIMODE | SYS_CFG_SITE_DB1, 2);
 114 }
 115
 116 static int ct_ca9x4_clcd_setup(struct clcd_fb *fb)
 117 {
 118         unsigned long framesize = 1024 * 768 * 2;
 119         dma_addr_t dma;
 120
 121         fb->panel = &xvga_panel;
 122
 123         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
 124                                 &dma, GFP_KERNEL);
 125         if (!fb->fb.screen_base) {
 126                 printk(KERN_ERR "CLCD: unable to map frame buffer\n");
 127                 return -ENOMEM;
 128         }
 129         fb->fb.fix.smem_start = dma;
 130         fb->fb.fix.smem_len = framesize;
 131
 132         return 0;
 133 }
 134
 135 static int ct_ca9x4_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
 136 {
 137         return dma_mmap_writecombine(&fb->dev->dev, vma, fb->fb.screen_base,
 138                 fb->fb.fix.smem_start, fb->fb.fix.smem_len);
 139 }
 140
 141 static void ct_ca9x4_clcd_remove(struct clcd_fb *fb)
 142 {
 143         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
 144                 fb->fb.screen_base, fb->fb.fix.smem_start);
 145 }
 146
 147 static struct clcd_board ct_ca9x4_clcd_data = {
 148         .name           = "CT-CA9X4",
 149         .check          = clcdfb_check,
 150         .decode         = clcdfb_decode,
 151         .enable         = ct_ca9x4_clcd_enable,
 152         .setup          = ct_ca9x4_clcd_setup,
 153         .mmap           = ct_ca9x4_clcd_mmap,
 154         .remove         = ct_ca9x4_clcd_remove,
 155 };
 156
 157 static AMBA_DEVICE(clcd, "ct:clcd", CT_CA9X4_CLCDC, &ct_ca9x4_clcd_data);
 158 static AMBA_DEVICE(dmc, "ct:dmc", CT_CA9X4_DMC, NULL);
 159 static AMBA_DEVICE(smc, "ct:smc", CT_CA9X4_SMC, NULL);
 160 static AMBA_DEVICE(gpio, "ct:gpio", CT_CA9X4_GPIO, NULL);
 161
 162 static struct amba_device *ct_ca9x4_amba_devs[] __initdata = {
 163         &clcd_device,
 164         &dmc_device,
 165         &smc_device,
 166         &gpio_device,
 167 };
 168
 169
 170 static long ct_round(struct clk *clk, unsigned long rate)
 171 {
 172         return rate;
 173 }
 174
 175 static int ct_set(struct clk *clk, unsigned long rate)
 176 {
 177         return v2m_cfg_write(SYS_CFG_OSC | SYS_CFG_SITE_DB1 | 1, rate);
 178 }
 179
 180 static const struct clk_ops osc1_clk_ops = {
 181         .round  = ct_round,
 182         .set    = ct_set,
 183 };
 184
 185 static struct clk osc1_clk = {
 186         .ops    = &osc1_clk_ops,
 187         .rate   = 24000000,
 188 };
 189
 190 static struct clk_lookup lookups[] = {
 191         {       /* CLCD */
 192                 .dev_id         = "ct:clcd",
 193                 .clk            = &osc1_clk,
 194         },
 195 };
 196
 197 static struct resource pmu_resources[] = {
 198         [0] = {
 199                 .start  = IRQ_CT_CA9X4_PMU_CPU0,
 200                 .end    = IRQ_CT_CA9X4_PMU_CPU0,
 201                 .flags  = IORESOURCE_IRQ,
 202         },
 203         [1] = {
 204                 .start  = IRQ_CT_CA9X4_PMU_CPU1,
 205                 .end    = IRQ_CT_CA9X4_PMU_CPU1,
 206                 .flags  = IORESOURCE_IRQ,
 207         },
 208         [2] = {
 209                 .start  = IRQ_CT_CA9X4_PMU_CPU2,
 210                 .end    = IRQ_CT_CA9X4_PMU_CPU2,
 211                 .flags  = IORESOURCE_IRQ,
 212         },
 213         [3] = {
 214                 .start  = IRQ_CT_CA9X4_PMU_CPU3,
 215                 .end    = IRQ_CT_CA9X4_PMU_CPU3,
 216                 .flags  = IORESOURCE_IRQ,
 217         },
 218 };
 219
 220 static struct platform_device pmu_device = {
 221         .name           = "arm-pmu",
 222         .id             = ARM_PMU_DEVICE_CPU,
 223         .num_resources  = ARRAY_SIZE(pmu_resources),
 224         .resource       = pmu_resources,
 225 };
 226
 227 static void __init ct_ca9x4_init(void)
 228 {
 229         int i;
 230
 231 #ifdef CONFIG_CACHE_L2X0
 232         void __iomem *l2x0_base = MMIO_P2V(CT_CA9X4_L2CC);
 233
 234         /* set RAM latencies to 1 cycle for this core tile. */
 235         writel(0, l2x0_base + L2X0_TAG_LATENCY_CTRL);
 236         writel(0, l2x0_base + L2X0_DATA_LATENCY_CTRL);
 237
 238         l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff);
 239 #endif
 240
 241         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 242
 243         for (i = 0; i < ARRAY_SIZE(ct_ca9x4_amba_devs); i++)
 244                 amba_device_register(ct_ca9x4_amba_devs[i], &iomem_resource);
 245
 246         platform_device_register(&pmu_device);
 247 }
 248
 249 MACHINE_START(VEXPRESS, "ARM-Versatile Express CA9x4")
 250         .boot_params    = PHYS_OFFSET + 0x00000100,
 251         .map_io         = ct_ca9x4_map_io,
 252         .init_irq       = ct_ca9x4_init_irq,
 253 #if 0
 254         .timer          = &ct_ca9x4_timer,
 255 #else
 256         .timer          = &v2m_timer,
 257 #endif
 258         .init_machine   = ct_ca9x4_init,
 259 MACHINE_END