arch/arm/mach-versatile/core.c

   1 /*
   2  *  linux/arch/arm/mach-versatile/core.c
   3  *
   4  *  Copyright (C) 1999 - 2003 ARM Limited
   5  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21 #include <linux/init.h>
  22 #include <linux/device.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/sysdev.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/amba/bus.h>
  28 #include <linux/amba/clcd.h>
  29 #include <linux/clocksource.h>
  30 #include <linux/clockchips.h>
  31 #include <linux/cnt32_to_63.h>
  32 #include <linux/io.h>
  33
  34 #include <asm/clkdev.h>
  35 #include <asm/system.h>
  36 #include <mach/hardware.h>
  37 #include <asm/irq.h>
  38 #include <asm/leds.h>
  39 #include <asm/hardware/arm_timer.h>
  40 #include <asm/hardware/icst307.h>
  41 #include <asm/hardware/vic.h>
  42 #include <asm/mach-types.h>
  43
  44 #include <asm/mach/arch.h>
  45 #include <asm/mach/flash.h>
  46 #include <asm/mach/irq.h>
  47 #include <asm/mach/time.h>
  48 #include <asm/mach/map.h>
  49 #include <asm/mach/mmc.h>
  50
  51 #include "core.h"
  52 #include "clock.h"
  53
  54 /*
  55  * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
  56  * is the (PA >> 12).
  57  *
  58  * Setup a VA for the Versatile Vectored Interrupt Controller.
  59  */
  60 #define __io_address(n)         __io(IO_ADDRESS(n))
  61 #define VA_VIC_BASE             __io_address(VERSATILE_VIC_BASE)
  62 #define VA_SIC_BASE             __io_address(VERSATILE_SIC_BASE)
  63
  64 static void sic_mask_irq(unsigned int irq)
  65 {
  66         irq -= IRQ_SIC_START;
  67         writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
  68 }
  69
  70 static void sic_unmask_irq(unsigned int irq)
  71 {
  72         irq -= IRQ_SIC_START;
  73         writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_SET);
  74 }
  75
  76 static struct irq_chip sic_chip = {
  77         .name   = "SIC",
  78         .ack    = sic_mask_irq,
  79         .mask   = sic_mask_irq,
  80         .unmask = sic_unmask_irq,
  81 };
  82
  83 static void
  84 sic_handle_irq(unsigned int irq, struct irq_desc *desc)
  85 {
  86         unsigned long status = readl(VA_SIC_BASE + SIC_IRQ_STATUS);
  87
  88         if (status == 0) {
  89                 do_bad_IRQ(irq, desc);
  90                 return;
  91         }
  92
  93         do {
  94                 irq = ffs(status) - 1;
  95                 status &= ~(1 << irq);
  96
  97                 irq += IRQ_SIC_START;
  98
  99                 generic_handle_irq(irq);
 100         } while (status);
 101 }
 102
 103 #if 1
 104 #define IRQ_MMCI0A      IRQ_VICSOURCE22
 105 #define IRQ_AACI        IRQ_VICSOURCE24
 106 #define IRQ_ETH         IRQ_VICSOURCE25
 107 #define PIC_MASK        0xFFD00000
 108 #else
 109 #define IRQ_MMCI0A      IRQ_SIC_MMCI0A
 110 #define IRQ_AACI        IRQ_SIC_AACI
 111 #define IRQ_ETH         IRQ_SIC_ETH
 112 #define PIC_MASK        0
 113 #endif
 114
 115 void __init versatile_init_irq(void)
 116 {
 117         unsigned int i;
 118
 119         vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0, 0);
 120
 121         set_irq_chained_handler(IRQ_VICSOURCE31, sic_handle_irq);
 122
 123         /* Do second interrupt controller */
 124         writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
 125
 126         for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
 127                 if ((PIC_MASK & (1 << (i - IRQ_SIC_START))) == 0) {
 128                         set_irq_chip(i, &sic_chip);
 129                         set_irq_handler(i, handle_level_irq);
 130                         set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 131                 }
 132         }
 133
 134         /*
 135          * Interrupts on secondary controller from 0 to 8 are routed to
 136          * source 31 on PIC.
 137          * Interrupts from 21 to 31 are routed directly to the VIC on
 138          * the corresponding number on primary controller. This is controlled
 139          * by setting PIC_ENABLEx.
 140          */
 141         writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE);
 142 }
 143
 144 static struct map_desc versatile_io_desc[] __initdata = {
 145         {
 146                 .virtual        =  IO_ADDRESS(VERSATILE_SYS_BASE),
 147                 .pfn            = __phys_to_pfn(VERSATILE_SYS_BASE),
 148                 .length         = SZ_4K,
 149                 .type           = MT_DEVICE
 150         }, {
 151                 .virtual        =  IO_ADDRESS(VERSATILE_SIC_BASE),
 152                 .pfn            = __phys_to_pfn(VERSATILE_SIC_BASE),
 153                 .length         = SZ_4K,
 154                 .type           = MT_DEVICE
 155         }, {
 156                 .virtual        =  IO_ADDRESS(VERSATILE_VIC_BASE),
 157                 .pfn            = __phys_to_pfn(VERSATILE_VIC_BASE),
 158                 .length         = SZ_4K,
 159                 .type           = MT_DEVICE
 160         }, {
 161                 .virtual        =  IO_ADDRESS(VERSATILE_SCTL_BASE),
 162                 .pfn            = __phys_to_pfn(VERSATILE_SCTL_BASE),
 163                 .length         = SZ_4K * 9,
 164                 .type           = MT_DEVICE
 165         },
 166 #ifdef CONFIG_MACH_VERSATILE_AB
 167         {
 168                 .virtual        =  IO_ADDRESS(VERSATILE_GPIO0_BASE),
 169                 .pfn            = __phys_to_pfn(VERSATILE_GPIO0_BASE),
 170                 .length         = SZ_4K,
 171                 .type           = MT_DEVICE
 172         }, {
 173                 .virtual        =  IO_ADDRESS(VERSATILE_IB2_BASE),
 174                 .pfn            = __phys_to_pfn(VERSATILE_IB2_BASE),
 175                 .length         = SZ_64M,
 176                 .type           = MT_DEVICE
 177         },
 178 #endif
 179 #ifdef CONFIG_DEBUG_LL
 180         {
 181                 .virtual        =  IO_ADDRESS(VERSATILE_UART0_BASE),
 182                 .pfn            = __phys_to_pfn(VERSATILE_UART0_BASE),
 183                 .length         = SZ_4K,
 184                 .type           = MT_DEVICE
 185         },
 186 #endif
 187 #ifdef CONFIG_PCI
 188         {
 189                 .virtual        =  IO_ADDRESS(VERSATILE_PCI_CORE_BASE),
 190                 .pfn            = __phys_to_pfn(VERSATILE_PCI_CORE_BASE),
 191                 .length         = SZ_4K,
 192                 .type           = MT_DEVICE
 193         }, {
 194                 .virtual        =  (unsigned long)VERSATILE_PCI_VIRT_BASE,
 195                 .pfn            = __phys_to_pfn(VERSATILE_PCI_BASE),
 196                 .length         = VERSATILE_PCI_BASE_SIZE,
 197                 .type           = MT_DEVICE
 198         }, {
 199                 .virtual        =  (unsigned long)VERSATILE_PCI_CFG_VIRT_BASE,
 200                 .pfn            = __phys_to_pfn(VERSATILE_PCI_CFG_BASE),
 201                 .length         = VERSATILE_PCI_CFG_BASE_SIZE,
 202                 .type           = MT_DEVICE
 203         },
 204 #if 0
 205         {
 206                 .virtual        =  VERSATILE_PCI_VIRT_MEM_BASE0,
 207                 .pfn            = __phys_to_pfn(VERSATILE_PCI_MEM_BASE0),
 208                 .length         = SZ_16M,
 209                 .type           = MT_DEVICE
 210         }, {
 211                 .virtual        =  VERSATILE_PCI_VIRT_MEM_BASE1,
 212                 .pfn            = __phys_to_pfn(VERSATILE_PCI_MEM_BASE1),
 213                 .length         = SZ_16M,
 214                 .type           = MT_DEVICE
 215         }, {
 216                 .virtual        =  VERSATILE_PCI_VIRT_MEM_BASE2,
 217                 .pfn            = __phys_to_pfn(VERSATILE_PCI_MEM_BASE2),
 218                 .length         = SZ_16M,
 219                 .type           = MT_DEVICE
 220         },
 221 #endif
 222 #endif
 223 };
 224
 225 void __init versatile_map_io(void)
 226 {
 227         iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc));
 228 }
 229
 230 #define VERSATILE_REFCOUNTER    (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_24MHz_OFFSET)
 231
 232 /*
 233  * This is the Versatile sched_clock implementation.  This has
 234  * a resolution of 41.7ns, and a maximum value of about 35583 days.
 235  *
 236  * The return value is guaranteed to be monotonic in that range as
 237  * long as there is always less than 89 seconds between successive
 238  * calls to this function.
 239  */
 240 unsigned long long sched_clock(void)
 241 {
 242         unsigned long long v = cnt32_to_63(readl(VERSATILE_REFCOUNTER));
 243
 244         /* the <<1 gets rid of the cnt_32_to_63 top bit saving on a bic insn */
 245         v *= 125<<1;
 246         do_div(v, 3<<1);
 247
 248         return v;
 249 }
 250
 251
 252 #define VERSATILE_FLASHCTRL    (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
 253
 254 static int versatile_flash_init(void)
 255 {
 256         u32 val;
 257
 258         val = __raw_readl(VERSATILE_FLASHCTRL);
 259         val &= ~VERSATILE_FLASHPROG_FLVPPEN;
 260         __raw_writel(val, VERSATILE_FLASHCTRL);
 261
 262         return 0;
 263 }
 264
 265 static void versatile_flash_exit(void)
 266 {
 267         u32 val;
 268
 269         val = __raw_readl(VERSATILE_FLASHCTRL);
 270         val &= ~VERSATILE_FLASHPROG_FLVPPEN;
 271         __raw_writel(val, VERSATILE_FLASHCTRL);
 272 }
 273
 274 static void versatile_flash_set_vpp(int on)
 275 {
 276         u32 val;
 277
 278         val = __raw_readl(VERSATILE_FLASHCTRL);
 279         if (on)
 280                 val |= VERSATILE_FLASHPROG_FLVPPEN;
 281         else
 282                 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
 283         __raw_writel(val, VERSATILE_FLASHCTRL);
 284 }
 285
 286 static struct flash_platform_data versatile_flash_data = {
 287         .map_name               = "cfi_probe",
 288         .width                  = 4,
 289         .init                   = versatile_flash_init,
 290         .exit                   = versatile_flash_exit,
 291         .set_vpp                = versatile_flash_set_vpp,
 292 };
 293
 294 static struct resource versatile_flash_resource = {
 295         .start                  = VERSATILE_FLASH_BASE,
 296         .end                    = VERSATILE_FLASH_BASE + VERSATILE_FLASH_SIZE - 1,
 297         .flags                  = IORESOURCE_MEM,
 298 };
 299
 300 static struct platform_device versatile_flash_device = {
 301         .name                   = "armflash",
 302         .id                     = 0,
 303         .dev                    = {
 304                 .platform_data  = &versatile_flash_data,
 305         },
 306         .num_resources          = 1,
 307         .resource               = &versatile_flash_resource,
 308 };
 309
 310 static struct resource smc91x_resources[] = {
 311         [0] = {
 312                 .start          = VERSATILE_ETH_BASE,
 313                 .end            = VERSATILE_ETH_BASE + SZ_64K - 1,
 314                 .flags          = IORESOURCE_MEM,
 315         },
 316         [1] = {
 317                 .start          = IRQ_ETH,
 318                 .end            = IRQ_ETH,
 319                 .flags          = IORESOURCE_IRQ,
 320         },
 321 };
 322
 323 static struct platform_device smc91x_device = {
 324         .name           = "smc91x",
 325         .id             = 0,
 326         .num_resources  = ARRAY_SIZE(smc91x_resources),
 327         .resource       = smc91x_resources,
 328 };
 329
 330 static struct resource versatile_i2c_resource = {
 331         .start                  = VERSATILE_I2C_BASE,
 332         .end                    = VERSATILE_I2C_BASE + SZ_4K - 1,
 333         .flags                  = IORESOURCE_MEM,
 334 };
 335
 336 static struct platform_device versatile_i2c_device = {
 337         .name                   = "versatile-i2c",
 338         .id                     = 0,
 339         .num_resources          = 1,
 340         .resource               = &versatile_i2c_resource,
 341 };
 342
 343 static struct i2c_board_info versatile_i2c_board_info[] = {
 344         {
 345                 I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
 346         },
 347 };
 348
 349 static int __init versatile_i2c_init(void)
 350 {
 351         return i2c_register_board_info(0, versatile_i2c_board_info,
 352                                        ARRAY_SIZE(versatile_i2c_board_info));
 353 }
 354 arch_initcall(versatile_i2c_init);
 355
 356 #define VERSATILE_SYSMCI        (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
 357
 358 unsigned int mmc_status(struct device *dev)
 359 {
 360         struct amba_device *adev = container_of(dev, struct amba_device, dev);
 361         u32 mask;
 362
 363         if (adev->res.start == VERSATILE_MMCI0_BASE)
 364                 mask = 1;
 365         else
 366                 mask = 2;
 367
 368         return readl(VERSATILE_SYSMCI) & mask;
 369 }
 370
 371 static struct mmc_platform_data mmc0_plat_data = {
 372         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 373         .status         = mmc_status,
 374 };
 375
 376 /*
 377  * Clock handling
 378  */
 379 static const struct icst307_params versatile_oscvco_params = {
 380         .ref            = 24000,
 381         .vco_max        = 200000,
 382         .vd_min         = 4 + 8,
 383         .vd_max         = 511 + 8,
 384         .rd_min         = 1 + 2,
 385         .rd_max         = 127 + 2,
 386 };
 387
 388 static void versatile_oscvco_set(struct clk *clk, struct icst307_vco vco)
 389 {
 390         void __iomem *sys = __io_address(VERSATILE_SYS_BASE);
 391         void __iomem *sys_lock = sys + VERSATILE_SYS_LOCK_OFFSET;
 392         u32 val;
 393
 394         val = readl(sys + clk->oscoff) & ~0x7ffff;
 395         val |= vco.v | (vco.r << 9) | (vco.s << 16);
 396
 397         writel(0xa05f, sys_lock);
 398         writel(val, sys + clk->oscoff);
 399         writel(0, sys_lock);
 400 }
 401
 402 static struct clk osc4_clk = {
 403         .params = &versatile_oscvco_params,
 404         .oscoff = VERSATILE_SYS_OSCCLCD_OFFSET,
 405         .setvco = versatile_oscvco_set,
 406 };
 407
 408 /*
 409  * These are fixed clocks.
 410  */
 411 static struct clk ref24_clk = {
 412         .rate   = 24000000,
 413 };
 414
 415 static struct clk_lookup lookups[] = {
 416         {       /* UART0 */
 417                 .dev_id         = "dev:f1",
 418                 .clk            = &ref24_clk,
 419         }, {    /* UART1 */
 420                 .dev_id         = "dev:f2",
 421                 .clk            = &ref24_clk,
 422         }, {    /* UART2 */
 423                 .dev_id         = "dev:f3",
 424                 .clk            = &ref24_clk,
 425         }, {    /* UART3 */
 426                 .dev_id         = "fpga:09",
 427                 .clk            = &ref24_clk,
 428         }, {    /* KMI0 */
 429                 .dev_id         = "fpga:06",
 430                 .clk            = &ref24_clk,
 431         }, {    /* KMI1 */
 432                 .dev_id         = "fpga:07",
 433                 .clk            = &ref24_clk,
 434         }, {    /* MMC0 */
 435                 .dev_id         = "fpga:05",
 436                 .clk            = &ref24_clk,
 437         }, {    /* MMC1 */
 438                 .dev_id         = "fpga:0b",
 439                 .clk            = &ref24_clk,
 440         }, {    /* CLCD */
 441                 .dev_id         = "dev:20",
 442                 .clk            = &osc4_clk,
 443         }
 444 };
 445
 446 /*
 447  * CLCD support.
 448  */
 449 #define SYS_CLCD_MODE_MASK      (3 << 0)
 450 #define SYS_CLCD_MODE_888       (0 << 0)
 451 #define SYS_CLCD_MODE_5551      (1 << 0)
 452 #define SYS_CLCD_MODE_565_RLSB  (2 << 0)
 453 #define SYS_CLCD_MODE_565_BLSB  (3 << 0)
 454 #define SYS_CLCD_NLCDIOON       (1 << 2)
 455 #define SYS_CLCD_VDDPOSSWITCH   (1 << 3)
 456 #define SYS_CLCD_PWR3V5SWITCH   (1 << 4)
 457 #define SYS_CLCD_ID_MASK        (0x1f << 8)
 458 #define SYS_CLCD_ID_SANYO_3_8   (0x00 << 8)
 459 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
 460 #define SYS_CLCD_ID_EPSON_2_2   (0x02 << 8)
 461 #define SYS_CLCD_ID_SANYO_2_5   (0x07 << 8)
 462 #define SYS_CLCD_ID_VGA         (0x1f << 8)
 463
 464 static struct clcd_panel vga = {
 465         .mode           = {
 466                 .name           = "VGA",
 467                 .refresh        = 60,
 468                 .xres           = 640,
 469                 .yres           = 480,
 470                 .pixclock       = 39721,
 471                 .left_margin    = 40,
 472                 .right_margin   = 24,
 473                 .upper_margin   = 32,
 474                 .lower_margin   = 11,
 475                 .hsync_len      = 96,
 476                 .vsync_len      = 2,
 477                 .sync           = 0,
 478                 .vmode          = FB_VMODE_NONINTERLACED,
 479         },
 480         .width          = -1,
 481         .height         = -1,
 482         .tim2           = TIM2_BCD | TIM2_IPC,
 483         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 484         .bpp            = 16,
 485 };
 486
 487 static struct clcd_panel sanyo_3_8_in = {
 488         .mode           = {
 489                 .name           = "Sanyo QVGA",
 490                 .refresh        = 116,
 491                 .xres           = 320,
 492                 .yres           = 240,
 493                 .pixclock       = 100000,
 494                 .left_margin    = 6,
 495                 .right_margin   = 6,
 496                 .upper_margin   = 5,
 497                 .lower_margin   = 5,
 498                 .hsync_len      = 6,
 499                 .vsync_len      = 6,
 500                 .sync           = 0,
 501                 .vmode          = FB_VMODE_NONINTERLACED,
 502         },
 503         .width          = -1,
 504         .height         = -1,
 505         .tim2           = TIM2_BCD,
 506         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 507         .bpp            = 16,
 508 };
 509
 510 static struct clcd_panel sanyo_2_5_in = {
 511         .mode           = {
 512                 .name           = "Sanyo QVGA Portrait",
 513                 .refresh        = 116,
 514                 .xres           = 240,
 515                 .yres           = 320,
 516                 .pixclock       = 100000,
 517                 .left_margin    = 20,
 518                 .right_margin   = 10,
 519                 .upper_margin   = 2,
 520                 .lower_margin   = 2,
 521                 .hsync_len      = 10,
 522                 .vsync_len      = 2,
 523                 .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
 524                 .vmode          = FB_VMODE_NONINTERLACED,
 525         },
 526         .width          = -1,
 527         .height         = -1,
 528         .tim2           = TIM2_IVS | TIM2_IHS | TIM2_IPC,
 529         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 530         .bpp            = 16,
 531 };
 532
 533 static struct clcd_panel epson_2_2_in = {
 534         .mode           = {
 535                 .name           = "Epson QCIF",
 536                 .refresh        = 390,
 537                 .xres           = 176,
 538                 .yres           = 220,
 539                 .pixclock       = 62500,
 540                 .left_margin    = 3,
 541                 .right_margin   = 2,
 542                 .upper_margin   = 1,
 543                 .lower_margin   = 0,
 544                 .hsync_len      = 3,
 545                 .vsync_len      = 2,
 546                 .sync           = 0,
 547                 .vmode          = FB_VMODE_NONINTERLACED,
 548         },
 549         .width          = -1,
 550         .height         = -1,
 551         .tim2           = TIM2_BCD | TIM2_IPC,
 552         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 553         .bpp            = 16,
 554 };
 555
 556 /*
 557  * Detect which LCD panel is connected, and return the appropriate
 558  * clcd_panel structure.  Note: we do not have any information on
 559  * the required timings for the 8.4in panel, so we presently assume
 560  * VGA timings.
 561  */
 562 static struct clcd_panel *versatile_clcd_panel(void)
 563 {
 564         void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
 565         struct clcd_panel *panel = &vga;
 566         u32 val;
 567
 568         val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
 569         if (val == SYS_CLCD_ID_SANYO_3_8)
 570                 panel = &sanyo_3_8_in;
 571         else if (val == SYS_CLCD_ID_SANYO_2_5)
 572                 panel = &sanyo_2_5_in;
 573         else if (val == SYS_CLCD_ID_EPSON_2_2)
 574                 panel = &epson_2_2_in;
 575         else if (val == SYS_CLCD_ID_VGA)
 576                 panel = &vga;
 577         else {
 578                 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
 579                         val);
 580                 panel = &vga;
 581         }
 582
 583         return panel;
 584 }
 585
 586 /*
 587  * Disable all display connectors on the interface module.
 588  */
 589 static void versatile_clcd_disable(struct clcd_fb *fb)
 590 {
 591         void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
 592         u32 val;
 593
 594         val = readl(sys_clcd);
 595         val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 596         writel(val, sys_clcd);
 597
 598 #ifdef CONFIG_MACH_VERSATILE_AB
 599         /*
 600          * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
 601          */
 602         if (machine_is_versatile_ab() && fb->panel == &sanyo_2_5_in) {
 603                 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
 604                 unsigned long ctrl;
 605
 606                 ctrl = readl(versatile_ib2_ctrl);
 607                 ctrl &= ~0x01;
 608                 writel(ctrl, versatile_ib2_ctrl);
 609         }
 610 #endif
 611 }
 612
 613 /*
 614  * Enable the relevant connector on the interface module.
 615  */
 616 static void versatile_clcd_enable(struct clcd_fb *fb)
 617 {
 618         void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
 619         u32 val;
 620
 621         val = readl(sys_clcd);
 622         val &= ~SYS_CLCD_MODE_MASK;
 623
 624         switch (fb->fb.var.green.length) {
 625         case 5:
 626                 val |= SYS_CLCD_MODE_5551;
 627                 break;
 628         case 6:
 629                 val |= SYS_CLCD_MODE_565_RLSB;
 630                 break;
 631         case 8:
 632                 val |= SYS_CLCD_MODE_888;
 633                 break;
 634         }
 635
 636         /*
 637          * Set the MUX
 638          */
 639         writel(val, sys_clcd);
 640
 641         /*
 642          * And now enable the PSUs
 643          */
 644         val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 645         writel(val, sys_clcd);
 646
 647 #ifdef CONFIG_MACH_VERSATILE_AB
 648         /*
 649          * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
 650          */
 651         if (machine_is_versatile_ab() && fb->panel == &sanyo_2_5_in) {
 652                 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
 653                 unsigned long ctrl;
 654
 655                 ctrl = readl(versatile_ib2_ctrl);
 656                 ctrl |= 0x01;
 657                 writel(ctrl, versatile_ib2_ctrl);
 658         }
 659 #endif
 660 }
 661
 662 static unsigned long framesize = SZ_1M;
 663
 664 static int versatile_clcd_setup(struct clcd_fb *fb)
 665 {
 666         dma_addr_t dma;
 667
 668         fb->panel               = versatile_clcd_panel();
 669
 670         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
 671                                                     &dma, GFP_KERNEL);
 672         if (!fb->fb.screen_base) {
 673                 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
 674                 return -ENOMEM;
 675         }
 676
 677         fb->fb.fix.smem_start   = dma;
 678         fb->fb.fix.smem_len     = framesize;
 679
 680         return 0;
 681 }
 682
 683 static int versatile_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
 684 {
 685         return dma_mmap_writecombine(&fb->dev->dev, vma,
 686                                      fb->fb.screen_base,
 687                                      fb->fb.fix.smem_start,
 688                                      fb->fb.fix.smem_len);
 689 }
 690
 691 static void versatile_clcd_remove(struct clcd_fb *fb)
 692 {
 693         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
 694                               fb->fb.screen_base, fb->fb.fix.smem_start);
 695 }
 696
 697 static struct clcd_board clcd_plat_data = {
 698         .name           = "Versatile",
 699         .check          = clcdfb_check,
 700         .decode         = clcdfb_decode,
 701         .disable        = versatile_clcd_disable,
 702         .enable         = versatile_clcd_enable,
 703         .setup          = versatile_clcd_setup,
 704         .mmap           = versatile_clcd_mmap,
 705         .remove         = versatile_clcd_remove,
 706 };
 707
 708 #define AACI_IRQ        { IRQ_AACI, NO_IRQ }
 709 #define AACI_DMA        { 0x80, 0x81 }
 710 #define MMCI0_IRQ       { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
 711 #define MMCI0_DMA       { 0x84, 0 }
 712 #define KMI0_IRQ        { IRQ_SIC_KMI0, NO_IRQ }
 713 #define KMI0_DMA        { 0, 0 }
 714 #define KMI1_IRQ        { IRQ_SIC_KMI1, NO_IRQ }
 715 #define KMI1_DMA        { 0, 0 }
 716
 717 /*
 718  * These devices are connected directly to the multi-layer AHB switch
 719  */
 720 #define SMC_IRQ         { NO_IRQ, NO_IRQ }
 721 #define SMC_DMA         { 0, 0 }
 722 #define MPMC_IRQ        { NO_IRQ, NO_IRQ }
 723 #define MPMC_DMA        { 0, 0 }
 724 #define CLCD_IRQ        { IRQ_CLCDINT, NO_IRQ }
 725 #define CLCD_DMA        { 0, 0 }
 726 #define DMAC_IRQ        { IRQ_DMAINT, NO_IRQ }
 727 #define DMAC_DMA        { 0, 0 }
 728
 729 /*
 730  * These devices are connected via the core APB bridge
 731  */
 732 #define SCTL_IRQ        { NO_IRQ, NO_IRQ }
 733 #define SCTL_DMA        { 0, 0 }
 734 #define WATCHDOG_IRQ    { IRQ_WDOGINT, NO_IRQ }
 735 #define WATCHDOG_DMA    { 0, 0 }
 736 #define GPIO0_IRQ       { IRQ_GPIOINT0, NO_IRQ }
 737 #define GPIO0_DMA       { 0, 0 }
 738 #define GPIO1_IRQ       { IRQ_GPIOINT1, NO_IRQ }
 739 #define GPIO1_DMA       { 0, 0 }
 740 #define RTC_IRQ         { IRQ_RTCINT, NO_IRQ }
 741 #define RTC_DMA         { 0, 0 }
 742
 743 /*
 744  * These devices are connected via the DMA APB bridge
 745  */
 746 #define SCI_IRQ         { IRQ_SCIINT, NO_IRQ }
 747 #define SCI_DMA         { 7, 6 }
 748 #define UART0_IRQ       { IRQ_UARTINT0, NO_IRQ }
 749 #define UART0_DMA       { 15, 14 }
 750 #define UART1_IRQ       { IRQ_UARTINT1, NO_IRQ }
 751 #define UART1_DMA       { 13, 12 }
 752 #define UART2_IRQ       { IRQ_UARTINT2, NO_IRQ }
 753 #define UART2_DMA       { 11, 10 }
 754 #define SSP_IRQ         { IRQ_SSPINT, NO_IRQ }
 755 #define SSP_DMA         { 9, 8 }
 756
 757 /* FPGA Primecells */
 758 AMBA_DEVICE(aaci,  "fpga:04", AACI,     NULL);
 759 AMBA_DEVICE(mmc0,  "fpga:05", MMCI0,    &mmc0_plat_data);
 760 AMBA_DEVICE(kmi0,  "fpga:06", KMI0,     NULL);
 761 AMBA_DEVICE(kmi1,  "fpga:07", KMI1,     NULL);
 762
 763 /* DevChip Primecells */
 764 AMBA_DEVICE(smc,   "dev:00",  SMC,      NULL);
 765 AMBA_DEVICE(mpmc,  "dev:10",  MPMC,     NULL);
 766 AMBA_DEVICE(clcd,  "dev:20",  CLCD,     &clcd_plat_data);
 767 AMBA_DEVICE(dmac,  "dev:30",  DMAC,     NULL);
 768 AMBA_DEVICE(sctl,  "dev:e0",  SCTL,     NULL);
 769 AMBA_DEVICE(wdog,  "dev:e1",  WATCHDOG, NULL);
 770 AMBA_DEVICE(gpio0, "dev:e4",  GPIO0,    NULL);
 771 AMBA_DEVICE(gpio1, "dev:e5",  GPIO1,    NULL);
 772 AMBA_DEVICE(rtc,   "dev:e8",  RTC,      NULL);
 773 AMBA_DEVICE(sci0,  "dev:f0",  SCI,      NULL);
 774 AMBA_DEVICE(uart0, "dev:f1",  UART0,    NULL);
 775 AMBA_DEVICE(uart1, "dev:f2",  UART1,    NULL);
 776 AMBA_DEVICE(uart2, "dev:f3",  UART2,    NULL);
 777 AMBA_DEVICE(ssp0,  "dev:f4",  SSP,      NULL);
 778
 779 static struct amba_device *amba_devs[] __initdata = {
 780         &dmac_device,
 781         &uart0_device,
 782         &uart1_device,
 783         &uart2_device,
 784         &smc_device,
 785         &mpmc_device,
 786         &clcd_device,
 787         &sctl_device,
 788         &wdog_device,
 789         &gpio0_device,
 790         &gpio1_device,
 791         &rtc_device,
 792         &sci0_device,
 793         &ssp0_device,
 794         &aaci_device,
 795         &mmc0_device,
 796         &kmi0_device,
 797         &kmi1_device,
 798 };
 799
 800 #ifdef CONFIG_LEDS
 801 #define VA_LEDS_BASE (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
 802
 803 static void versatile_leds_event(led_event_t ledevt)
 804 {
 805         unsigned long flags;
 806         u32 val;
 807
 808         local_irq_save(flags);
 809         val = readl(VA_LEDS_BASE);
 810
 811         switch (ledevt) {
 812         case led_idle_start:
 813                 val = val & ~VERSATILE_SYS_LED0;
 814                 break;
 815
 816         case led_idle_end:
 817                 val = val | VERSATILE_SYS_LED0;
 818                 break;
 819
 820         case led_timer:
 821                 val = val ^ VERSATILE_SYS_LED1;
 822                 break;
 823
 824         case led_halted:
 825                 val = 0;
 826                 break;
 827
 828         default:
 829                 break;
 830         }
 831
 832         writel(val, VA_LEDS_BASE);
 833         local_irq_restore(flags);
 834 }
 835 #endif  /* CONFIG_LEDS */
 836
 837 void __init versatile_init(void)
 838 {
 839         int i;
 840
 841         for (i = 0; i < ARRAY_SIZE(lookups); i++)
 842                 clkdev_add(&lookups[i]);
 843
 844         platform_device_register(&versatile_flash_device);
 845         platform_device_register(&versatile_i2c_device);
 846         platform_device_register(&smc91x_device);
 847
 848         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
 849                 struct amba_device *d = amba_devs[i];
 850                 amba_device_register(d, &iomem_resource);
 851         }
 852
 853 #ifdef CONFIG_LEDS
 854         leds_event = versatile_leds_event;
 855 #endif
 856 }
 857
 858 /*
 859  * Where is the timer (VA)?
 860  */
 861 #define TIMER0_VA_BASE           __io_address(VERSATILE_TIMER0_1_BASE)
 862 #define TIMER1_VA_BASE          (__io_address(VERSATILE_TIMER0_1_BASE) + 0x20)
 863 #define TIMER2_VA_BASE           __io_address(VERSATILE_TIMER2_3_BASE)
 864 #define TIMER3_VA_BASE          (__io_address(VERSATILE_TIMER2_3_BASE) + 0x20)
 865 #define VA_IC_BASE               __io_address(VERSATILE_VIC_BASE)
 866
 867 /*
 868  * How long is the timer interval?
 869  */
 870 #define TIMER_INTERVAL  (TICKS_PER_uSEC * mSEC_10)
 871 #if TIMER_INTERVAL >= 0x100000
 872 #define TIMER_RELOAD    (TIMER_INTERVAL >> 8)
 873 #define TIMER_DIVISOR   (TIMER_CTRL_DIV256)
 874 #define TICKS2USECS(x)  (256 * (x) / TICKS_PER_uSEC)
 875 #elif TIMER_INTERVAL >= 0x10000
 876 #define TIMER_RELOAD    (TIMER_INTERVAL >> 4)           /* Divide by 16 */
 877 #define TIMER_DIVISOR   (TIMER_CTRL_DIV16)
 878 #define TICKS2USECS(x)  (16 * (x) / TICKS_PER_uSEC)
 879 #else
 880 #define TIMER_RELOAD    (TIMER_INTERVAL)
 881 #define TIMER_DIVISOR   (TIMER_CTRL_DIV1)
 882 #define TICKS2USECS(x)  ((x) / TICKS_PER_uSEC)
 883 #endif
 884
 885 static void timer_set_mode(enum clock_event_mode mode,
 886                            struct clock_event_device *clk)
 887 {
 888         unsigned long ctrl;
 889
 890         switch(mode) {
 891         case CLOCK_EVT_MODE_PERIODIC:
 892                 writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);
 893
 894                 ctrl = TIMER_CTRL_PERIODIC;
 895                 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE | TIMER_CTRL_ENABLE;
 896                 break;
 897         case CLOCK_EVT_MODE_ONESHOT:
 898                 /* period set, and timer enabled in 'next_event' hook */
 899                 ctrl = TIMER_CTRL_ONESHOT;
 900                 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE;
 901                 break;
 902         case CLOCK_EVT_MODE_UNUSED:
 903         case CLOCK_EVT_MODE_SHUTDOWN:
 904         default:
 905                 ctrl = 0;
 906         }
 907
 908         writel(ctrl, TIMER0_VA_BASE + TIMER_CTRL);
 909 }
 910
 911 static int timer_set_next_event(unsigned long evt,
 912                                 struct clock_event_device *unused)
 913 {
 914         unsigned long ctrl = readl(TIMER0_VA_BASE + TIMER_CTRL);
 915
 916         writel(evt, TIMER0_VA_BASE + TIMER_LOAD);
 917         writel(ctrl | TIMER_CTRL_ENABLE, TIMER0_VA_BASE + TIMER_CTRL);
 918
 919         return 0;
 920 }
 921
 922 static struct clock_event_device timer0_clockevent =     {
 923         .name           = "timer0",
 924         .shift          = 32,
 925         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 926         .set_mode       = timer_set_mode,
 927         .set_next_event = timer_set_next_event,
 928 };
 929
 930 /*
 931  * IRQ handler for the timer
 932  */
 933 static irqreturn_t versatile_timer_interrupt(int irq, void *dev_id)
 934 {
 935         struct clock_event_device *evt = &timer0_clockevent;
 936
 937         writel(1, TIMER0_VA_BASE + TIMER_INTCLR);
 938
 939         evt->event_handler(evt);
 940
 941         return IRQ_HANDLED;
 942 }
 943
 944 static struct irqaction versatile_timer_irq = {
 945         .name           = "Versatile Timer Tick",
 946         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 947         .handler        = versatile_timer_interrupt,
 948 };
 949
 950 static cycle_t versatile_get_cycles(struct clocksource *cs)
 951 {
 952         return ~readl(TIMER3_VA_BASE + TIMER_VALUE);
 953 }
 954
 955 static struct clocksource clocksource_versatile = {
 956         .name           = "timer3",
 957         .rating         = 200,
 958         .read           = versatile_get_cycles,
 959         .mask           = CLOCKSOURCE_MASK(32),
 960         .shift          = 20,
 961         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 962 };
 963
 964 static int __init versatile_clocksource_init(void)
 965 {
 966         /* setup timer3 as free-running clocksource */
 967         writel(0, TIMER3_VA_BASE + TIMER_CTRL);
 968         writel(0xffffffff, TIMER3_VA_BASE + TIMER_LOAD);
 969         writel(0xffffffff, TIMER3_VA_BASE + TIMER_VALUE);
 970         writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
 971                TIMER3_VA_BASE + TIMER_CTRL);
 972
 973         clocksource_versatile.mult =
 974                 clocksource_khz2mult(1000, clocksource_versatile.shift);
 975         clocksource_register(&clocksource_versatile);
 976
 977         return 0;
 978 }
 979
 980 /*
 981  * Set up timer interrupt, and return the current time in seconds.
 982  */
 983 static void __init versatile_timer_init(void)
 984 {
 985         u32 val;
 986
 987         /*
 988          * set clock frequency:
 989          *      VERSATILE_REFCLK is 32KHz
 990          *      VERSATILE_TIMCLK is 1MHz
 991          */
 992         val = readl(__io_address(VERSATILE_SCTL_BASE));
 993         writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
 994                (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
 995                (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
 996                (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
 997                __io_address(VERSATILE_SCTL_BASE));
 998
 999         /*
1000          * Initialise to a known state (all timers off)
1001          */
1002         writel(0, TIMER0_VA_BASE + TIMER_CTRL);
1003         writel(0, TIMER1_VA_BASE + TIMER_CTRL);
1004         writel(0, TIMER2_VA_BASE + TIMER_CTRL);
1005         writel(0, TIMER3_VA_BASE + TIMER_CTRL);
1006
1007         /*
1008          * Make irqs happen for the system timer
1009          */
1010         setup_irq(IRQ_TIMERINT0_1, &versatile_timer_irq);
1011
1012         versatile_clocksource_init();
1013
1014         timer0_clockevent.mult =
1015                 div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift);
1016         timer0_clockevent.max_delta_ns =
1017                 clockevent_delta2ns(0xffffffff, &timer0_clockevent);
1018         timer0_clockevent.min_delta_ns =
1019                 clockevent_delta2ns(0xf, &timer0_clockevent);
1020
1021         timer0_clockevent.cpumask = cpumask_of(0);
1022         clockevents_register_device(&timer0_clockevent);
1023 }
1024
1025 struct sys_timer versatile_timer = {
1026         .init           = versatile_timer_init,
1027 };
1028