arch/arm/mach-versatile/core.c

   1 /*
   2  *  linux/arch/arm/mach-versatile/core.c
   3  *
   4  *  Copyright (C) 1999 - 2003 ARM Limited
   5  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21 #include <linux/init.h>
  22 #include <linux/device.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/sysdev.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/amba/bus.h>
  28 #include <linux/amba/clcd.h>
  29 #include <linux/amba/pl061.h>
  30 #include <linux/amba/mmci.h>
  31 #include <linux/amba/pl022.h>
  32 #include <linux/io.h>
  33 #include <linux/gfp.h>
  34 #include <linux/clkdev.h>
  35
  36 #include <asm/system.h>
  37 #include <asm/irq.h>
  38 #include <asm/leds.h>
  39 #include <asm/hardware/arm_timer.h>
  40 #include <asm/hardware/icst.h>
  41 #include <asm/hardware/vic.h>
  42 #include <asm/mach-types.h>
  43
  44 #include <asm/mach/arch.h>
  45 #include <asm/mach/flash.h>
  46 #include <asm/mach/irq.h>
  47 #include <asm/mach/time.h>
  48 #include <asm/mach/map.h>
  49 #include <mach/hardware.h>
  50 #include <mach/platform.h>
  51 #include <asm/hardware/timer-sp.h>
  52
  53 #include <plat/sched_clock.h>
  54
  55 #include "core.h"
  56
  57 /*
  58  * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
  59  * is the (PA >> 12).
  60  *
  61  * Setup a VA for the Versatile Vectored Interrupt Controller.
  62  */
  63 #define VA_VIC_BASE             __io_address(VERSATILE_VIC_BASE)
  64 #define VA_SIC_BASE             __io_address(VERSATILE_SIC_BASE)
  65
  66 static void sic_mask_irq(struct irq_data *d)
  67 {
  68         unsigned int irq = d->irq - IRQ_SIC_START;
  69
  70         writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
  71 }
  72
  73 static void sic_unmask_irq(struct irq_data *d)
  74 {
  75         unsigned int irq = d->irq - IRQ_SIC_START;
  76
  77         writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_SET);
  78 }
  79
  80 static struct irq_chip sic_chip = {
  81         .name           = "SIC",
  82         .irq_ack        = sic_mask_irq,
  83         .irq_mask       = sic_mask_irq,
  84         .irq_unmask     = sic_unmask_irq,
  85 };
  86
  87 static void
  88 sic_handle_irq(unsigned int irq, struct irq_desc *desc)
  89 {
  90         unsigned long status = readl(VA_SIC_BASE + SIC_IRQ_STATUS);
  91
  92         if (status == 0) {
  93                 do_bad_IRQ(irq, desc);
  94                 return;
  95         }
  96
  97         do {
  98                 irq = ffs(status) - 1;
  99                 status &= ~(1 << irq);
 100
 101                 irq += IRQ_SIC_START;
 102
 103                 generic_handle_irq(irq);
 104         } while (status);
 105 }
 106
 107 #if 1
 108 #define IRQ_MMCI0A      IRQ_VICSOURCE22
 109 #define IRQ_AACI        IRQ_VICSOURCE24
 110 #define IRQ_ETH         IRQ_VICSOURCE25
 111 #define PIC_MASK        0xFFD00000
 112 #else
 113 #define IRQ_MMCI0A      IRQ_SIC_MMCI0A
 114 #define IRQ_AACI        IRQ_SIC_AACI
 115 #define IRQ_ETH         IRQ_SIC_ETH
 116 #define PIC_MASK        0
 117 #endif
 118
 119 void __init versatile_init_irq(void)
 120 {
 121         unsigned int i;
 122
 123         vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0, 0);
 124
 125         set_irq_chained_handler(IRQ_VICSOURCE31, sic_handle_irq);
 126
 127         /* Do second interrupt controller */
 128         writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
 129
 130         for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
 131                 if ((PIC_MASK & (1 << (i - IRQ_SIC_START))) == 0) {
 132                         set_irq_chip(i, &sic_chip);
 133                         set_irq_handler(i, handle_level_irq);
 134                         set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 135                 }
 136         }
 137
 138         /*
 139          * Interrupts on secondary controller from 0 to 8 are routed to
 140          * source 31 on PIC.
 141          * Interrupts from 21 to 31 are routed directly to the VIC on
 142          * the corresponding number on primary controller. This is controlled
 143          * by setting PIC_ENABLEx.
 144          */
 145         writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE);
 146 }
 147
 148 static struct map_desc versatile_io_desc[] __initdata = {
 149         {
 150                 .virtual        =  IO_ADDRESS(VERSATILE_SYS_BASE),
 151                 .pfn            = __phys_to_pfn(VERSATILE_SYS_BASE),
 152                 .length         = SZ_4K,
 153                 .type           = MT_DEVICE
 154         }, {
 155                 .virtual        =  IO_ADDRESS(VERSATILE_SIC_BASE),
 156                 .pfn            = __phys_to_pfn(VERSATILE_SIC_BASE),
 157                 .length         = SZ_4K,
 158                 .type           = MT_DEVICE
 159         }, {
 160                 .virtual        =  IO_ADDRESS(VERSATILE_VIC_BASE),
 161                 .pfn            = __phys_to_pfn(VERSATILE_VIC_BASE),
 162                 .length         = SZ_4K,
 163                 .type           = MT_DEVICE
 164         }, {
 165                 .virtual        =  IO_ADDRESS(VERSATILE_SCTL_BASE),
 166                 .pfn            = __phys_to_pfn(VERSATILE_SCTL_BASE),
 167                 .length         = SZ_4K * 9,
 168                 .type           = MT_DEVICE
 169         },
 170 #ifdef CONFIG_MACH_VERSATILE_AB
 171         {
 172                 .virtual        =  IO_ADDRESS(VERSATILE_GPIO0_BASE),
 173                 .pfn            = __phys_to_pfn(VERSATILE_GPIO0_BASE),
 174                 .length         = SZ_4K,
 175                 .type           = MT_DEVICE
 176         }, {
 177                 .virtual        =  IO_ADDRESS(VERSATILE_IB2_BASE),
 178                 .pfn            = __phys_to_pfn(VERSATILE_IB2_BASE),
 179                 .length         = SZ_64M,
 180                 .type           = MT_DEVICE
 181         },
 182 #endif
 183 #ifdef CONFIG_DEBUG_LL
 184         {
 185                 .virtual        =  IO_ADDRESS(VERSATILE_UART0_BASE),
 186                 .pfn            = __phys_to_pfn(VERSATILE_UART0_BASE),
 187                 .length         = SZ_4K,
 188                 .type           = MT_DEVICE
 189         },
 190 #endif
 191 #ifdef CONFIG_PCI
 192         {
 193                 .virtual        =  IO_ADDRESS(VERSATILE_PCI_CORE_BASE),
 194                 .pfn            = __phys_to_pfn(VERSATILE_PCI_CORE_BASE),
 195                 .length         = SZ_4K,
 196                 .type           = MT_DEVICE
 197         }, {
 198                 .virtual        =  (unsigned long)VERSATILE_PCI_VIRT_BASE,
 199                 .pfn            = __phys_to_pfn(VERSATILE_PCI_BASE),
 200                 .length         = VERSATILE_PCI_BASE_SIZE,
 201                 .type           = MT_DEVICE
 202         }, {
 203                 .virtual        =  (unsigned long)VERSATILE_PCI_CFG_VIRT_BASE,
 204                 .pfn            = __phys_to_pfn(VERSATILE_PCI_CFG_BASE),
 205                 .length         = VERSATILE_PCI_CFG_BASE_SIZE,
 206                 .type           = MT_DEVICE
 207         },
 208 #if 0
 209         {
 210                 .virtual        =  VERSATILE_PCI_VIRT_MEM_BASE0,
 211                 .pfn            = __phys_to_pfn(VERSATILE_PCI_MEM_BASE0),
 212                 .length         = SZ_16M,
 213                 .type           = MT_DEVICE
 214         }, {
 215                 .virtual        =  VERSATILE_PCI_VIRT_MEM_BASE1,
 216                 .pfn            = __phys_to_pfn(VERSATILE_PCI_MEM_BASE1),
 217                 .length         = SZ_16M,
 218                 .type           = MT_DEVICE
 219         }, {
 220                 .virtual        =  VERSATILE_PCI_VIRT_MEM_BASE2,
 221                 .pfn            = __phys_to_pfn(VERSATILE_PCI_MEM_BASE2),
 222                 .length         = SZ_16M,
 223                 .type           = MT_DEVICE
 224         },
 225 #endif
 226 #endif
 227 };
 228
 229 void __init versatile_map_io(void)
 230 {
 231         iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc));
 232 }
 233
 234
 235 #define VERSATILE_FLASHCTRL    (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
 236
 237 static int versatile_flash_init(void)
 238 {
 239         u32 val;
 240
 241         val = __raw_readl(VERSATILE_FLASHCTRL);
 242         val &= ~VERSATILE_FLASHPROG_FLVPPEN;
 243         __raw_writel(val, VERSATILE_FLASHCTRL);
 244
 245         return 0;
 246 }
 247
 248 static void versatile_flash_exit(void)
 249 {
 250         u32 val;
 251
 252         val = __raw_readl(VERSATILE_FLASHCTRL);
 253         val &= ~VERSATILE_FLASHPROG_FLVPPEN;
 254         __raw_writel(val, VERSATILE_FLASHCTRL);
 255 }
 256
 257 static void versatile_flash_set_vpp(int on)
 258 {
 259         u32 val;
 260
 261         val = __raw_readl(VERSATILE_FLASHCTRL);
 262         if (on)
 263                 val |= VERSATILE_FLASHPROG_FLVPPEN;
 264         else
 265                 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
 266         __raw_writel(val, VERSATILE_FLASHCTRL);
 267 }
 268
 269 static struct flash_platform_data versatile_flash_data = {
 270         .map_name               = "cfi_probe",
 271         .width                  = 4,
 272         .init                   = versatile_flash_init,
 273         .exit                   = versatile_flash_exit,
 274         .set_vpp                = versatile_flash_set_vpp,
 275 };
 276
 277 static struct resource versatile_flash_resource = {
 278         .start                  = VERSATILE_FLASH_BASE,
 279         .end                    = VERSATILE_FLASH_BASE + VERSATILE_FLASH_SIZE - 1,
 280         .flags                  = IORESOURCE_MEM,
 281 };
 282
 283 static struct platform_device versatile_flash_device = {
 284         .name                   = "armflash",
 285         .id                     = 0,
 286         .dev                    = {
 287                 .platform_data  = &versatile_flash_data,
 288         },
 289         .num_resources          = 1,
 290         .resource               = &versatile_flash_resource,
 291 };
 292
 293 static struct resource smc91x_resources[] = {
 294         [0] = {
 295                 .start          = VERSATILE_ETH_BASE,
 296                 .end            = VERSATILE_ETH_BASE + SZ_64K - 1,
 297                 .flags          = IORESOURCE_MEM,
 298         },
 299         [1] = {
 300                 .start          = IRQ_ETH,
 301                 .end            = IRQ_ETH,
 302                 .flags          = IORESOURCE_IRQ,
 303         },
 304 };
 305
 306 static struct platform_device smc91x_device = {
 307         .name           = "smc91x",
 308         .id             = 0,
 309         .num_resources  = ARRAY_SIZE(smc91x_resources),
 310         .resource       = smc91x_resources,
 311 };
 312
 313 static struct resource versatile_i2c_resource = {
 314         .start                  = VERSATILE_I2C_BASE,
 315         .end                    = VERSATILE_I2C_BASE + SZ_4K - 1,
 316         .flags                  = IORESOURCE_MEM,
 317 };
 318
 319 static struct platform_device versatile_i2c_device = {
 320         .name                   = "versatile-i2c",
 321         .id                     = 0,
 322         .num_resources          = 1,
 323         .resource               = &versatile_i2c_resource,
 324 };
 325
 326 static struct i2c_board_info versatile_i2c_board_info[] = {
 327         {
 328                 I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
 329         },
 330 };
 331
 332 static int __init versatile_i2c_init(void)
 333 {
 334         return i2c_register_board_info(0, versatile_i2c_board_info,
 335                                        ARRAY_SIZE(versatile_i2c_board_info));
 336 }
 337 arch_initcall(versatile_i2c_init);
 338
 339 #define VERSATILE_SYSMCI        (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
 340
 341 unsigned int mmc_status(struct device *dev)
 342 {
 343         struct amba_device *adev = container_of(dev, struct amba_device, dev);
 344         u32 mask;
 345
 346         if (adev->res.start == VERSATILE_MMCI0_BASE)
 347                 mask = 1;
 348         else
 349                 mask = 2;
 350
 351         return readl(VERSATILE_SYSMCI) & mask;
 352 }
 353
 354 static struct mmci_platform_data mmc0_plat_data = {
 355         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 356         .status         = mmc_status,
 357         .gpio_wp        = -1,
 358         .gpio_cd        = -1,
 359 };
 360
 361 static struct resource char_lcd_resources[] = {
 362         {
 363                 .start = VERSATILE_CHAR_LCD_BASE,
 364                 .end   = (VERSATILE_CHAR_LCD_BASE + SZ_4K - 1),
 365                 .flags = IORESOURCE_MEM,
 366         },
 367 };
 368
 369 static struct platform_device char_lcd_device = {
 370         .name           =       "arm-charlcd",
 371         .id             =       -1,
 372         .num_resources  =       ARRAY_SIZE(char_lcd_resources),
 373         .resource       =       char_lcd_resources,
 374 };
 375
 376 /*
 377  * Clock handling
 378  */
 379 static const struct icst_params versatile_oscvco_params = {
 380         .ref            = 24000000,
 381         .vco_max        = ICST307_VCO_MAX,
 382         .vco_min        = ICST307_VCO_MIN,
 383         .vd_min         = 4 + 8,
 384         .vd_max         = 511 + 8,
 385         .rd_min         = 1 + 2,
 386         .rd_max         = 127 + 2,
 387         .s2div          = icst307_s2div,
 388         .idx2s          = icst307_idx2s,
 389 };
 390
 391 static void versatile_oscvco_set(struct clk *clk, struct icst_vco vco)
 392 {
 393         void __iomem *sys_lock = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LOCK_OFFSET;
 394         u32 val;
 395
 396         val = readl(clk->vcoreg) & ~0x7ffff;
 397         val |= vco.v | (vco.r << 9) | (vco.s << 16);
 398
 399         writel(0xa05f, sys_lock);
 400         writel(val, clk->vcoreg);
 401         writel(0, sys_lock);
 402 }
 403
 404 static const struct clk_ops osc4_clk_ops = {
 405         .round  = icst_clk_round,
 406         .set    = icst_clk_set,
 407         .setvco = versatile_oscvco_set,
 408 };
 409
 410 static struct clk osc4_clk = {
 411         .ops    = &osc4_clk_ops,
 412         .params = &versatile_oscvco_params,
 413 };
 414
 415 /*
 416  * These are fixed clocks.
 417  */
 418 static struct clk ref24_clk = {
 419         .rate   = 24000000,
 420 };
 421
 422 static struct clk dummy_apb_pclk;
 423
 424 static struct clk_lookup lookups[] = {
 425         {       /* AMBA bus clock */
 426                 .con_id         = "apb_pclk",
 427                 .clk            = &dummy_apb_pclk,
 428         }, {    /* UART0 */
 429                 .dev_id         = "dev:f1",
 430                 .clk            = &ref24_clk,
 431         }, {    /* UART1 */
 432                 .dev_id         = "dev:f2",
 433                 .clk            = &ref24_clk,
 434         }, {    /* UART2 */
 435                 .dev_id         = "dev:f3",
 436                 .clk            = &ref24_clk,
 437         }, {    /* UART3 */
 438                 .dev_id         = "fpga:09",
 439                 .clk            = &ref24_clk,
 440         }, {    /* KMI0 */
 441                 .dev_id         = "fpga:06",
 442                 .clk            = &ref24_clk,
 443         }, {    /* KMI1 */
 444                 .dev_id         = "fpga:07",
 445                 .clk            = &ref24_clk,
 446         }, {    /* MMC0 */
 447                 .dev_id         = "fpga:05",
 448                 .clk            = &ref24_clk,
 449         }, {    /* MMC1 */
 450                 .dev_id         = "fpga:0b",
 451                 .clk            = &ref24_clk,
 452         }, {    /* SSP */
 453                 .dev_id         = "dev:f4",
 454                 .clk            = &ref24_clk,
 455         }, {    /* CLCD */
 456                 .dev_id         = "dev:20",
 457                 .clk            = &osc4_clk,
 458         }
 459 };
 460
 461 /*
 462  * CLCD support.
 463  */
 464 #define SYS_CLCD_MODE_MASK      (3 << 0)
 465 #define SYS_CLCD_MODE_888       (0 << 0)
 466 #define SYS_CLCD_MODE_5551      (1 << 0)
 467 #define SYS_CLCD_MODE_565_RLSB  (2 << 0)
 468 #define SYS_CLCD_MODE_565_BLSB  (3 << 0)
 469 #define SYS_CLCD_NLCDIOON       (1 << 2)
 470 #define SYS_CLCD_VDDPOSSWITCH   (1 << 3)
 471 #define SYS_CLCD_PWR3V5SWITCH   (1 << 4)
 472 #define SYS_CLCD_ID_MASK        (0x1f << 8)
 473 #define SYS_CLCD_ID_SANYO_3_8   (0x00 << 8)
 474 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
 475 #define SYS_CLCD_ID_EPSON_2_2   (0x02 << 8)
 476 #define SYS_CLCD_ID_SANYO_2_5   (0x07 << 8)
 477 #define SYS_CLCD_ID_VGA         (0x1f << 8)
 478
 479 static struct clcd_panel vga = {
 480         .mode           = {
 481                 .name           = "VGA",
 482                 .refresh        = 60,
 483                 .xres           = 640,
 484                 .yres           = 480,
 485                 .pixclock       = 39721,
 486                 .left_margin    = 40,
 487                 .right_margin   = 24,
 488                 .upper_margin   = 32,
 489                 .lower_margin   = 11,
 490                 .hsync_len      = 96,
 491                 .vsync_len      = 2,
 492                 .sync           = 0,
 493                 .vmode          = FB_VMODE_NONINTERLACED,
 494         },
 495         .width          = -1,
 496         .height         = -1,
 497         .tim2           = TIM2_BCD | TIM2_IPC,
 498         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 499         .bpp            = 16,
 500 };
 501
 502 static struct clcd_panel sanyo_3_8_in = {
 503         .mode           = {
 504                 .name           = "Sanyo QVGA",
 505                 .refresh        = 116,
 506                 .xres           = 320,
 507                 .yres           = 240,
 508                 .pixclock       = 100000,
 509                 .left_margin    = 6,
 510                 .right_margin   = 6,
 511                 .upper_margin   = 5,
 512                 .lower_margin   = 5,
 513                 .hsync_len      = 6,
 514                 .vsync_len      = 6,
 515                 .sync           = 0,
 516                 .vmode          = FB_VMODE_NONINTERLACED,
 517         },
 518         .width          = -1,
 519         .height         = -1,
 520         .tim2           = TIM2_BCD,
 521         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 522         .bpp            = 16,
 523 };
 524
 525 static struct clcd_panel sanyo_2_5_in = {
 526         .mode           = {
 527                 .name           = "Sanyo QVGA Portrait",
 528                 .refresh        = 116,
 529                 .xres           = 240,
 530                 .yres           = 320,
 531                 .pixclock       = 100000,
 532                 .left_margin    = 20,
 533                 .right_margin   = 10,
 534                 .upper_margin   = 2,
 535                 .lower_margin   = 2,
 536                 .hsync_len      = 10,
 537                 .vsync_len      = 2,
 538                 .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
 539                 .vmode          = FB_VMODE_NONINTERLACED,
 540         },
 541         .width          = -1,
 542         .height         = -1,
 543         .tim2           = TIM2_IVS | TIM2_IHS | TIM2_IPC,
 544         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 545         .bpp            = 16,
 546 };
 547
 548 static struct clcd_panel epson_2_2_in = {
 549         .mode           = {
 550                 .name           = "Epson QCIF",
 551                 .refresh        = 390,
 552                 .xres           = 176,
 553                 .yres           = 220,
 554                 .pixclock       = 62500,
 555                 .left_margin    = 3,
 556                 .right_margin   = 2,
 557                 .upper_margin   = 1,
 558                 .lower_margin   = 0,
 559                 .hsync_len      = 3,
 560                 .vsync_len      = 2,
 561                 .sync           = 0,
 562                 .vmode          = FB_VMODE_NONINTERLACED,
 563         },
 564         .width          = -1,
 565         .height         = -1,
 566         .tim2           = TIM2_BCD | TIM2_IPC,
 567         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 568         .bpp            = 16,
 569 };
 570
 571 /*
 572  * Detect which LCD panel is connected, and return the appropriate
 573  * clcd_panel structure.  Note: we do not have any information on
 574  * the required timings for the 8.4in panel, so we presently assume
 575  * VGA timings.
 576  */
 577 static struct clcd_panel *versatile_clcd_panel(void)
 578 {
 579         void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
 580         struct clcd_panel *panel = &vga;
 581         u32 val;
 582
 583         val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
 584         if (val == SYS_CLCD_ID_SANYO_3_8)
 585                 panel = &sanyo_3_8_in;
 586         else if (val == SYS_CLCD_ID_SANYO_2_5)
 587                 panel = &sanyo_2_5_in;
 588         else if (val == SYS_CLCD_ID_EPSON_2_2)
 589                 panel = &epson_2_2_in;
 590         else if (val == SYS_CLCD_ID_VGA)
 591                 panel = &vga;
 592         else {
 593                 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
 594                         val);
 595                 panel = &vga;
 596         }
 597
 598         return panel;
 599 }
 600
 601 /*
 602  * Disable all display connectors on the interface module.
 603  */
 604 static void versatile_clcd_disable(struct clcd_fb *fb)
 605 {
 606         void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
 607         u32 val;
 608
 609         val = readl(sys_clcd);
 610         val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 611         writel(val, sys_clcd);
 612
 613 #ifdef CONFIG_MACH_VERSATILE_AB
 614         /*
 615          * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
 616          */
 617         if (machine_is_versatile_ab() && fb->panel == &sanyo_2_5_in) {
 618                 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
 619                 unsigned long ctrl;
 620
 621                 ctrl = readl(versatile_ib2_ctrl);
 622                 ctrl &= ~0x01;
 623                 writel(ctrl, versatile_ib2_ctrl);
 624         }
 625 #endif
 626 }
 627
 628 /*
 629  * Enable the relevant connector on the interface module.
 630  */
 631 static void versatile_clcd_enable(struct clcd_fb *fb)
 632 {
 633         void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
 634         u32 val;
 635
 636         val = readl(sys_clcd);
 637         val &= ~SYS_CLCD_MODE_MASK;
 638
 639         switch (fb->fb.var.green.length) {
 640         case 5:
 641                 val |= SYS_CLCD_MODE_5551;
 642                 break;
 643         case 6:
 644                 val |= SYS_CLCD_MODE_565_RLSB;
 645                 break;
 646         case 8:
 647                 val |= SYS_CLCD_MODE_888;
 648                 break;
 649         }
 650
 651         /*
 652          * Set the MUX
 653          */
 654         writel(val, sys_clcd);
 655
 656         /*
 657          * And now enable the PSUs
 658          */
 659         val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 660         writel(val, sys_clcd);
 661
 662 #ifdef CONFIG_MACH_VERSATILE_AB
 663         /*
 664          * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
 665          */
 666         if (machine_is_versatile_ab() && fb->panel == &sanyo_2_5_in) {
 667                 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
 668                 unsigned long ctrl;
 669
 670                 ctrl = readl(versatile_ib2_ctrl);
 671                 ctrl |= 0x01;
 672                 writel(ctrl, versatile_ib2_ctrl);
 673         }
 674 #endif
 675 }
 676
 677 static unsigned long framesize = SZ_1M;
 678
 679 static int versatile_clcd_setup(struct clcd_fb *fb)
 680 {
 681         dma_addr_t dma;
 682
 683         fb->panel               = versatile_clcd_panel();
 684
 685         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
 686                                                     &dma, GFP_KERNEL);
 687         if (!fb->fb.screen_base) {
 688                 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
 689                 return -ENOMEM;
 690         }
 691
 692         fb->fb.fix.smem_start   = dma;
 693         fb->fb.fix.smem_len     = framesize;
 694
 695         return 0;
 696 }
 697
 698 static int versatile_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
 699 {
 700         return dma_mmap_writecombine(&fb->dev->dev, vma,
 701                                      fb->fb.screen_base,
 702                                      fb->fb.fix.smem_start,
 703                                      fb->fb.fix.smem_len);
 704 }
 705
 706 static void versatile_clcd_remove(struct clcd_fb *fb)
 707 {
 708         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
 709                               fb->fb.screen_base, fb->fb.fix.smem_start);
 710 }
 711
 712 static struct clcd_board clcd_plat_data = {
 713         .name           = "Versatile",
 714         .check          = clcdfb_check,
 715         .decode         = clcdfb_decode,
 716         .disable        = versatile_clcd_disable,
 717         .enable         = versatile_clcd_enable,
 718         .setup          = versatile_clcd_setup,
 719         .mmap           = versatile_clcd_mmap,
 720         .remove         = versatile_clcd_remove,
 721 };
 722
 723 static struct pl061_platform_data gpio0_plat_data = {
 724         .gpio_base      = 0,
 725         .irq_base       = IRQ_GPIO0_START,
 726 };
 727
 728 static struct pl061_platform_data gpio1_plat_data = {
 729         .gpio_base      = 8,
 730         .irq_base       = IRQ_GPIO1_START,
 731 };
 732
 733 static struct pl022_ssp_controller ssp0_plat_data = {
 734         .bus_id = 0,
 735         .enable_dma = 0,
 736         .num_chipselect = 1,
 737 };
 738
 739 #define AACI_IRQ        { IRQ_AACI, NO_IRQ }
 740 #define AACI_DMA        { 0x80, 0x81 }
 741 #define MMCI0_IRQ       { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
 742 #define MMCI0_DMA       { 0x84, 0 }
 743 #define KMI0_IRQ        { IRQ_SIC_KMI0, NO_IRQ }
 744 #define KMI0_DMA        { 0, 0 }
 745 #define KMI1_IRQ        { IRQ_SIC_KMI1, NO_IRQ }
 746 #define KMI1_DMA        { 0, 0 }
 747
 748 /*
 749  * These devices are connected directly to the multi-layer AHB switch
 750  */
 751 #define SMC_IRQ         { NO_IRQ, NO_IRQ }
 752 #define SMC_DMA         { 0, 0 }
 753 #define MPMC_IRQ        { NO_IRQ, NO_IRQ }
 754 #define MPMC_DMA        { 0, 0 }
 755 #define CLCD_IRQ        { IRQ_CLCDINT, NO_IRQ }
 756 #define CLCD_DMA        { 0, 0 }
 757 #define DMAC_IRQ        { IRQ_DMAINT, NO_IRQ }
 758 #define DMAC_DMA        { 0, 0 }
 759
 760 /*
 761  * These devices are connected via the core APB bridge
 762  */
 763 #define SCTL_IRQ        { NO_IRQ, NO_IRQ }
 764 #define SCTL_DMA        { 0, 0 }
 765 #define WATCHDOG_IRQ    { IRQ_WDOGINT, NO_IRQ }
 766 #define WATCHDOG_DMA    { 0, 0 }
 767 #define GPIO0_IRQ       { IRQ_GPIOINT0, NO_IRQ }
 768 #define GPIO0_DMA       { 0, 0 }
 769 #define GPIO1_IRQ       { IRQ_GPIOINT1, NO_IRQ }
 770 #define GPIO1_DMA       { 0, 0 }
 771 #define RTC_IRQ         { IRQ_RTCINT, NO_IRQ }
 772 #define RTC_DMA         { 0, 0 }
 773
 774 /*
 775  * These devices are connected via the DMA APB bridge
 776  */
 777 #define SCI_IRQ         { IRQ_SCIINT, NO_IRQ }
 778 #define SCI_DMA         { 7, 6 }
 779 #define UART0_IRQ       { IRQ_UARTINT0, NO_IRQ }
 780 #define UART0_DMA       { 15, 14 }
 781 #define UART1_IRQ       { IRQ_UARTINT1, NO_IRQ }
 782 #define UART1_DMA       { 13, 12 }
 783 #define UART2_IRQ       { IRQ_UARTINT2, NO_IRQ }
 784 #define UART2_DMA       { 11, 10 }
 785 #define SSP_IRQ         { IRQ_SSPINT, NO_IRQ }
 786 #define SSP_DMA         { 9, 8 }
 787
 788 /* FPGA Primecells */
 789 AMBA_DEVICE(aaci,  "fpga:04", AACI,     NULL);
 790 AMBA_DEVICE(mmc0,  "fpga:05", MMCI0,    &mmc0_plat_data);
 791 AMBA_DEVICE(kmi0,  "fpga:06", KMI0,     NULL);
 792 AMBA_DEVICE(kmi1,  "fpga:07", KMI1,     NULL);
 793
 794 /* DevChip Primecells */
 795 AMBA_DEVICE(smc,   "dev:00",  SMC,      NULL);
 796 AMBA_DEVICE(mpmc,  "dev:10",  MPMC,     NULL);
 797 AMBA_DEVICE(clcd,  "dev:20",  CLCD,     &clcd_plat_data);
 798 AMBA_DEVICE(dmac,  "dev:30",  DMAC,     NULL);
 799 AMBA_DEVICE(sctl,  "dev:e0",  SCTL,     NULL);
 800 AMBA_DEVICE(wdog,  "dev:e1",  WATCHDOG, NULL);
 801 AMBA_DEVICE(gpio0, "dev:e4",  GPIO0,    &gpio0_plat_data);
 802 AMBA_DEVICE(gpio1, "dev:e5",  GPIO1,    &gpio1_plat_data);
 803 AMBA_DEVICE(rtc,   "dev:e8",  RTC,      NULL);
 804 AMBA_DEVICE(sci0,  "dev:f0",  SCI,      NULL);
 805 AMBA_DEVICE(uart0, "dev:f1",  UART0,    NULL);
 806 AMBA_DEVICE(uart1, "dev:f2",  UART1,    NULL);
 807 AMBA_DEVICE(uart2, "dev:f3",  UART2,    NULL);
 808 AMBA_DEVICE(ssp0,  "dev:f4",  SSP,      &ssp0_plat_data);
 809
 810 static struct amba_device *amba_devs[] __initdata = {
 811         &dmac_device,
 812         &uart0_device,
 813         &uart1_device,
 814         &uart2_device,
 815         &smc_device,
 816         &mpmc_device,
 817         &clcd_device,
 818         &sctl_device,
 819         &wdog_device,
 820         &gpio0_device,
 821         &gpio1_device,
 822         &rtc_device,
 823         &sci0_device,
 824         &ssp0_device,
 825         &aaci_device,
 826         &mmc0_device,
 827         &kmi0_device,
 828         &kmi1_device,
 829 };
 830
 831 #ifdef CONFIG_LEDS
 832 #define VA_LEDS_BASE (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
 833
 834 static void versatile_leds_event(led_event_t ledevt)
 835 {
 836         unsigned long flags;
 837         u32 val;
 838
 839         local_irq_save(flags);
 840         val = readl(VA_LEDS_BASE);
 841
 842         switch (ledevt) {
 843         case led_idle_start:
 844                 val = val & ~VERSATILE_SYS_LED0;
 845                 break;
 846
 847         case led_idle_end:
 848                 val = val | VERSATILE_SYS_LED0;
 849                 break;
 850
 851         case led_timer:
 852                 val = val ^ VERSATILE_SYS_LED1;
 853                 break;
 854
 855         case led_halted:
 856                 val = 0;
 857                 break;
 858
 859         default:
 860                 break;
 861         }
 862
 863         writel(val, VA_LEDS_BASE);
 864         local_irq_restore(flags);
 865 }
 866 #endif  /* CONFIG_LEDS */
 867
 868 void __init versatile_init(void)
 869 {
 870         int i;
 871
 872         osc4_clk.vcoreg = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_OSCCLCD_OFFSET;
 873
 874         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 875
 876         platform_device_register(&versatile_flash_device);
 877         platform_device_register(&versatile_i2c_device);
 878         platform_device_register(&smc91x_device);
 879         platform_device_register(&char_lcd_device);
 880
 881         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
 882                 struct amba_device *d = amba_devs[i];
 883                 amba_device_register(d, &iomem_resource);
 884         }
 885
 886 #ifdef CONFIG_LEDS
 887         leds_event = versatile_leds_event;
 888 #endif
 889 }
 890
 891 /*
 892  * The sched_clock counter
 893  */
 894 #define REFCOUNTER              (__io_address(VERSATILE_SYS_BASE) + \
 895                                  VERSATILE_SYS_24MHz_OFFSET)
 896
 897 /*
 898  * Where is the timer (VA)?
 899  */
 900 #define TIMER0_VA_BASE           __io_address(VERSATILE_TIMER0_1_BASE)
 901 #define TIMER1_VA_BASE          (__io_address(VERSATILE_TIMER0_1_BASE) + 0x20)
 902 #define TIMER2_VA_BASE           __io_address(VERSATILE_TIMER2_3_BASE)
 903 #define TIMER3_VA_BASE          (__io_address(VERSATILE_TIMER2_3_BASE) + 0x20)
 904
 905 /*
 906  * Set up timer interrupt, and return the current time in seconds.
 907  */
 908 static void __init versatile_timer_init(void)
 909 {
 910         u32 val;
 911
 912         versatile_sched_clock_init(REFCOUNTER, 24000000);
 913
 914         /*
 915          * set clock frequency:
 916          *      VERSATILE_REFCLK is 32KHz
 917          *      VERSATILE_TIMCLK is 1MHz
 918          */
 919         val = readl(__io_address(VERSATILE_SCTL_BASE));
 920         writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
 921                (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
 922                (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
 923                (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
 924                __io_address(VERSATILE_SCTL_BASE));
 925
 926         /*
 927          * Initialise to a known state (all timers off)
 928          */
 929         writel(0, TIMER0_VA_BASE + TIMER_CTRL);
 930         writel(0, TIMER1_VA_BASE + TIMER_CTRL);
 931         writel(0, TIMER2_VA_BASE + TIMER_CTRL);
 932         writel(0, TIMER3_VA_BASE + TIMER_CTRL);
 933
 934         sp804_clocksource_init(TIMER3_VA_BASE);
 935         sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMERINT0_1);
 936 }
 937
 938 struct sys_timer versatile_timer = {
 939         .init           = versatile_timer_init,
 940 };
 941