2 * Copyright (C) ST-Ericsson SA 2010
4 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
5 * License terms: GNU General Public License (GPL) version 2
8 #include <linux/platform_device.h>
10 #include <linux/clk.h>
12 #include <asm/cacheflush.h>
13 #include <asm/hardware/cache-l2x0.h>
14 #include <asm/hardware/gic.h>
15 #include <asm/mach/map.h>
16 #include <asm/localtimer.h>
19 #include <mach/hardware.h>
20 #include <mach/setup.h>
21 #include <mach/devices.h>
22 #include <mach/prcmu.h>
26 static struct map_desc ux500_io_desc[] __initdata = {
27 __IO_DEV_DESC(UX500_UART0_BASE, SZ_4K),
28 __IO_DEV_DESC(UX500_UART2_BASE, SZ_4K),
30 __IO_DEV_DESC(UX500_GIC_CPU_BASE, SZ_4K),
31 __IO_DEV_DESC(UX500_GIC_DIST_BASE, SZ_4K),
32 __IO_DEV_DESC(UX500_L2CC_BASE, SZ_4K),
33 __IO_DEV_DESC(UX500_TWD_BASE, SZ_4K),
34 __IO_DEV_DESC(UX500_SCU_BASE, SZ_4K),
36 __IO_DEV_DESC(UX500_CLKRST1_BASE, SZ_4K),
37 __IO_DEV_DESC(UX500_CLKRST2_BASE, SZ_4K),
38 __IO_DEV_DESC(UX500_CLKRST3_BASE, SZ_4K),
39 __IO_DEV_DESC(UX500_CLKRST5_BASE, SZ_4K),
40 __IO_DEV_DESC(UX500_CLKRST6_BASE, SZ_4K),
42 __IO_DEV_DESC(UX500_MTU0_BASE, SZ_4K),
43 __IO_DEV_DESC(UX500_MTU1_BASE, SZ_4K),
45 __IO_DEV_DESC(UX500_BACKUPRAM0_BASE, SZ_8K),
48 void __init ux500_map_io(void)
50 iotable_init(ux500_io_desc, ARRAY_SIZE(ux500_io_desc));
53 void __init ux500_init_irq(void)
55 gic_init(0, 29, __io_address(UX500_GIC_DIST_BASE),
56 __io_address(UX500_GIC_CPU_BASE));
59 * Init clocks here so that they are available for system timer
67 #ifdef CONFIG_CACHE_L2X0
68 static inline void ux500_cache_wait(void __iomem *reg, unsigned long mask)
70 /* wait for the operation to complete */
71 while (readl_relaxed(reg) & mask)
75 static inline void ux500_cache_sync(void)
77 void __iomem *base = __io_address(UX500_L2CC_BASE);
78 writel_relaxed(0, base + L2X0_CACHE_SYNC);
79 ux500_cache_wait(base + L2X0_CACHE_SYNC, 1);
83 * The L2 cache cannot be turned off in the non-secure world.
84 * Dummy until a secure service is in place.
86 static void ux500_l2x0_disable(void)
91 * This is only called when doing a kexec, just after turning off the L2
92 * and L1 cache, and it is surrounded by a spinlock in the generic version.
93 * However, we're not really turning off the L2 cache right now and the
94 * PL310 does not support exclusive accesses (used to implement the spinlock).
95 * So, the invalidation needs to be done without the spinlock.
97 static void ux500_l2x0_inv_all(void)
99 void __iomem *l2x0_base = __io_address(UX500_L2CC_BASE);
100 uint32_t l2x0_way_mask = (1<<16) - 1; /* Bitmask of active ways */
102 /* invalidate all ways */
103 writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
104 ux500_cache_wait(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
108 static int ux500_l2x0_init(void)
110 void __iomem *l2x0_base;
112 l2x0_base = __io_address(UX500_L2CC_BASE);
114 /* 64KB way size, 8 way associativity, force WA */
115 l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff);
117 /* Override invalidate function */
118 outer_cache.disable = ux500_l2x0_disable;
119 outer_cache.inv_all = ux500_l2x0_inv_all;
123 early_initcall(ux500_l2x0_init);
126 static void __init ux500_timer_init(void)
128 #ifdef CONFIG_LOCAL_TIMERS
129 /* Setup the local timer base */
130 twd_base = __io_address(UX500_TWD_BASE);
132 /* Setup the MTU base */
133 if (cpu_is_u8500ed())
134 mtu_base = __io_address(U8500_MTU0_BASE_ED);
136 mtu_base = __io_address(UX500_MTU0_BASE);
141 struct sys_timer ux500_timer = {
142 .init = ux500_timer_init,