arch/arm/mach-u300/core.c

   1 /*
   2  *
   3  * arch/arm/mach-u300/core.c
   4  *
   5  *
   6  * Copyright (C) 2007-2010 ST-Ericsson AB
   7  * License terms: GNU General Public License (GPL) version 2
   8  * Core platform support, IRQ handling and device definitions.
   9  * Author: Linus Walleij <linus.walleij@stericsson.com>
  10  */
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/spinlock.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/bitops.h>
  16 #include <linux/device.h>
  17 #include <linux/mm.h>
  18 #include <linux/termios.h>
  19 #include <linux/amba/bus.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/gpio.h>
  22 #include <linux/clk.h>
  23 #include <linux/err.h>
  24 #include <linux/mtd/nand.h>
  25 #include <linux/mtd/fsmc.h>
  26
  27 #include <asm/types.h>
  28 #include <asm/setup.h>
  29 #include <asm/memory.h>
  30 #include <asm/hardware/vic.h>
  31 #include <asm/mach/map.h>
  32 #include <asm/mach/irq.h>
  33
  34 #include <mach/coh901318.h>
  35 #include <mach/hardware.h>
  36 #include <mach/syscon.h>
  37 #include <mach/dma_channels.h>
  38
  39 #include "clock.h"
  40 #include "mmc.h"
  41 #include "spi.h"
  42 #include "i2c.h"
  43
  44 /*
  45  * Static I/O mappings that are needed for booting the U300 platforms. The
  46  * only things we need are the areas where we find the timer, syscon and
  47  * intcon, since the remaining device drivers will map their own memory
  48  * physical to virtual as the need arise.
  49  */
  50 static struct map_desc u300_io_desc[] __initdata = {
  51         {
  52                 .virtual        = U300_SLOW_PER_VIRT_BASE,
  53                 .pfn            = __phys_to_pfn(U300_SLOW_PER_PHYS_BASE),
  54                 .length         = SZ_64K,
  55                 .type           = MT_DEVICE,
  56         },
  57         {
  58                 .virtual        = U300_AHB_PER_VIRT_BASE,
  59                 .pfn            = __phys_to_pfn(U300_AHB_PER_PHYS_BASE),
  60                 .length         = SZ_32K,
  61                 .type           = MT_DEVICE,
  62         },
  63         {
  64                 .virtual        = U300_FAST_PER_VIRT_BASE,
  65                 .pfn            = __phys_to_pfn(U300_FAST_PER_PHYS_BASE),
  66                 .length         = SZ_32K,
  67                 .type           = MT_DEVICE,
  68         },
  69         {
  70                 .virtual        = 0xffff2000, /* TCM memory */
  71                 .pfn            = __phys_to_pfn(0xffff2000),
  72                 .length         = SZ_16K,
  73                 .type           = MT_DEVICE,
  74         },
  75
  76         /*
  77          * This overlaps with the IRQ vectors etc at 0xffff0000, so these
  78          * may have to be moved to 0x00000000 in order to use the ROM.
  79          */
  80         /*
  81         {
  82                 .virtual        = U300_BOOTROM_VIRT_BASE,
  83                 .pfn            = __phys_to_pfn(U300_BOOTROM_PHYS_BASE),
  84                 .length         = SZ_64K,
  85                 .type           = MT_ROM,
  86         },
  87         */
  88 };
  89
  90 void __init u300_map_io(void)
  91 {
  92         iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc));
  93 }
  94
  95 /*
  96  * Declaration of devices found on the U300 board and
  97  * their respective memory locations.
  98  */
  99 static struct amba_device uart0_device = {
 100         .dev = {
 101                 .init_name = "uart0", /* Slow device at 0x3000 offset */
 102                 .platform_data = NULL,
 103         },
 104         .res = {
 105                 .start = U300_UART0_BASE,
 106                 .end   = U300_UART0_BASE + SZ_4K - 1,
 107                 .flags = IORESOURCE_MEM,
 108         },
 109         .irq = { IRQ_U300_UART0, NO_IRQ },
 110 };
 111
 112 /* The U335 have an additional UART1 on the APP CPU */
 113 #ifdef CONFIG_MACH_U300_BS335
 114 static struct amba_device uart1_device = {
 115         .dev = {
 116                 .init_name = "uart1", /* Fast device at 0x7000 offset */
 117                 .platform_data = NULL,
 118         },
 119         .res = {
 120                 .start = U300_UART1_BASE,
 121                 .end   = U300_UART1_BASE + SZ_4K - 1,
 122                 .flags = IORESOURCE_MEM,
 123         },
 124         .irq = { IRQ_U300_UART1, NO_IRQ },
 125 };
 126 #endif
 127
 128 static struct amba_device pl172_device = {
 129         .dev = {
 130                 .init_name = "pl172", /* AHB device at 0x4000 offset */
 131                 .platform_data = NULL,
 132         },
 133         .res = {
 134                 .start = U300_EMIF_CFG_BASE,
 135                 .end   = U300_EMIF_CFG_BASE + SZ_4K - 1,
 136                 .flags = IORESOURCE_MEM,
 137         },
 138 };
 139
 140
 141 /*
 142  * Everything within this next ifdef deals with external devices connected to
 143  * the APP SPI bus.
 144  */
 145 static struct amba_device pl022_device = {
 146         .dev = {
 147                 .coherent_dma_mask = ~0,
 148                 .init_name = "pl022", /* Fast device at 0x6000 offset */
 149         },
 150         .res = {
 151                 .start = U300_SPI_BASE,
 152                 .end   = U300_SPI_BASE + SZ_4K - 1,
 153                 .flags = IORESOURCE_MEM,
 154         },
 155         .irq = {IRQ_U300_SPI, NO_IRQ },
 156         /*
 157          * This device has a DMA channel but the Linux driver does not use
 158          * it currently.
 159          */
 160 };
 161
 162 static struct amba_device mmcsd_device = {
 163         .dev = {
 164                 .init_name = "mmci", /* Fast device at 0x1000 offset */
 165                 .platform_data = NULL, /* Added later */
 166         },
 167         .res = {
 168                 .start = U300_MMCSD_BASE,
 169                 .end   = U300_MMCSD_BASE + SZ_4K - 1,
 170                 .flags = IORESOURCE_MEM,
 171         },
 172         .irq = {IRQ_U300_MMCSD_MCIINTR0, IRQ_U300_MMCSD_MCIINTR1 },
 173         /*
 174          * This device has a DMA channel but the Linux driver does not use
 175          * it currently.
 176          */
 177 };
 178
 179 /*
 180  * The order of device declaration may be important, since some devices
 181  * have dependencies on other devices being initialized first.
 182  */
 183 static struct amba_device *amba_devs[] __initdata = {
 184         &uart0_device,
 185 #ifdef CONFIG_MACH_U300_BS335
 186         &uart1_device,
 187 #endif
 188         &pl022_device,
 189         &pl172_device,
 190         &mmcsd_device,
 191 };
 192
 193 /* Here follows a list of all hw resources that the platform devices
 194  * allocate. Note, clock dependencies are not included
 195  */
 196
 197 static struct resource gpio_resources[] = {
 198         {
 199                 .start = U300_GPIO_BASE,
 200                 .end   = (U300_GPIO_BASE + SZ_4K - 1),
 201                 .flags = IORESOURCE_MEM,
 202         },
 203         {
 204                 .name  = "gpio0",
 205                 .start = IRQ_U300_GPIO_PORT0,
 206                 .end   = IRQ_U300_GPIO_PORT0,
 207                 .flags = IORESOURCE_IRQ,
 208         },
 209         {
 210                 .name  = "gpio1",
 211                 .start = IRQ_U300_GPIO_PORT1,
 212                 .end   = IRQ_U300_GPIO_PORT1,
 213                 .flags = IORESOURCE_IRQ,
 214         },
 215         {
 216                 .name  = "gpio2",
 217                 .start = IRQ_U300_GPIO_PORT2,
 218                 .end   = IRQ_U300_GPIO_PORT2,
 219                 .flags = IORESOURCE_IRQ,
 220         },
 221 #ifdef U300_COH901571_3
 222         {
 223                 .name  = "gpio3",
 224                 .start = IRQ_U300_GPIO_PORT3,
 225                 .end   = IRQ_U300_GPIO_PORT3,
 226                 .flags = IORESOURCE_IRQ,
 227         },
 228         {
 229                 .name  = "gpio4",
 230                 .start = IRQ_U300_GPIO_PORT4,
 231                 .end   = IRQ_U300_GPIO_PORT4,
 232                 .flags = IORESOURCE_IRQ,
 233         },
 234 #ifdef CONFIG_MACH_U300_BS335
 235         {
 236                 .name  = "gpio5",
 237                 .start = IRQ_U300_GPIO_PORT5,
 238                 .end   = IRQ_U300_GPIO_PORT5,
 239                 .flags = IORESOURCE_IRQ,
 240         },
 241         {
 242                 .name  = "gpio6",
 243                 .start = IRQ_U300_GPIO_PORT6,
 244                 .end   = IRQ_U300_GPIO_PORT6,
 245                 .flags = IORESOURCE_IRQ,
 246         },
 247 #endif /* CONFIG_MACH_U300_BS335 */
 248 #endif /* U300_COH901571_3 */
 249 };
 250
 251 static struct resource keypad_resources[] = {
 252         {
 253                 .start = U300_KEYPAD_BASE,
 254                 .end   = U300_KEYPAD_BASE + SZ_4K - 1,
 255                 .flags = IORESOURCE_MEM,
 256         },
 257         {
 258                 .name  = "coh901461-press",
 259                 .start = IRQ_U300_KEYPAD_KEYBF,
 260                 .end   = IRQ_U300_KEYPAD_KEYBF,
 261                 .flags = IORESOURCE_IRQ,
 262         },
 263         {
 264                 .name  = "coh901461-release",
 265                 .start = IRQ_U300_KEYPAD_KEYBR,
 266                 .end   = IRQ_U300_KEYPAD_KEYBR,
 267                 .flags = IORESOURCE_IRQ,
 268         },
 269 };
 270
 271 static struct resource rtc_resources[] = {
 272         {
 273                 .start = U300_RTC_BASE,
 274                 .end   = U300_RTC_BASE + SZ_4K - 1,
 275                 .flags = IORESOURCE_MEM,
 276         },
 277         {
 278                 .start = IRQ_U300_RTC,
 279                 .end   = IRQ_U300_RTC,
 280                 .flags = IORESOURCE_IRQ,
 281         },
 282 };
 283
 284 /*
 285  * Fsmc does have IRQs: #43 and #44 (NFIF and NFIF2)
 286  * but these are not yet used by the driver.
 287  */
 288 static struct resource fsmc_resources[] = {
 289         {
 290                 .name  = "nand_data",
 291                 .start = U300_NAND_CS0_PHYS_BASE,
 292                 .end   = U300_NAND_CS0_PHYS_BASE + SZ_16K - 1,
 293                 .flags = IORESOURCE_MEM,
 294         },
 295         {
 296                 .name  = "fsmc_regs",
 297                 .start = U300_NAND_IF_PHYS_BASE,
 298                 .end   = U300_NAND_IF_PHYS_BASE + SZ_4K - 1,
 299                 .flags = IORESOURCE_MEM,
 300         },
 301 };
 302
 303 static struct resource i2c0_resources[] = {
 304         {
 305                 .start = U300_I2C0_BASE,
 306                 .end   = U300_I2C0_BASE + SZ_4K - 1,
 307                 .flags = IORESOURCE_MEM,
 308         },
 309         {
 310                 .start = IRQ_U300_I2C0,
 311                 .end   = IRQ_U300_I2C0,
 312                 .flags = IORESOURCE_IRQ,
 313         },
 314 };
 315
 316 static struct resource i2c1_resources[] = {
 317         {
 318                 .start = U300_I2C1_BASE,
 319                 .end   = U300_I2C1_BASE + SZ_4K - 1,
 320                 .flags = IORESOURCE_MEM,
 321         },
 322         {
 323                 .start = IRQ_U300_I2C1,
 324                 .end   = IRQ_U300_I2C1,
 325                 .flags = IORESOURCE_IRQ,
 326         },
 327
 328 };
 329
 330 static struct resource wdog_resources[] = {
 331         {
 332                 .start = U300_WDOG_BASE,
 333                 .end   = U300_WDOG_BASE + SZ_4K - 1,
 334                 .flags = IORESOURCE_MEM,
 335         },
 336         {
 337                 .start = IRQ_U300_WDOG,
 338                 .end   = IRQ_U300_WDOG,
 339                 .flags = IORESOURCE_IRQ,
 340         }
 341 };
 342
 343 /* TODO: These should be protected by suitable #ifdef's */
 344 static struct resource ave_resources[] = {
 345         {
 346                 .name  = "AVE3e I/O Area",
 347                 .start = U300_VIDEOENC_BASE,
 348                 .end   = U300_VIDEOENC_BASE + SZ_512K - 1,
 349                 .flags = IORESOURCE_MEM,
 350         },
 351         {
 352                 .name  = "AVE3e IRQ0",
 353                 .start = IRQ_U300_VIDEO_ENC_0,
 354                 .end   = IRQ_U300_VIDEO_ENC_0,
 355                 .flags = IORESOURCE_IRQ,
 356         },
 357         {
 358                 .name  = "AVE3e IRQ1",
 359                 .start = IRQ_U300_VIDEO_ENC_1,
 360                 .end   = IRQ_U300_VIDEO_ENC_1,
 361                 .flags = IORESOURCE_IRQ,
 362         },
 363         {
 364                 .name  = "AVE3e Physmem Area",
 365                 .start = 0, /* 0 will be remapped to reserved memory */
 366                 .end   = SZ_1M - 1,
 367                 .flags = IORESOURCE_MEM,
 368         },
 369         /*
 370          * The AVE3e requires two regions of 256MB that it considers
 371          * "invisible". The hardware will not be able to access these
 372          * addresses, so they should never point to system RAM.
 373          */
 374         {
 375                 .name  = "AVE3e Reserved 0",
 376                 .start = 0xd0000000,
 377                 .end   = 0xd0000000 + SZ_256M - 1,
 378                 .flags = IORESOURCE_MEM,
 379         },
 380         {
 381                 .name  = "AVE3e Reserved 1",
 382                 .start = 0xe0000000,
 383                 .end   = 0xe0000000 + SZ_256M - 1,
 384                 .flags = IORESOURCE_MEM,
 385         },
 386 };
 387
 388 static struct resource dma_resource[] = {
 389         {
 390                 .start = U300_DMAC_BASE,
 391                 .end = U300_DMAC_BASE + PAGE_SIZE - 1,
 392                 .flags =  IORESOURCE_MEM,
 393         },
 394         {
 395                 .start = IRQ_U300_DMA,
 396                 .end = IRQ_U300_DMA,
 397                 .flags =  IORESOURCE_IRQ,
 398         }
 399 };
 400
 401 #ifdef CONFIG_MACH_U300_BS335
 402 /* points out all dma slave channels.
 403  * Syntax is [A1, B1, A2, B2, .... ,-1,-1]
 404  * Select all channels from A to B, end of list is marked with -1,-1
 405  */
 406 static int dma_slave_channels[] = {
 407         U300_DMA_MSL_TX_0, U300_DMA_SPI_RX,
 408         U300_DMA_UART1_TX, U300_DMA_UART1_RX, -1, -1};
 409
 410 /* points out all dma memcpy channels. */
 411 static int dma_memcpy_channels[] = {
 412         U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1};
 413
 414 #else /* CONFIG_MACH_U300_BS335 */
 415
 416 static int dma_slave_channels[] = {U300_DMA_MSL_TX_0, U300_DMA_SPI_RX, -1, -1};
 417 static int dma_memcpy_channels[] = {
 418         U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_10, -1, -1};
 419
 420 #endif
 421
 422 /** register dma for memory access
 423  *
 424  * active  1 means dma intends to access memory
 425  *         0 means dma wont access memory
 426  */
 427 static void coh901318_access_memory_state(struct device *dev, bool active)
 428 {
 429 }
 430
 431 #define flags_memcpy_config (COH901318_CX_CFG_CH_DISABLE | \
 432                         COH901318_CX_CFG_RM_MEMORY_TO_MEMORY | \
 433                         COH901318_CX_CFG_LCR_DISABLE | \
 434                         COH901318_CX_CFG_TC_IRQ_ENABLE | \
 435                         COH901318_CX_CFG_BE_IRQ_ENABLE)
 436 #define flags_memcpy_lli_chained (COH901318_CX_CTRL_TC_ENABLE | \
 437                         COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
 438                         COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
 439                         COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
 440                         COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
 441                         COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
 442                         COH901318_CX_CTRL_MASTER_MODE_M1RW | \
 443                         COH901318_CX_CTRL_TCP_DISABLE | \
 444                         COH901318_CX_CTRL_TC_IRQ_DISABLE | \
 445                         COH901318_CX_CTRL_HSP_DISABLE | \
 446                         COH901318_CX_CTRL_HSS_DISABLE | \
 447                         COH901318_CX_CTRL_DDMA_LEGACY | \
 448                         COH901318_CX_CTRL_PRDD_SOURCE)
 449 #define flags_memcpy_lli (COH901318_CX_CTRL_TC_ENABLE | \
 450                         COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
 451                         COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
 452                         COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
 453                         COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
 454                         COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
 455                         COH901318_CX_CTRL_MASTER_MODE_M1RW | \
 456                         COH901318_CX_CTRL_TCP_DISABLE | \
 457                         COH901318_CX_CTRL_TC_IRQ_DISABLE | \
 458                         COH901318_CX_CTRL_HSP_DISABLE | \
 459                         COH901318_CX_CTRL_HSS_DISABLE | \
 460                         COH901318_CX_CTRL_DDMA_LEGACY | \
 461                         COH901318_CX_CTRL_PRDD_SOURCE)
 462 #define flags_memcpy_lli_last (COH901318_CX_CTRL_TC_ENABLE | \
 463                         COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
 464                         COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
 465                         COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
 466                         COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
 467                         COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
 468                         COH901318_CX_CTRL_MASTER_MODE_M1RW | \
 469                         COH901318_CX_CTRL_TCP_DISABLE | \
 470                         COH901318_CX_CTRL_TC_IRQ_ENABLE | \
 471                         COH901318_CX_CTRL_HSP_DISABLE | \
 472                         COH901318_CX_CTRL_HSS_DISABLE | \
 473                         COH901318_CX_CTRL_DDMA_LEGACY | \
 474                         COH901318_CX_CTRL_PRDD_SOURCE)
 475
 476 const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
 477         {
 478                 .number = U300_DMA_MSL_TX_0,
 479                 .name = "MSL TX 0",
 480                 .priority_high = 0,
 481                 .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x20,
 482         },
 483         {
 484                 .number = U300_DMA_MSL_TX_1,
 485                 .name = "MSL TX 1",
 486                 .priority_high = 0,
 487                 .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x20,
 488                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 489                                 COH901318_CX_CFG_LCR_DISABLE |
 490                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 491                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 492                 .param.ctrl_lli_chained = 0 |
 493                                 COH901318_CX_CTRL_TC_ENABLE |
 494                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 495                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 496                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 497                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 498                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 499                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 500                                 COH901318_CX_CTRL_TCP_DISABLE |
 501                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 502                                 COH901318_CX_CTRL_HSP_ENABLE |
 503                                 COH901318_CX_CTRL_HSS_DISABLE |
 504                                 COH901318_CX_CTRL_DDMA_LEGACY |
 505                                 COH901318_CX_CTRL_PRDD_SOURCE,
 506                 .param.ctrl_lli = 0 |
 507                                 COH901318_CX_CTRL_TC_ENABLE |
 508                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 509                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 510                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 511                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 512                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 513                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 514                                 COH901318_CX_CTRL_TCP_ENABLE |
 515                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 516                                 COH901318_CX_CTRL_HSP_ENABLE |
 517                                 COH901318_CX_CTRL_HSS_DISABLE |
 518                                 COH901318_CX_CTRL_DDMA_LEGACY |
 519                                 COH901318_CX_CTRL_PRDD_SOURCE,
 520                 .param.ctrl_lli_last = 0 |
 521                                 COH901318_CX_CTRL_TC_ENABLE |
 522                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 523                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 524                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 525                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 526                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 527                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 528                                 COH901318_CX_CTRL_TCP_ENABLE |
 529                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 530                                 COH901318_CX_CTRL_HSP_ENABLE |
 531                                 COH901318_CX_CTRL_HSS_DISABLE |
 532                                 COH901318_CX_CTRL_DDMA_LEGACY |
 533                                 COH901318_CX_CTRL_PRDD_SOURCE,
 534         },
 535         {
 536                 .number = U300_DMA_MSL_TX_2,
 537                 .name = "MSL TX 2",
 538                 .priority_high = 0,
 539                 .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x20,
 540                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 541                                 COH901318_CX_CFG_LCR_DISABLE |
 542                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 543                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 544                 .param.ctrl_lli_chained = 0 |
 545                                 COH901318_CX_CTRL_TC_ENABLE |
 546                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 547                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 548                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 549                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 550                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 551                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 552                                 COH901318_CX_CTRL_TCP_DISABLE |
 553                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 554                                 COH901318_CX_CTRL_HSP_ENABLE |
 555                                 COH901318_CX_CTRL_HSS_DISABLE |
 556                                 COH901318_CX_CTRL_DDMA_LEGACY |
 557                                 COH901318_CX_CTRL_PRDD_SOURCE,
 558                 .param.ctrl_lli = 0 |
 559                                 COH901318_CX_CTRL_TC_ENABLE |
 560                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 561                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 562                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 563                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 564                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 565                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 566                                 COH901318_CX_CTRL_TCP_ENABLE |
 567                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 568                                 COH901318_CX_CTRL_HSP_ENABLE |
 569                                 COH901318_CX_CTRL_HSS_DISABLE |
 570                                 COH901318_CX_CTRL_DDMA_LEGACY |
 571                                 COH901318_CX_CTRL_PRDD_SOURCE,
 572                 .param.ctrl_lli_last = 0 |
 573                                 COH901318_CX_CTRL_TC_ENABLE |
 574                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 575                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 576                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 577                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 578                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 579                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 580                                 COH901318_CX_CTRL_TCP_ENABLE |
 581                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 582                                 COH901318_CX_CTRL_HSP_ENABLE |
 583                                 COH901318_CX_CTRL_HSS_DISABLE |
 584                                 COH901318_CX_CTRL_DDMA_LEGACY |
 585                                 COH901318_CX_CTRL_PRDD_SOURCE,
 586                 .desc_nbr_max = 10,
 587         },
 588         {
 589                 .number = U300_DMA_MSL_TX_3,
 590                 .name = "MSL TX 3",
 591                 .priority_high = 0,
 592                 .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x20,
 593                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 594                                 COH901318_CX_CFG_LCR_DISABLE |
 595                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 596                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 597                 .param.ctrl_lli_chained = 0 |
 598                                 COH901318_CX_CTRL_TC_ENABLE |
 599                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 600                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 601                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 602                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 603                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 604                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 605                                 COH901318_CX_CTRL_TCP_DISABLE |
 606                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 607                                 COH901318_CX_CTRL_HSP_ENABLE |
 608                                 COH901318_CX_CTRL_HSS_DISABLE |
 609                                 COH901318_CX_CTRL_DDMA_LEGACY |
 610                                 COH901318_CX_CTRL_PRDD_SOURCE,
 611                 .param.ctrl_lli = 0 |
 612                                 COH901318_CX_CTRL_TC_ENABLE |
 613                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 614                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 615                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 616                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 617                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 618                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 619                                 COH901318_CX_CTRL_TCP_ENABLE |
 620                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 621                                 COH901318_CX_CTRL_HSP_ENABLE |
 622                                 COH901318_CX_CTRL_HSS_DISABLE |
 623                                 COH901318_CX_CTRL_DDMA_LEGACY |
 624                                 COH901318_CX_CTRL_PRDD_SOURCE,
 625                 .param.ctrl_lli_last = 0 |
 626                                 COH901318_CX_CTRL_TC_ENABLE |
 627                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 628                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 629                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 630                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 631                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 632                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 633                                 COH901318_CX_CTRL_TCP_ENABLE |
 634                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 635                                 COH901318_CX_CTRL_HSP_ENABLE |
 636                                 COH901318_CX_CTRL_HSS_DISABLE |
 637                                 COH901318_CX_CTRL_DDMA_LEGACY |
 638                                 COH901318_CX_CTRL_PRDD_SOURCE,
 639         },
 640         {
 641                 .number = U300_DMA_MSL_TX_4,
 642                 .name = "MSL TX 4",
 643                 .priority_high = 0,
 644                 .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x20,
 645                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 646                                 COH901318_CX_CFG_LCR_DISABLE |
 647                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 648                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 649                 .param.ctrl_lli_chained = 0 |
 650                                 COH901318_CX_CTRL_TC_ENABLE |
 651                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 652                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 653                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 654                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 655                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 656                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 657                                 COH901318_CX_CTRL_TCP_DISABLE |
 658                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 659                                 COH901318_CX_CTRL_HSP_ENABLE |
 660                                 COH901318_CX_CTRL_HSS_DISABLE |
 661                                 COH901318_CX_CTRL_DDMA_LEGACY |
 662                                 COH901318_CX_CTRL_PRDD_SOURCE,
 663                 .param.ctrl_lli = 0 |
 664                                 COH901318_CX_CTRL_TC_ENABLE |
 665                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 666                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 667                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 668                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 669                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 670                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 671                                 COH901318_CX_CTRL_TCP_ENABLE |
 672                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 673                                 COH901318_CX_CTRL_HSP_ENABLE |
 674                                 COH901318_CX_CTRL_HSS_DISABLE |
 675                                 COH901318_CX_CTRL_DDMA_LEGACY |
 676                                 COH901318_CX_CTRL_PRDD_SOURCE,
 677                 .param.ctrl_lli_last = 0 |
 678                                 COH901318_CX_CTRL_TC_ENABLE |
 679                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 680                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 681                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 682                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 683                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 684                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 685                                 COH901318_CX_CTRL_TCP_ENABLE |
 686                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 687                                 COH901318_CX_CTRL_HSP_ENABLE |
 688                                 COH901318_CX_CTRL_HSS_DISABLE |
 689                                 COH901318_CX_CTRL_DDMA_LEGACY |
 690                                 COH901318_CX_CTRL_PRDD_SOURCE,
 691         },
 692         {
 693                 .number = U300_DMA_MSL_TX_5,
 694                 .name = "MSL TX 5",
 695                 .priority_high = 0,
 696                 .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x20,
 697         },
 698         {
 699                 .number = U300_DMA_MSL_TX_6,
 700                 .name = "MSL TX 6",
 701                 .priority_high = 0,
 702                 .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x20,
 703         },
 704         {
 705                 .number = U300_DMA_MSL_RX_0,
 706                 .name = "MSL RX 0",
 707                 .priority_high = 0,
 708                 .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x220,
 709         },
 710         {
 711                 .number = U300_DMA_MSL_RX_1,
 712                 .name = "MSL RX 1",
 713                 .priority_high = 0,
 714                 .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x220,
 715                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 716                                 COH901318_CX_CFG_LCR_DISABLE |
 717                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 718                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 719                 .param.ctrl_lli_chained = 0 |
 720                                 COH901318_CX_CTRL_TC_ENABLE |
 721                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 722                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 723                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 724                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 725                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 726                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 727                                 COH901318_CX_CTRL_TCP_DISABLE |
 728                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 729                                 COH901318_CX_CTRL_HSP_ENABLE |
 730                                 COH901318_CX_CTRL_HSS_DISABLE |
 731                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 732                                 COH901318_CX_CTRL_PRDD_DEST,
 733                 .param.ctrl_lli = 0,
 734                 .param.ctrl_lli_last = 0 |
 735                                 COH901318_CX_CTRL_TC_ENABLE |
 736                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 737                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 738                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 739                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 740                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 741                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 742                                 COH901318_CX_CTRL_TCP_DISABLE |
 743                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 744                                 COH901318_CX_CTRL_HSP_ENABLE |
 745                                 COH901318_CX_CTRL_HSS_DISABLE |
 746                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 747                                 COH901318_CX_CTRL_PRDD_DEST,
 748         },
 749         {
 750                 .number = U300_DMA_MSL_RX_2,
 751                 .name = "MSL RX 2",
 752                 .priority_high = 0,
 753                 .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x220,
 754                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 755                                 COH901318_CX_CFG_LCR_DISABLE |
 756                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 757                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 758                 .param.ctrl_lli_chained = 0 |
 759                                 COH901318_CX_CTRL_TC_ENABLE |
 760                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 761                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 762                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 763                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 764                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 765                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 766                                 COH901318_CX_CTRL_TCP_DISABLE |
 767                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 768                                 COH901318_CX_CTRL_HSP_ENABLE |
 769                                 COH901318_CX_CTRL_HSS_DISABLE |
 770                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 771                                 COH901318_CX_CTRL_PRDD_DEST,
 772                 .param.ctrl_lli = 0 |
 773                                 COH901318_CX_CTRL_TC_ENABLE |
 774                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 775                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 776                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 777                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 778                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 779                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 780                                 COH901318_CX_CTRL_TCP_DISABLE |
 781                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 782                                 COH901318_CX_CTRL_HSP_ENABLE |
 783                                 COH901318_CX_CTRL_HSS_DISABLE |
 784                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 785                                 COH901318_CX_CTRL_PRDD_DEST,
 786                 .param.ctrl_lli_last = 0 |
 787                                 COH901318_CX_CTRL_TC_ENABLE |
 788                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 789                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 790                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 791                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 792                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 793                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 794                                 COH901318_CX_CTRL_TCP_DISABLE |
 795                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 796                                 COH901318_CX_CTRL_HSP_ENABLE |
 797                                 COH901318_CX_CTRL_HSS_DISABLE |
 798                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 799                                 COH901318_CX_CTRL_PRDD_DEST,
 800         },
 801         {
 802                 .number = U300_DMA_MSL_RX_3,
 803                 .name = "MSL RX 3",
 804                 .priority_high = 0,
 805                 .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x220,
 806                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 807                                 COH901318_CX_CFG_LCR_DISABLE |
 808                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 809                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 810                 .param.ctrl_lli_chained = 0 |
 811                                 COH901318_CX_CTRL_TC_ENABLE |
 812                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 813                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 814                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 815                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 816                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 817                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 818                                 COH901318_CX_CTRL_TCP_DISABLE |
 819                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 820                                 COH901318_CX_CTRL_HSP_ENABLE |
 821                                 COH901318_CX_CTRL_HSS_DISABLE |
 822                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 823                                 COH901318_CX_CTRL_PRDD_DEST,
 824                 .param.ctrl_lli = 0 |
 825                                 COH901318_CX_CTRL_TC_ENABLE |
 826                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 827                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 828                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 829                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 830                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 831                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 832                                 COH901318_CX_CTRL_TCP_DISABLE |
 833                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 834                                 COH901318_CX_CTRL_HSP_ENABLE |
 835                                 COH901318_CX_CTRL_HSS_DISABLE |
 836                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 837                                 COH901318_CX_CTRL_PRDD_DEST,
 838                 .param.ctrl_lli_last = 0 |
 839                                 COH901318_CX_CTRL_TC_ENABLE |
 840                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 841                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 842                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 843                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 844                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 845                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 846                                 COH901318_CX_CTRL_TCP_DISABLE |
 847                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 848                                 COH901318_CX_CTRL_HSP_ENABLE |
 849                                 COH901318_CX_CTRL_HSS_DISABLE |
 850                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 851                                 COH901318_CX_CTRL_PRDD_DEST,
 852         },
 853         {
 854                 .number = U300_DMA_MSL_RX_4,
 855                 .name = "MSL RX 4",
 856                 .priority_high = 0,
 857                 .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x220,
 858                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 859                                 COH901318_CX_CFG_LCR_DISABLE |
 860                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 861                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 862                 .param.ctrl_lli_chained = 0 |
 863                                 COH901318_CX_CTRL_TC_ENABLE |
 864                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 865                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 866                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 867                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 868                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 869                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 870                                 COH901318_CX_CTRL_TCP_DISABLE |
 871                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 872                                 COH901318_CX_CTRL_HSP_ENABLE |
 873                                 COH901318_CX_CTRL_HSS_DISABLE |
 874                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 875                                 COH901318_CX_CTRL_PRDD_DEST,
 876                 .param.ctrl_lli = 0 |
 877                                 COH901318_CX_CTRL_TC_ENABLE |
 878                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 879                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 880                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 881                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 882                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 883                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 884                                 COH901318_CX_CTRL_TCP_DISABLE |
 885                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 886                                 COH901318_CX_CTRL_HSP_ENABLE |
 887                                 COH901318_CX_CTRL_HSS_DISABLE |
 888                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 889                                 COH901318_CX_CTRL_PRDD_DEST,
 890                 .param.ctrl_lli_last = 0 |
 891                                 COH901318_CX_CTRL_TC_ENABLE |
 892                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 893                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 894                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 895                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 896                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 897                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 898                                 COH901318_CX_CTRL_TCP_DISABLE |
 899                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 900                                 COH901318_CX_CTRL_HSP_ENABLE |
 901                                 COH901318_CX_CTRL_HSS_DISABLE |
 902                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 903                                 COH901318_CX_CTRL_PRDD_DEST,
 904         },
 905         {
 906                 .number = U300_DMA_MSL_RX_5,
 907                 .name = "MSL RX 5",
 908                 .priority_high = 0,
 909                 .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x220,
 910                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 911                                 COH901318_CX_CFG_LCR_DISABLE |
 912                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 913                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 914                 .param.ctrl_lli_chained = 0 |
 915                                 COH901318_CX_CTRL_TC_ENABLE |
 916                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 917                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 918                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 919                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 920                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 921                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 922                                 COH901318_CX_CTRL_TCP_DISABLE |
 923                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 924                                 COH901318_CX_CTRL_HSP_ENABLE |
 925                                 COH901318_CX_CTRL_HSS_DISABLE |
 926                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 927                                 COH901318_CX_CTRL_PRDD_DEST,
 928                 .param.ctrl_lli = 0 |
 929                                 COH901318_CX_CTRL_TC_ENABLE |
 930                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 931                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 932                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 933                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 934                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 935                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 936                                 COH901318_CX_CTRL_TCP_DISABLE |
 937                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 938                                 COH901318_CX_CTRL_HSP_ENABLE |
 939                                 COH901318_CX_CTRL_HSS_DISABLE |
 940                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 941                                 COH901318_CX_CTRL_PRDD_DEST,
 942                 .param.ctrl_lli_last = 0 |
 943                                 COH901318_CX_CTRL_TC_ENABLE |
 944                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 945                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 946                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 947                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 948                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 949                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 950                                 COH901318_CX_CTRL_TCP_DISABLE |
 951                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 952                                 COH901318_CX_CTRL_HSP_ENABLE |
 953                                 COH901318_CX_CTRL_HSS_DISABLE |
 954                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 955                                 COH901318_CX_CTRL_PRDD_DEST,
 956         },
 957         {
 958                 .number = U300_DMA_MSL_RX_6,
 959                 .name = "MSL RX 6",
 960                 .priority_high = 0,
 961                 .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x220,
 962         },
 963         {
 964                 .number = U300_DMA_MMCSD_RX_TX,
 965                 .name = "MMCSD RX TX",
 966                 .priority_high = 0,
 967                 .dev_addr =  U300_MMCSD_BASE + 0x080,
 968                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 969                                 COH901318_CX_CFG_LCR_DISABLE |
 970                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 971                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 972                 .param.ctrl_lli_chained = 0 |
 973                                 COH901318_CX_CTRL_TC_ENABLE |
 974                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 975                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 976                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 977                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 978                                 COH901318_CX_CTRL_TCP_ENABLE |
 979                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 980                                 COH901318_CX_CTRL_HSP_ENABLE |
 981                                 COH901318_CX_CTRL_HSS_DISABLE |
 982                                 COH901318_CX_CTRL_DDMA_LEGACY,
 983                 .param.ctrl_lli = 0 |
 984                                 COH901318_CX_CTRL_TC_ENABLE |
 985                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 986                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 987                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 988                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 989                                 COH901318_CX_CTRL_TCP_ENABLE |
 990                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 991                                 COH901318_CX_CTRL_HSP_ENABLE |
 992                                 COH901318_CX_CTRL_HSS_DISABLE |
 993                                 COH901318_CX_CTRL_DDMA_LEGACY,
 994                 .param.ctrl_lli_last = 0 |
 995                                 COH901318_CX_CTRL_TC_ENABLE |
 996                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 997                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 998                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 999                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1000                                 COH901318_CX_CTRL_TCP_DISABLE |
1001                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1002                                 COH901318_CX_CTRL_HSP_ENABLE |
1003                                 COH901318_CX_CTRL_HSS_DISABLE |
1004                                 COH901318_CX_CTRL_DDMA_LEGACY,
1005
1006         },
1007         {
1008                 .number = U300_DMA_MSPRO_TX,
1009                 .name = "MSPRO TX",
1010                 .priority_high = 0,
1011         },
1012         {
1013                 .number = U300_DMA_MSPRO_RX,
1014                 .name = "MSPRO RX",
1015                 .priority_high = 0,
1016         },
1017         {
1018                 .number = U300_DMA_UART0_TX,
1019                 .name = "UART0 TX",
1020                 .priority_high = 0,
1021         },
1022         {
1023                 .number = U300_DMA_UART0_RX,
1024                 .name = "UART0 RX",
1025                 .priority_high = 0,
1026         },
1027         {
1028                 .number = U300_DMA_APEX_TX,
1029                 .name = "APEX TX",
1030                 .priority_high = 0,
1031         },
1032         {
1033                 .number = U300_DMA_APEX_RX,
1034                 .name = "APEX RX",
1035                 .priority_high = 0,
1036         },
1037         {
1038                 .number = U300_DMA_PCM_I2S0_TX,
1039                 .name = "PCM I2S0 TX",
1040                 .priority_high = 1,
1041                 .dev_addr = U300_PCM_I2S0_BASE + 0x14,
1042                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1043                                 COH901318_CX_CFG_LCR_DISABLE |
1044                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1045                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1046                 .param.ctrl_lli_chained = 0 |
1047                                 COH901318_CX_CTRL_TC_ENABLE |
1048                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1049                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1050                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1051                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1052                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1053                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1054                                 COH901318_CX_CTRL_TCP_DISABLE |
1055                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1056                                 COH901318_CX_CTRL_HSP_ENABLE |
1057                                 COH901318_CX_CTRL_HSS_DISABLE |
1058                                 COH901318_CX_CTRL_DDMA_LEGACY |
1059                                 COH901318_CX_CTRL_PRDD_SOURCE,
1060                 .param.ctrl_lli = 0 |
1061                                 COH901318_CX_CTRL_TC_ENABLE |
1062                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1063                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1064                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1065                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1066                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1067                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1068                                 COH901318_CX_CTRL_TCP_ENABLE |
1069                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1070                                 COH901318_CX_CTRL_HSP_ENABLE |
1071                                 COH901318_CX_CTRL_HSS_DISABLE |
1072                                 COH901318_CX_CTRL_DDMA_LEGACY |
1073                                 COH901318_CX_CTRL_PRDD_SOURCE,
1074                 .param.ctrl_lli_last = 0 |
1075                                 COH901318_CX_CTRL_TC_ENABLE |
1076                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1077                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1078                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1079                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1080                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1081                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1082                                 COH901318_CX_CTRL_TCP_ENABLE |
1083                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1084                                 COH901318_CX_CTRL_HSP_ENABLE |
1085                                 COH901318_CX_CTRL_HSS_DISABLE |
1086                                 COH901318_CX_CTRL_DDMA_LEGACY |
1087                                 COH901318_CX_CTRL_PRDD_SOURCE,
1088         },
1089         {
1090                 .number = U300_DMA_PCM_I2S0_RX,
1091                 .name = "PCM I2S0 RX",
1092                 .priority_high = 1,
1093                 .dev_addr = U300_PCM_I2S0_BASE + 0x10,
1094                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1095                                 COH901318_CX_CFG_LCR_DISABLE |
1096                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1097                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1098                 .param.ctrl_lli_chained = 0 |
1099                                 COH901318_CX_CTRL_TC_ENABLE |
1100                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1101                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1102                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1103                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1104                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1105                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1106                                 COH901318_CX_CTRL_TCP_DISABLE |
1107                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1108                                 COH901318_CX_CTRL_HSP_ENABLE |
1109                                 COH901318_CX_CTRL_HSS_DISABLE |
1110                                 COH901318_CX_CTRL_DDMA_LEGACY |
1111                                 COH901318_CX_CTRL_PRDD_DEST,
1112                 .param.ctrl_lli = 0 |
1113                                 COH901318_CX_CTRL_TC_ENABLE |
1114                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1115                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1116                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1117                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1118                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1119                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1120                                 COH901318_CX_CTRL_TCP_ENABLE |
1121                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1122                                 COH901318_CX_CTRL_HSP_ENABLE |
1123                                 COH901318_CX_CTRL_HSS_DISABLE |
1124                                 COH901318_CX_CTRL_DDMA_LEGACY |
1125                                 COH901318_CX_CTRL_PRDD_DEST,
1126                 .param.ctrl_lli_last = 0 |
1127                                 COH901318_CX_CTRL_TC_ENABLE |
1128                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1129                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1130                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1131                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1132                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1133                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1134                                 COH901318_CX_CTRL_TCP_ENABLE |
1135                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1136                                 COH901318_CX_CTRL_HSP_ENABLE |
1137                                 COH901318_CX_CTRL_HSS_DISABLE |
1138                                 COH901318_CX_CTRL_DDMA_LEGACY |
1139                                 COH901318_CX_CTRL_PRDD_DEST,
1140         },
1141         {
1142                 .number = U300_DMA_PCM_I2S1_TX,
1143                 .name = "PCM I2S1 TX",
1144                 .priority_high = 1,
1145                 .dev_addr =  U300_PCM_I2S1_BASE + 0x14,
1146                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1147                                 COH901318_CX_CFG_LCR_DISABLE |
1148                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1149                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1150                 .param.ctrl_lli_chained = 0 |
1151                                 COH901318_CX_CTRL_TC_ENABLE |
1152                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1153                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1154                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1155                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1156                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1157                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1158                                 COH901318_CX_CTRL_TCP_DISABLE |
1159                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1160                                 COH901318_CX_CTRL_HSP_ENABLE |
1161                                 COH901318_CX_CTRL_HSS_DISABLE |
1162                                 COH901318_CX_CTRL_DDMA_LEGACY |
1163                                 COH901318_CX_CTRL_PRDD_SOURCE,
1164                 .param.ctrl_lli = 0 |
1165                                 COH901318_CX_CTRL_TC_ENABLE |
1166                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1167                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1168                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1169                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1170                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1171                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1172                                 COH901318_CX_CTRL_TCP_ENABLE |
1173                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1174                                 COH901318_CX_CTRL_HSP_ENABLE |
1175                                 COH901318_CX_CTRL_HSS_DISABLE |
1176                                 COH901318_CX_CTRL_DDMA_LEGACY |
1177                                 COH901318_CX_CTRL_PRDD_SOURCE,
1178                 .param.ctrl_lli_last = 0 |
1179                                 COH901318_CX_CTRL_TC_ENABLE |
1180                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1181                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1182                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1183                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1184                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1185                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1186                                 COH901318_CX_CTRL_TCP_ENABLE |
1187                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1188                                 COH901318_CX_CTRL_HSP_ENABLE |
1189                                 COH901318_CX_CTRL_HSS_DISABLE |
1190                                 COH901318_CX_CTRL_DDMA_LEGACY |
1191                                 COH901318_CX_CTRL_PRDD_SOURCE,
1192         },
1193         {
1194                 .number = U300_DMA_PCM_I2S1_RX,
1195                 .name = "PCM I2S1 RX",
1196                 .priority_high = 1,
1197                 .dev_addr = U300_PCM_I2S1_BASE + 0x10,
1198                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1199                                 COH901318_CX_CFG_LCR_DISABLE |
1200                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1201                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1202                 .param.ctrl_lli_chained = 0 |
1203                                 COH901318_CX_CTRL_TC_ENABLE |
1204                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1205                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1206                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1207                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1208                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1209                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1210                                 COH901318_CX_CTRL_TCP_DISABLE |
1211                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1212                                 COH901318_CX_CTRL_HSP_ENABLE |
1213                                 COH901318_CX_CTRL_HSS_DISABLE |
1214                                 COH901318_CX_CTRL_DDMA_LEGACY |
1215                                 COH901318_CX_CTRL_PRDD_DEST,
1216                 .param.ctrl_lli = 0 |
1217                                 COH901318_CX_CTRL_TC_ENABLE |
1218                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1219                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1220                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1221                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1222                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1223                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1224                                 COH901318_CX_CTRL_TCP_ENABLE |
1225                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1226                                 COH901318_CX_CTRL_HSP_ENABLE |
1227                                 COH901318_CX_CTRL_HSS_DISABLE |
1228                                 COH901318_CX_CTRL_DDMA_LEGACY |
1229                                 COH901318_CX_CTRL_PRDD_DEST,
1230                 .param.ctrl_lli_last = 0 |
1231                                 COH901318_CX_CTRL_TC_ENABLE |
1232                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1233                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1234                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1235                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1236                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1237                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1238                                 COH901318_CX_CTRL_TCP_ENABLE |
1239                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1240                                 COH901318_CX_CTRL_HSP_ENABLE |
1241                                 COH901318_CX_CTRL_HSS_DISABLE |
1242                                 COH901318_CX_CTRL_DDMA_LEGACY |
1243                                 COH901318_CX_CTRL_PRDD_DEST,
1244         },
1245         {
1246                 .number = U300_DMA_XGAM_CDI,
1247                 .name = "XGAM CDI",
1248                 .priority_high = 0,
1249         },
1250         {
1251                 .number = U300_DMA_XGAM_PDI,
1252                 .name = "XGAM PDI",
1253                 .priority_high = 0,
1254         },
1255         {
1256                 .number = U300_DMA_SPI_TX,
1257                 .name = "SPI TX",
1258                 .priority_high = 0,
1259         },
1260         {
1261                 .number = U300_DMA_SPI_RX,
1262                 .name = "SPI RX",
1263                 .priority_high = 0,
1264         },
1265         {
1266                 .number = U300_DMA_GENERAL_PURPOSE_0,
1267                 .name = "GENERAL 00",
1268                 .priority_high = 0,
1269
1270                 .param.config = flags_memcpy_config,
1271                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1272                 .param.ctrl_lli = flags_memcpy_lli,
1273                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1274         },
1275         {
1276                 .number = U300_DMA_GENERAL_PURPOSE_1,
1277                 .name = "GENERAL 01",
1278                 .priority_high = 0,
1279
1280                 .param.config = flags_memcpy_config,
1281                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1282                 .param.ctrl_lli = flags_memcpy_lli,
1283                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1284         },
1285         {
1286                 .number = U300_DMA_GENERAL_PURPOSE_2,
1287                 .name = "GENERAL 02",
1288                 .priority_high = 0,
1289
1290                 .param.config = flags_memcpy_config,
1291                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1292                 .param.ctrl_lli = flags_memcpy_lli,
1293                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1294         },
1295         {
1296                 .number = U300_DMA_GENERAL_PURPOSE_3,
1297                 .name = "GENERAL 03",
1298                 .priority_high = 0,
1299
1300                 .param.config = flags_memcpy_config,
1301                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1302                 .param.ctrl_lli = flags_memcpy_lli,
1303                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1304         },
1305         {
1306                 .number = U300_DMA_GENERAL_PURPOSE_4,
1307                 .name = "GENERAL 04",
1308                 .priority_high = 0,
1309
1310                 .param.config = flags_memcpy_config,
1311                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1312                 .param.ctrl_lli = flags_memcpy_lli,
1313                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1314         },
1315         {
1316                 .number = U300_DMA_GENERAL_PURPOSE_5,
1317                 .name = "GENERAL 05",
1318                 .priority_high = 0,
1319
1320                 .param.config = flags_memcpy_config,
1321                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1322                 .param.ctrl_lli = flags_memcpy_lli,
1323                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1324         },
1325         {
1326                 .number = U300_DMA_GENERAL_PURPOSE_6,
1327                 .name = "GENERAL 06",
1328                 .priority_high = 0,
1329
1330                 .param.config = flags_memcpy_config,
1331                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1332                 .param.ctrl_lli = flags_memcpy_lli,
1333                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1334         },
1335         {
1336                 .number = U300_DMA_GENERAL_PURPOSE_7,
1337                 .name = "GENERAL 07",
1338                 .priority_high = 0,
1339
1340                 .param.config = flags_memcpy_config,
1341                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1342                 .param.ctrl_lli = flags_memcpy_lli,
1343                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1344         },
1345         {
1346                 .number = U300_DMA_GENERAL_PURPOSE_8,
1347                 .name = "GENERAL 08",
1348                 .priority_high = 0,
1349
1350                 .param.config = flags_memcpy_config,
1351                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1352                 .param.ctrl_lli = flags_memcpy_lli,
1353                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1354         },
1355 #ifdef CONFIG_MACH_U300_BS335
1356         {
1357                 .number = U300_DMA_UART1_TX,
1358                 .name = "UART1 TX",
1359                 .priority_high = 0,
1360         },
1361         {
1362                 .number = U300_DMA_UART1_RX,
1363                 .name = "UART1 RX",
1364                 .priority_high = 0,
1365         }
1366 #else
1367         {
1368                 .number = U300_DMA_GENERAL_PURPOSE_9,
1369                 .name = "GENERAL 09",
1370                 .priority_high = 0,
1371
1372                 .param.config = flags_memcpy_config,
1373                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1374                 .param.ctrl_lli = flags_memcpy_lli,
1375                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1376         },
1377         {
1378                 .number = U300_DMA_GENERAL_PURPOSE_10,
1379                 .name = "GENERAL 10",
1380                 .priority_high = 0,
1381
1382                 .param.config = flags_memcpy_config,
1383                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1384                 .param.ctrl_lli = flags_memcpy_lli,
1385                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1386         }
1387 #endif
1388 };
1389
1390
1391 static struct coh901318_platform coh901318_platform = {
1392         .chans_slave = dma_slave_channels,
1393         .chans_memcpy = dma_memcpy_channels,
1394         .access_memory_state = coh901318_access_memory_state,
1395         .chan_conf = chan_config,
1396         .max_channels = U300_DMA_CHANNELS,
1397 };
1398
1399 static struct platform_device wdog_device = {
1400         .name = "coh901327_wdog",
1401         .id = -1,
1402         .num_resources = ARRAY_SIZE(wdog_resources),
1403         .resource = wdog_resources,
1404 };
1405
1406 static struct platform_device i2c0_device = {
1407         .name = "stu300",
1408         .id = 0,
1409         .num_resources = ARRAY_SIZE(i2c0_resources),
1410         .resource = i2c0_resources,
1411 };
1412
1413 static struct platform_device i2c1_device = {
1414         .name = "stu300",
1415         .id = 1,
1416         .num_resources = ARRAY_SIZE(i2c1_resources),
1417         .resource = i2c1_resources,
1418 };
1419
1420 static struct platform_device gpio_device = {
1421         .name = "u300-gpio",
1422         .id = -1,
1423         .num_resources = ARRAY_SIZE(gpio_resources),
1424         .resource = gpio_resources,
1425 };
1426
1427 static struct platform_device keypad_device = {
1428         .name = "keypad",
1429         .id = -1,
1430         .num_resources = ARRAY_SIZE(keypad_resources),
1431         .resource = keypad_resources,
1432 };
1433
1434 static struct platform_device rtc_device = {
1435         .name = "rtc-coh901331",
1436         .id = -1,
1437         .num_resources = ARRAY_SIZE(rtc_resources),
1438         .resource = rtc_resources,
1439 };
1440
1441 static struct mtd_partition u300_partitions[] = {
1442         {
1443                 .name = "bootrecords",
1444                 .offset = 0,
1445                 .size = SZ_128K,
1446         },
1447         {
1448                 .name = "free",
1449                 .offset = SZ_128K,
1450                 .size = 8064 * SZ_1K,
1451         },
1452         {
1453                 .name = "platform",
1454                 .offset = 8192 * SZ_1K,
1455                 .size = 253952 * SZ_1K,
1456         },
1457 };
1458
1459 static struct fsmc_nand_platform_data nand_platform_data = {
1460         .partitions = u300_partitions,
1461         .nr_partitions = ARRAY_SIZE(u300_partitions),
1462         .options = NAND_SKIP_BBTSCAN,
1463         .width = FSMC_NAND_BW8,
1464 };
1465
1466 static struct platform_device nand_device = {
1467         .name = "fsmc-nand",
1468         .id = -1,
1469         .resource = fsmc_resources,
1470         .num_resources = ARRAY_SIZE(fsmc_resources),
1471         .dev = {
1472                 .platform_data = &nand_platform_data,
1473         },
1474 };
1475
1476 static struct platform_device ave_device = {
1477         .name = "video_enc",
1478         .id = -1,
1479         .num_resources = ARRAY_SIZE(ave_resources),
1480         .resource = ave_resources,
1481 };
1482
1483 static struct platform_device dma_device = {
1484         .name           = "coh901318",
1485         .id             = -1,
1486         .resource       = dma_resource,
1487         .num_resources  = ARRAY_SIZE(dma_resource),
1488         .dev = {
1489                 .platform_data = &coh901318_platform,
1490                 .coherent_dma_mask = ~0,
1491         },
1492 };
1493
1494 /*
1495  * Notice that AMBA devices are initialized before platform devices.
1496  *
1497  */
1498 static struct platform_device *platform_devs[] __initdata = {
1499         &dma_device,
1500         &i2c0_device,
1501         &i2c1_device,
1502         &keypad_device,
1503         &rtc_device,
1504         &gpio_device,
1505         &nand_device,
1506         &wdog_device,
1507         &ave_device
1508 };
1509
1510
1511 /*
1512  * Interrupts: the U300 platforms have two pl190 ARM PrimeCells connected
1513  * together so some interrupts are connected to the first one and some
1514  * to the second one.
1515  */
1516 void __init u300_init_irq(void)
1517 {
1518         u32 mask[2] = {0, 0};
1519         struct clk *clk;
1520         int i;
1521
1522         /* initialize clocking early, we want to clock the INTCON */
1523         u300_clock_init();
1524
1525         /* Clock the interrupt controller */
1526         clk = clk_get_sys("intcon", NULL);
1527         BUG_ON(IS_ERR(clk));
1528         clk_enable(clk);
1529
1530         for (i = 0; i < NR_IRQS; i++)
1531                 set_bit(i, (unsigned long *) &mask[0]);
1532         vic_init((void __iomem *) U300_INTCON0_VBASE, 0, mask[0], mask[0]);
1533         vic_init((void __iomem *) U300_INTCON1_VBASE, 32, mask[1], mask[1]);
1534 }
1535
1536
1537 /*
1538  * U300 platforms peripheral handling
1539  */
1540 struct db_chip {
1541         u16 chipid;
1542         const char *name;
1543 };
1544
1545 /*
1546  * This is a list of the Digital Baseband chips used in the U300 platform.
1547  */
1548 static struct db_chip db_chips[] __initdata = {
1549         {
1550                 .chipid = 0xb800,
1551                 .name = "DB3000",
1552         },
1553         {
1554                 .chipid = 0xc000,
1555                 .name = "DB3100",
1556         },
1557         {
1558                 .chipid = 0xc800,
1559                 .name = "DB3150",
1560         },
1561         {
1562                 .chipid = 0xd800,
1563                 .name = "DB3200",
1564         },
1565         {
1566                 .chipid = 0xe000,
1567                 .name = "DB3250",
1568         },
1569         {
1570                 .chipid = 0xe800,
1571                 .name = "DB3210",
1572         },
1573         {
1574                 .chipid = 0xf000,
1575                 .name = "DB3350 P1x",
1576         },
1577         {
1578                 .chipid = 0xf100,
1579                 .name = "DB3350 P2x",
1580         },
1581         {
1582                 .chipid = 0x0000, /* List terminator */
1583                 .name = NULL,
1584         }
1585 };
1586
1587 static void __init u300_init_check_chip(void)
1588 {
1589
1590         u16 val;
1591         struct db_chip *chip;
1592         const char *chipname;
1593         const char unknown[] = "UNKNOWN";
1594
1595         /* Read out and print chip ID */
1596         val = readw(U300_SYSCON_VBASE + U300_SYSCON_CIDR);
1597         /* This is in funky bigendian order... */
1598         val = (val & 0xFFU) << 8 | (val >> 8);
1599         chip = db_chips;
1600         chipname = unknown;
1601
1602         for ( ; chip->chipid; chip++) {
1603                 if (chip->chipid == (val & 0xFF00U)) {
1604                         chipname = chip->name;
1605                         break;
1606                 }
1607         }
1608         printk(KERN_INFO "Initializing U300 system on %s baseband chip " \
1609                "(chip ID 0x%04x)\n", chipname, val);
1610
1611 #ifdef CONFIG_MACH_U300_BS330
1612         if ((val & 0xFF00U) != 0xd800) {
1613                 printk(KERN_ERR "Platform configured for BS330 " \
1614                        "with DB3200 but %s detected, expect problems!",
1615                        chipname);
1616         }
1617 #endif
1618 #ifdef CONFIG_MACH_U300_BS335
1619         if ((val & 0xFF00U) != 0xf000 && (val & 0xFF00U) != 0xf100) {
1620                 printk(KERN_ERR "Platform configured for BS365 " \
1621                        " with DB3350 but %s detected, expect problems!",
1622                        chipname);
1623         }
1624 #endif
1625 #ifdef CONFIG_MACH_U300_BS365
1626         if ((val & 0xFF00U) != 0xe800) {
1627                 printk(KERN_ERR "Platform configured for BS365 " \
1628                        "with DB3210 but %s detected, expect problems!",
1629                        chipname);
1630         }
1631 #endif
1632
1633
1634 }
1635
1636 /*
1637  * Some devices and their resources require reserved physical memory from
1638  * the end of the available RAM. This function traverses the list of devices
1639  * and assigns actual addresses to these.
1640  */
1641 static void __init u300_assign_physmem(void)
1642 {
1643         unsigned long curr_start = __pa(high_memory);
1644         int i, j;
1645
1646         for (i = 0; i < ARRAY_SIZE(platform_devs); i++) {
1647                 for (j = 0; j < platform_devs[i]->num_resources; j++) {
1648                         struct resource *const res =
1649                           &platform_devs[i]->resource[j];
1650
1651                         if (IORESOURCE_MEM == res->flags &&
1652                                      0 == res->start) {
1653                                 res->start  = curr_start;
1654                                 res->end   += curr_start;
1655                                 curr_start += (res->end - res->start + 1);
1656
1657                                 printk(KERN_INFO "core.c: Mapping RAM " \
1658                                        "%#x-%#x to device %s:%s\n",
1659                                         res->start, res->end,
1660                                        platform_devs[i]->name, res->name);
1661                         }
1662                 }
1663         }
1664 }
1665
1666 void __init u300_init_devices(void)
1667 {
1668         int i;
1669         u16 val;
1670
1671         /* Check what platform we run and print some status information */
1672         u300_init_check_chip();
1673
1674         /* Set system to run at PLL208, max performance, a known state. */
1675         val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
1676         val &= ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
1677         writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
1678         /* Wait for the PLL208 to lock if not locked in yet */
1679         while (!(readw(U300_SYSCON_VBASE + U300_SYSCON_CSR) &
1680                  U300_SYSCON_CSR_PLL208_LOCK_IND));
1681         /* Initialize SPI device with some board specifics */
1682         u300_spi_init(&pl022_device);
1683
1684         /* Register the AMBA devices in the AMBA bus abstraction layer */
1685         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
1686                 struct amba_device *d = amba_devs[i];
1687                 amba_device_register(d, &iomem_resource);
1688         }
1689
1690         u300_assign_physmem();
1691
1692         /* Register subdevices on the I2C buses */
1693         u300_i2c_register_board_devices();
1694
1695         /* Register subdevices on the SPI bus */
1696         u300_spi_register_board_devices();
1697
1698         /* Register the platform devices */
1699         platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
1700
1701 #ifndef CONFIG_MACH_U300_SEMI_IS_SHARED
1702         /*
1703          * Enable SEMI self refresh. Self-refresh of the SDRAM is entered when
1704          * both subsystems are requesting this mode.
1705          * If we not share the Acc SDRAM, this is never the case. Therefore
1706          * enable it here from the App side.
1707          */
1708         val = readw(U300_SYSCON_VBASE + U300_SYSCON_SMCR) |
1709                 U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE;
1710         writew(val, U300_SYSCON_VBASE + U300_SYSCON_SMCR);
1711 #endif /* CONFIG_MACH_U300_SEMI_IS_SHARED */
1712 }
1713
1714 static int core_module_init(void)
1715 {
1716         /*
1717          * This needs to be initialized later: it needs the input framework
1718          * to be initialized first.
1719          */
1720         return mmc_init(&mmcsd_device);
1721 }
1722 module_init(core_module_init);