arch/arm/mach-u300/core.c

   1 /*
   2  *
   3  * arch/arm/mach-u300/core.c
   4  *
   5  *
   6  * Copyright (C) 2007-2010 ST-Ericsson SA
   7  * License terms: GNU General Public License (GPL) version 2
   8  * Core platform support, IRQ handling and device definitions.
   9  * Author: Linus Walleij <linus.walleij@stericsson.com>
  10  */
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/spinlock.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/bitops.h>
  16 #include <linux/device.h>
  17 #include <linux/mm.h>
  18 #include <linux/termios.h>
  19 #include <linux/dmaengine.h>
  20 #include <linux/amba/bus.h>
  21 #include <linux/amba/serial.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/gpio.h>
  24 #include <linux/clk.h>
  25 #include <linux/err.h>
  26 #include <linux/mtd/nand.h>
  27 #include <linux/mtd/fsmc.h>
  28
  29 #include <asm/types.h>
  30 #include <asm/setup.h>
  31 #include <asm/memory.h>
  32 #include <asm/hardware/vic.h>
  33 #include <asm/mach/map.h>
  34 #include <asm/mach/irq.h>
  35
  36 #include <mach/coh901318.h>
  37 #include <mach/hardware.h>
  38 #include <mach/syscon.h>
  39 #include <mach/dma_channels.h>
  40
  41 #include "clock.h"
  42 #include "mmc.h"
  43 #include "spi.h"
  44 #include "i2c.h"
  45
  46 /*
  47  * Static I/O mappings that are needed for booting the U300 platforms. The
  48  * only things we need are the areas where we find the timer, syscon and
  49  * intcon, since the remaining device drivers will map their own memory
  50  * physical to virtual as the need arise.
  51  */
  52 static struct map_desc u300_io_desc[] __initdata = {
  53         {
  54                 .virtual        = U300_SLOW_PER_VIRT_BASE,
  55                 .pfn            = __phys_to_pfn(U300_SLOW_PER_PHYS_BASE),
  56                 .length         = SZ_64K,
  57                 .type           = MT_DEVICE,
  58         },
  59         {
  60                 .virtual        = U300_AHB_PER_VIRT_BASE,
  61                 .pfn            = __phys_to_pfn(U300_AHB_PER_PHYS_BASE),
  62                 .length         = SZ_32K,
  63                 .type           = MT_DEVICE,
  64         },
  65         {
  66                 .virtual        = U300_FAST_PER_VIRT_BASE,
  67                 .pfn            = __phys_to_pfn(U300_FAST_PER_PHYS_BASE),
  68                 .length         = SZ_32K,
  69                 .type           = MT_DEVICE,
  70         },
  71         {
  72                 .virtual        = 0xffff2000, /* TCM memory */
  73                 .pfn            = __phys_to_pfn(0xffff2000),
  74                 .length         = SZ_16K,
  75                 .type           = MT_DEVICE,
  76         },
  77
  78         /*
  79          * This overlaps with the IRQ vectors etc at 0xffff0000, so these
  80          * may have to be moved to 0x00000000 in order to use the ROM.
  81          */
  82         /*
  83         {
  84                 .virtual        = U300_BOOTROM_VIRT_BASE,
  85                 .pfn            = __phys_to_pfn(U300_BOOTROM_PHYS_BASE),
  86                 .length         = SZ_64K,
  87                 .type           = MT_ROM,
  88         },
  89         */
  90 };
  91
  92 void __init u300_map_io(void)
  93 {
  94         iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc));
  95 }
  96
  97 /*
  98  * Declaration of devices found on the U300 board and
  99  * their respective memory locations.
 100  */
 101
 102 static struct amba_pl011_data uart0_plat_data = {
 103 #ifdef CONFIG_COH901318
 104         .dma_filter = coh901318_filter_id,
 105         .dma_rx_param = (void *) U300_DMA_UART0_RX,
 106         .dma_tx_param = (void *) U300_DMA_UART0_TX,
 107 #endif
 108 };
 109
 110 static struct amba_device uart0_device = {
 111         .dev = {
 112                 .coherent_dma_mask = ~0,
 113                 .init_name = "uart0", /* Slow device at 0x3000 offset */
 114                 .platform_data = &uart0_plat_data,
 115         },
 116         .res = {
 117                 .start = U300_UART0_BASE,
 118                 .end   = U300_UART0_BASE + SZ_4K - 1,
 119                 .flags = IORESOURCE_MEM,
 120         },
 121         .irq = { IRQ_U300_UART0, NO_IRQ },
 122 };
 123
 124 /* The U335 have an additional UART1 on the APP CPU */
 125 #ifdef CONFIG_MACH_U300_BS335
 126 static struct amba_pl011_data uart1_plat_data = {
 127 #ifdef CONFIG_COH901318
 128         .dma_filter = coh901318_filter_id,
 129         .dma_rx_param = (void *) U300_DMA_UART1_RX,
 130         .dma_tx_param = (void *) U300_DMA_UART1_TX,
 131 #endif
 132 };
 133
 134 static struct amba_device uart1_device = {
 135         .dev = {
 136                 .coherent_dma_mask = ~0,
 137                 .init_name = "uart1", /* Fast device at 0x7000 offset */
 138                 .platform_data = &uart1_plat_data,
 139         },
 140         .res = {
 141                 .start = U300_UART1_BASE,
 142                 .end   = U300_UART1_BASE + SZ_4K - 1,
 143                 .flags = IORESOURCE_MEM,
 144         },
 145         .irq = { IRQ_U300_UART1, NO_IRQ },
 146 };
 147 #endif
 148
 149 static struct amba_device pl172_device = {
 150         .dev = {
 151                 .init_name = "pl172", /* AHB device at 0x4000 offset */
 152                 .platform_data = NULL,
 153         },
 154         .res = {
 155                 .start = U300_EMIF_CFG_BASE,
 156                 .end   = U300_EMIF_CFG_BASE + SZ_4K - 1,
 157                 .flags = IORESOURCE_MEM,
 158         },
 159 };
 160
 161
 162 /*
 163  * Everything within this next ifdef deals with external devices connected to
 164  * the APP SPI bus.
 165  */
 166 static struct amba_device pl022_device = {
 167         .dev = {
 168                 .coherent_dma_mask = ~0,
 169                 .init_name = "pl022", /* Fast device at 0x6000 offset */
 170         },
 171         .res = {
 172                 .start = U300_SPI_BASE,
 173                 .end   = U300_SPI_BASE + SZ_4K - 1,
 174                 .flags = IORESOURCE_MEM,
 175         },
 176         .irq = {IRQ_U300_SPI, NO_IRQ },
 177         /*
 178          * This device has a DMA channel but the Linux driver does not use
 179          * it currently.
 180          */
 181 };
 182
 183 static struct amba_device mmcsd_device = {
 184         .dev = {
 185                 .init_name = "mmci", /* Fast device at 0x1000 offset */
 186                 .platform_data = NULL, /* Added later */
 187         },
 188         .res = {
 189                 .start = U300_MMCSD_BASE,
 190                 .end   = U300_MMCSD_BASE + SZ_4K - 1,
 191                 .flags = IORESOURCE_MEM,
 192         },
 193         .irq = {IRQ_U300_MMCSD_MCIINTR0, IRQ_U300_MMCSD_MCIINTR1 },
 194         /*
 195          * This device has a DMA channel but the Linux driver does not use
 196          * it currently.
 197          */
 198 };
 199
 200 /*
 201  * The order of device declaration may be important, since some devices
 202  * have dependencies on other devices being initialized first.
 203  */
 204 static struct amba_device *amba_devs[] __initdata = {
 205         &uart0_device,
 206 #ifdef CONFIG_MACH_U300_BS335
 207         &uart1_device,
 208 #endif
 209         &pl022_device,
 210         &pl172_device,
 211         &mmcsd_device,
 212 };
 213
 214 /* Here follows a list of all hw resources that the platform devices
 215  * allocate. Note, clock dependencies are not included
 216  */
 217
 218 static struct resource gpio_resources[] = {
 219         {
 220                 .start = U300_GPIO_BASE,
 221                 .end   = (U300_GPIO_BASE + SZ_4K - 1),
 222                 .flags = IORESOURCE_MEM,
 223         },
 224         {
 225                 .name  = "gpio0",
 226                 .start = IRQ_U300_GPIO_PORT0,
 227                 .end   = IRQ_U300_GPIO_PORT0,
 228                 .flags = IORESOURCE_IRQ,
 229         },
 230         {
 231                 .name  = "gpio1",
 232                 .start = IRQ_U300_GPIO_PORT1,
 233                 .end   = IRQ_U300_GPIO_PORT1,
 234                 .flags = IORESOURCE_IRQ,
 235         },
 236         {
 237                 .name  = "gpio2",
 238                 .start = IRQ_U300_GPIO_PORT2,
 239                 .end   = IRQ_U300_GPIO_PORT2,
 240                 .flags = IORESOURCE_IRQ,
 241         },
 242 #ifdef U300_COH901571_3
 243         {
 244                 .name  = "gpio3",
 245                 .start = IRQ_U300_GPIO_PORT3,
 246                 .end   = IRQ_U300_GPIO_PORT3,
 247                 .flags = IORESOURCE_IRQ,
 248         },
 249         {
 250                 .name  = "gpio4",
 251                 .start = IRQ_U300_GPIO_PORT4,
 252                 .end   = IRQ_U300_GPIO_PORT4,
 253                 .flags = IORESOURCE_IRQ,
 254         },
 255 #ifdef CONFIG_MACH_U300_BS335
 256         {
 257                 .name  = "gpio5",
 258                 .start = IRQ_U300_GPIO_PORT5,
 259                 .end   = IRQ_U300_GPIO_PORT5,
 260                 .flags = IORESOURCE_IRQ,
 261         },
 262         {
 263                 .name  = "gpio6",
 264                 .start = IRQ_U300_GPIO_PORT6,
 265                 .end   = IRQ_U300_GPIO_PORT6,
 266                 .flags = IORESOURCE_IRQ,
 267         },
 268 #endif /* CONFIG_MACH_U300_BS335 */
 269 #endif /* U300_COH901571_3 */
 270 };
 271
 272 static struct resource keypad_resources[] = {
 273         {
 274                 .start = U300_KEYPAD_BASE,
 275                 .end   = U300_KEYPAD_BASE + SZ_4K - 1,
 276                 .flags = IORESOURCE_MEM,
 277         },
 278         {
 279                 .name  = "coh901461-press",
 280                 .start = IRQ_U300_KEYPAD_KEYBF,
 281                 .end   = IRQ_U300_KEYPAD_KEYBF,
 282                 .flags = IORESOURCE_IRQ,
 283         },
 284         {
 285                 .name  = "coh901461-release",
 286                 .start = IRQ_U300_KEYPAD_KEYBR,
 287                 .end   = IRQ_U300_KEYPAD_KEYBR,
 288                 .flags = IORESOURCE_IRQ,
 289         },
 290 };
 291
 292 static struct resource rtc_resources[] = {
 293         {
 294                 .start = U300_RTC_BASE,
 295                 .end   = U300_RTC_BASE + SZ_4K - 1,
 296                 .flags = IORESOURCE_MEM,
 297         },
 298         {
 299                 .start = IRQ_U300_RTC,
 300                 .end   = IRQ_U300_RTC,
 301                 .flags = IORESOURCE_IRQ,
 302         },
 303 };
 304
 305 /*
 306  * Fsmc does have IRQs: #43 and #44 (NFIF and NFIF2)
 307  * but these are not yet used by the driver.
 308  */
 309 static struct resource fsmc_resources[] = {
 310         {
 311                 .name  = "nand_data",
 312                 .start = U300_NAND_CS0_PHYS_BASE,
 313                 .end   = U300_NAND_CS0_PHYS_BASE + SZ_16K - 1,
 314                 .flags = IORESOURCE_MEM,
 315         },
 316         {
 317                 .name  = "fsmc_regs",
 318                 .start = U300_NAND_IF_PHYS_BASE,
 319                 .end   = U300_NAND_IF_PHYS_BASE + SZ_4K - 1,
 320                 .flags = IORESOURCE_MEM,
 321         },
 322 };
 323
 324 static struct resource i2c0_resources[] = {
 325         {
 326                 .start = U300_I2C0_BASE,
 327                 .end   = U300_I2C0_BASE + SZ_4K - 1,
 328                 .flags = IORESOURCE_MEM,
 329         },
 330         {
 331                 .start = IRQ_U300_I2C0,
 332                 .end   = IRQ_U300_I2C0,
 333                 .flags = IORESOURCE_IRQ,
 334         },
 335 };
 336
 337 static struct resource i2c1_resources[] = {
 338         {
 339                 .start = U300_I2C1_BASE,
 340                 .end   = U300_I2C1_BASE + SZ_4K - 1,
 341                 .flags = IORESOURCE_MEM,
 342         },
 343         {
 344                 .start = IRQ_U300_I2C1,
 345                 .end   = IRQ_U300_I2C1,
 346                 .flags = IORESOURCE_IRQ,
 347         },
 348
 349 };
 350
 351 static struct resource wdog_resources[] = {
 352         {
 353                 .start = U300_WDOG_BASE,
 354                 .end   = U300_WDOG_BASE + SZ_4K - 1,
 355                 .flags = IORESOURCE_MEM,
 356         },
 357         {
 358                 .start = IRQ_U300_WDOG,
 359                 .end   = IRQ_U300_WDOG,
 360                 .flags = IORESOURCE_IRQ,
 361         }
 362 };
 363
 364 /* TODO: These should be protected by suitable #ifdef's */
 365 static struct resource ave_resources[] = {
 366         {
 367                 .name  = "AVE3e I/O Area",
 368                 .start = U300_VIDEOENC_BASE,
 369                 .end   = U300_VIDEOENC_BASE + SZ_512K - 1,
 370                 .flags = IORESOURCE_MEM,
 371         },
 372         {
 373                 .name  = "AVE3e IRQ0",
 374                 .start = IRQ_U300_VIDEO_ENC_0,
 375                 .end   = IRQ_U300_VIDEO_ENC_0,
 376                 .flags = IORESOURCE_IRQ,
 377         },
 378         {
 379                 .name  = "AVE3e IRQ1",
 380                 .start = IRQ_U300_VIDEO_ENC_1,
 381                 .end   = IRQ_U300_VIDEO_ENC_1,
 382                 .flags = IORESOURCE_IRQ,
 383         },
 384         {
 385                 .name  = "AVE3e Physmem Area",
 386                 .start = 0, /* 0 will be remapped to reserved memory */
 387                 .end   = SZ_1M - 1,
 388                 .flags = IORESOURCE_MEM,
 389         },
 390         /*
 391          * The AVE3e requires two regions of 256MB that it considers
 392          * "invisible". The hardware will not be able to access these
 393          * addresses, so they should never point to system RAM.
 394          */
 395         {
 396                 .name  = "AVE3e Reserved 0",
 397                 .start = 0xd0000000,
 398                 .end   = 0xd0000000 + SZ_256M - 1,
 399                 .flags = IORESOURCE_MEM,
 400         },
 401         {
 402                 .name  = "AVE3e Reserved 1",
 403                 .start = 0xe0000000,
 404                 .end   = 0xe0000000 + SZ_256M - 1,
 405                 .flags = IORESOURCE_MEM,
 406         },
 407 };
 408
 409 static struct resource dma_resource[] = {
 410         {
 411                 .start = U300_DMAC_BASE,
 412                 .end = U300_DMAC_BASE + PAGE_SIZE - 1,
 413                 .flags =  IORESOURCE_MEM,
 414         },
 415         {
 416                 .start = IRQ_U300_DMA,
 417                 .end = IRQ_U300_DMA,
 418                 .flags =  IORESOURCE_IRQ,
 419         }
 420 };
 421
 422 #ifdef CONFIG_MACH_U300_BS335
 423 /* points out all dma slave channels.
 424  * Syntax is [A1, B1, A2, B2, .... ,-1,-1]
 425  * Select all channels from A to B, end of list is marked with -1,-1
 426  */
 427 static int dma_slave_channels[] = {
 428         U300_DMA_MSL_TX_0, U300_DMA_SPI_RX,
 429         U300_DMA_UART1_TX, U300_DMA_UART1_RX, -1, -1};
 430
 431 /* points out all dma memcpy channels. */
 432 static int dma_memcpy_channels[] = {
 433         U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1};
 434
 435 #else /* CONFIG_MACH_U300_BS335 */
 436
 437 static int dma_slave_channels[] = {U300_DMA_MSL_TX_0, U300_DMA_SPI_RX, -1, -1};
 438 static int dma_memcpy_channels[] = {
 439         U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_10, -1, -1};
 440
 441 #endif
 442
 443 /** register dma for memory access
 444  *
 445  * active  1 means dma intends to access memory
 446  *         0 means dma wont access memory
 447  */
 448 static void coh901318_access_memory_state(struct device *dev, bool active)
 449 {
 450 }
 451
 452 #define flags_memcpy_config (COH901318_CX_CFG_CH_DISABLE | \
 453                         COH901318_CX_CFG_RM_MEMORY_TO_MEMORY | \
 454                         COH901318_CX_CFG_LCR_DISABLE | \
 455                         COH901318_CX_CFG_TC_IRQ_ENABLE | \
 456                         COH901318_CX_CFG_BE_IRQ_ENABLE)
 457 #define flags_memcpy_lli_chained (COH901318_CX_CTRL_TC_ENABLE | \
 458                         COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
 459                         COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
 460                         COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
 461                         COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
 462                         COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
 463                         COH901318_CX_CTRL_MASTER_MODE_M1RW | \
 464                         COH901318_CX_CTRL_TCP_DISABLE | \
 465                         COH901318_CX_CTRL_TC_IRQ_DISABLE | \
 466                         COH901318_CX_CTRL_HSP_DISABLE | \
 467                         COH901318_CX_CTRL_HSS_DISABLE | \
 468                         COH901318_CX_CTRL_DDMA_LEGACY | \
 469                         COH901318_CX_CTRL_PRDD_SOURCE)
 470 #define flags_memcpy_lli (COH901318_CX_CTRL_TC_ENABLE | \
 471                         COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
 472                         COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
 473                         COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
 474                         COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
 475                         COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
 476                         COH901318_CX_CTRL_MASTER_MODE_M1RW | \
 477                         COH901318_CX_CTRL_TCP_DISABLE | \
 478                         COH901318_CX_CTRL_TC_IRQ_DISABLE | \
 479                         COH901318_CX_CTRL_HSP_DISABLE | \
 480                         COH901318_CX_CTRL_HSS_DISABLE | \
 481                         COH901318_CX_CTRL_DDMA_LEGACY | \
 482                         COH901318_CX_CTRL_PRDD_SOURCE)
 483 #define flags_memcpy_lli_last (COH901318_CX_CTRL_TC_ENABLE | \
 484                         COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
 485                         COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
 486                         COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
 487                         COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
 488                         COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
 489                         COH901318_CX_CTRL_MASTER_MODE_M1RW | \
 490                         COH901318_CX_CTRL_TCP_DISABLE | \
 491                         COH901318_CX_CTRL_TC_IRQ_ENABLE | \
 492                         COH901318_CX_CTRL_HSP_DISABLE | \
 493                         COH901318_CX_CTRL_HSS_DISABLE | \
 494                         COH901318_CX_CTRL_DDMA_LEGACY | \
 495                         COH901318_CX_CTRL_PRDD_SOURCE)
 496
 497 const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
 498         {
 499                 .number = U300_DMA_MSL_TX_0,
 500                 .name = "MSL TX 0",
 501                 .priority_high = 0,
 502                 .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x20,
 503         },
 504         {
 505                 .number = U300_DMA_MSL_TX_1,
 506                 .name = "MSL TX 1",
 507                 .priority_high = 0,
 508                 .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x20,
 509                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 510                                 COH901318_CX_CFG_LCR_DISABLE |
 511                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 512                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 513                 .param.ctrl_lli_chained = 0 |
 514                                 COH901318_CX_CTRL_TC_ENABLE |
 515                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 516                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 517                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 518                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 519                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 520                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 521                                 COH901318_CX_CTRL_TCP_DISABLE |
 522                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 523                                 COH901318_CX_CTRL_HSP_ENABLE |
 524                                 COH901318_CX_CTRL_HSS_DISABLE |
 525                                 COH901318_CX_CTRL_DDMA_LEGACY |
 526                                 COH901318_CX_CTRL_PRDD_SOURCE,
 527                 .param.ctrl_lli = 0 |
 528                                 COH901318_CX_CTRL_TC_ENABLE |
 529                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 530                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 531                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 532                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 533                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 534                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 535                                 COH901318_CX_CTRL_TCP_ENABLE |
 536                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 537                                 COH901318_CX_CTRL_HSP_ENABLE |
 538                                 COH901318_CX_CTRL_HSS_DISABLE |
 539                                 COH901318_CX_CTRL_DDMA_LEGACY |
 540                                 COH901318_CX_CTRL_PRDD_SOURCE,
 541                 .param.ctrl_lli_last = 0 |
 542                                 COH901318_CX_CTRL_TC_ENABLE |
 543                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 544                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 545                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 546                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 547                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 548                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 549                                 COH901318_CX_CTRL_TCP_ENABLE |
 550                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 551                                 COH901318_CX_CTRL_HSP_ENABLE |
 552                                 COH901318_CX_CTRL_HSS_DISABLE |
 553                                 COH901318_CX_CTRL_DDMA_LEGACY |
 554                                 COH901318_CX_CTRL_PRDD_SOURCE,
 555         },
 556         {
 557                 .number = U300_DMA_MSL_TX_2,
 558                 .name = "MSL TX 2",
 559                 .priority_high = 0,
 560                 .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x20,
 561                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 562                                 COH901318_CX_CFG_LCR_DISABLE |
 563                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 564                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 565                 .param.ctrl_lli_chained = 0 |
 566                                 COH901318_CX_CTRL_TC_ENABLE |
 567                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 568                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 569                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 570                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 571                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 572                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 573                                 COH901318_CX_CTRL_TCP_DISABLE |
 574                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 575                                 COH901318_CX_CTRL_HSP_ENABLE |
 576                                 COH901318_CX_CTRL_HSS_DISABLE |
 577                                 COH901318_CX_CTRL_DDMA_LEGACY |
 578                                 COH901318_CX_CTRL_PRDD_SOURCE,
 579                 .param.ctrl_lli = 0 |
 580                                 COH901318_CX_CTRL_TC_ENABLE |
 581                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 582                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 583                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 584                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 585                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 586                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 587                                 COH901318_CX_CTRL_TCP_ENABLE |
 588                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 589                                 COH901318_CX_CTRL_HSP_ENABLE |
 590                                 COH901318_CX_CTRL_HSS_DISABLE |
 591                                 COH901318_CX_CTRL_DDMA_LEGACY |
 592                                 COH901318_CX_CTRL_PRDD_SOURCE,
 593                 .param.ctrl_lli_last = 0 |
 594                                 COH901318_CX_CTRL_TC_ENABLE |
 595                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 596                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 597                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 598                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 599                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 600                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 601                                 COH901318_CX_CTRL_TCP_ENABLE |
 602                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 603                                 COH901318_CX_CTRL_HSP_ENABLE |
 604                                 COH901318_CX_CTRL_HSS_DISABLE |
 605                                 COH901318_CX_CTRL_DDMA_LEGACY |
 606                                 COH901318_CX_CTRL_PRDD_SOURCE,
 607                 .desc_nbr_max = 10,
 608         },
 609         {
 610                 .number = U300_DMA_MSL_TX_3,
 611                 .name = "MSL TX 3",
 612                 .priority_high = 0,
 613                 .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x20,
 614                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 615                                 COH901318_CX_CFG_LCR_DISABLE |
 616                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 617                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 618                 .param.ctrl_lli_chained = 0 |
 619                                 COH901318_CX_CTRL_TC_ENABLE |
 620                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 621                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 622                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 623                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 624                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 625                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 626                                 COH901318_CX_CTRL_TCP_DISABLE |
 627                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 628                                 COH901318_CX_CTRL_HSP_ENABLE |
 629                                 COH901318_CX_CTRL_HSS_DISABLE |
 630                                 COH901318_CX_CTRL_DDMA_LEGACY |
 631                                 COH901318_CX_CTRL_PRDD_SOURCE,
 632                 .param.ctrl_lli = 0 |
 633                                 COH901318_CX_CTRL_TC_ENABLE |
 634                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 635                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 636                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 637                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 638                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 639                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 640                                 COH901318_CX_CTRL_TCP_ENABLE |
 641                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 642                                 COH901318_CX_CTRL_HSP_ENABLE |
 643                                 COH901318_CX_CTRL_HSS_DISABLE |
 644                                 COH901318_CX_CTRL_DDMA_LEGACY |
 645                                 COH901318_CX_CTRL_PRDD_SOURCE,
 646                 .param.ctrl_lli_last = 0 |
 647                                 COH901318_CX_CTRL_TC_ENABLE |
 648                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 649                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 650                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 651                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 652                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 653                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 654                                 COH901318_CX_CTRL_TCP_ENABLE |
 655                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 656                                 COH901318_CX_CTRL_HSP_ENABLE |
 657                                 COH901318_CX_CTRL_HSS_DISABLE |
 658                                 COH901318_CX_CTRL_DDMA_LEGACY |
 659                                 COH901318_CX_CTRL_PRDD_SOURCE,
 660         },
 661         {
 662                 .number = U300_DMA_MSL_TX_4,
 663                 .name = "MSL TX 4",
 664                 .priority_high = 0,
 665                 .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x20,
 666                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 667                                 COH901318_CX_CFG_LCR_DISABLE |
 668                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 669                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 670                 .param.ctrl_lli_chained = 0 |
 671                                 COH901318_CX_CTRL_TC_ENABLE |
 672                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 673                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 674                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 675                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 676                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 677                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 678                                 COH901318_CX_CTRL_TCP_DISABLE |
 679                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 680                                 COH901318_CX_CTRL_HSP_ENABLE |
 681                                 COH901318_CX_CTRL_HSS_DISABLE |
 682                                 COH901318_CX_CTRL_DDMA_LEGACY |
 683                                 COH901318_CX_CTRL_PRDD_SOURCE,
 684                 .param.ctrl_lli = 0 |
 685                                 COH901318_CX_CTRL_TC_ENABLE |
 686                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 687                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 688                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 689                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 690                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 691                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 692                                 COH901318_CX_CTRL_TCP_ENABLE |
 693                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 694                                 COH901318_CX_CTRL_HSP_ENABLE |
 695                                 COH901318_CX_CTRL_HSS_DISABLE |
 696                                 COH901318_CX_CTRL_DDMA_LEGACY |
 697                                 COH901318_CX_CTRL_PRDD_SOURCE,
 698                 .param.ctrl_lli_last = 0 |
 699                                 COH901318_CX_CTRL_TC_ENABLE |
 700                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 701                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 702                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 703                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 704                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 705                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 706                                 COH901318_CX_CTRL_TCP_ENABLE |
 707                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 708                                 COH901318_CX_CTRL_HSP_ENABLE |
 709                                 COH901318_CX_CTRL_HSS_DISABLE |
 710                                 COH901318_CX_CTRL_DDMA_LEGACY |
 711                                 COH901318_CX_CTRL_PRDD_SOURCE,
 712         },
 713         {
 714                 .number = U300_DMA_MSL_TX_5,
 715                 .name = "MSL TX 5",
 716                 .priority_high = 0,
 717                 .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x20,
 718         },
 719         {
 720                 .number = U300_DMA_MSL_TX_6,
 721                 .name = "MSL TX 6",
 722                 .priority_high = 0,
 723                 .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x20,
 724         },
 725         {
 726                 .number = U300_DMA_MSL_RX_0,
 727                 .name = "MSL RX 0",
 728                 .priority_high = 0,
 729                 .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x220,
 730         },
 731         {
 732                 .number = U300_DMA_MSL_RX_1,
 733                 .name = "MSL RX 1",
 734                 .priority_high = 0,
 735                 .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x220,
 736                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 737                                 COH901318_CX_CFG_LCR_DISABLE |
 738                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 739                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 740                 .param.ctrl_lli_chained = 0 |
 741                                 COH901318_CX_CTRL_TC_ENABLE |
 742                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 743                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 744                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 745                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 746                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 747                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 748                                 COH901318_CX_CTRL_TCP_DISABLE |
 749                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 750                                 COH901318_CX_CTRL_HSP_ENABLE |
 751                                 COH901318_CX_CTRL_HSS_DISABLE |
 752                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 753                                 COH901318_CX_CTRL_PRDD_DEST,
 754                 .param.ctrl_lli = 0,
 755                 .param.ctrl_lli_last = 0 |
 756                                 COH901318_CX_CTRL_TC_ENABLE |
 757                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 758                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 759                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 760                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 761                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 762                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 763                                 COH901318_CX_CTRL_TCP_DISABLE |
 764                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 765                                 COH901318_CX_CTRL_HSP_ENABLE |
 766                                 COH901318_CX_CTRL_HSS_DISABLE |
 767                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 768                                 COH901318_CX_CTRL_PRDD_DEST,
 769         },
 770         {
 771                 .number = U300_DMA_MSL_RX_2,
 772                 .name = "MSL RX 2",
 773                 .priority_high = 0,
 774                 .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x220,
 775                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 776                                 COH901318_CX_CFG_LCR_DISABLE |
 777                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 778                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 779                 .param.ctrl_lli_chained = 0 |
 780                                 COH901318_CX_CTRL_TC_ENABLE |
 781                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 782                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 783                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 784                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 785                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 786                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 787                                 COH901318_CX_CTRL_TCP_DISABLE |
 788                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 789                                 COH901318_CX_CTRL_HSP_ENABLE |
 790                                 COH901318_CX_CTRL_HSS_DISABLE |
 791                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 792                                 COH901318_CX_CTRL_PRDD_DEST,
 793                 .param.ctrl_lli = 0 |
 794                                 COH901318_CX_CTRL_TC_ENABLE |
 795                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 796                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 797                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 798                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 799                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 800                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 801                                 COH901318_CX_CTRL_TCP_DISABLE |
 802                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 803                                 COH901318_CX_CTRL_HSP_ENABLE |
 804                                 COH901318_CX_CTRL_HSS_DISABLE |
 805                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 806                                 COH901318_CX_CTRL_PRDD_DEST,
 807                 .param.ctrl_lli_last = 0 |
 808                                 COH901318_CX_CTRL_TC_ENABLE |
 809                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 810                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 811                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 812                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 813                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 814                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 815                                 COH901318_CX_CTRL_TCP_DISABLE |
 816                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 817                                 COH901318_CX_CTRL_HSP_ENABLE |
 818                                 COH901318_CX_CTRL_HSS_DISABLE |
 819                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 820                                 COH901318_CX_CTRL_PRDD_DEST,
 821         },
 822         {
 823                 .number = U300_DMA_MSL_RX_3,
 824                 .name = "MSL RX 3",
 825                 .priority_high = 0,
 826                 .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x220,
 827                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 828                                 COH901318_CX_CFG_LCR_DISABLE |
 829                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 830                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 831                 .param.ctrl_lli_chained = 0 |
 832                                 COH901318_CX_CTRL_TC_ENABLE |
 833                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 834                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 835                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 836                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 837                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 838                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 839                                 COH901318_CX_CTRL_TCP_DISABLE |
 840                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 841                                 COH901318_CX_CTRL_HSP_ENABLE |
 842                                 COH901318_CX_CTRL_HSS_DISABLE |
 843                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 844                                 COH901318_CX_CTRL_PRDD_DEST,
 845                 .param.ctrl_lli = 0 |
 846                                 COH901318_CX_CTRL_TC_ENABLE |
 847                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 848                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 849                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 850                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 851                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 852                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 853                                 COH901318_CX_CTRL_TCP_DISABLE |
 854                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 855                                 COH901318_CX_CTRL_HSP_ENABLE |
 856                                 COH901318_CX_CTRL_HSS_DISABLE |
 857                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 858                                 COH901318_CX_CTRL_PRDD_DEST,
 859                 .param.ctrl_lli_last = 0 |
 860                                 COH901318_CX_CTRL_TC_ENABLE |
 861                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 862                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 863                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 864                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 865                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 866                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 867                                 COH901318_CX_CTRL_TCP_DISABLE |
 868                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 869                                 COH901318_CX_CTRL_HSP_ENABLE |
 870                                 COH901318_CX_CTRL_HSS_DISABLE |
 871                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 872                                 COH901318_CX_CTRL_PRDD_DEST,
 873         },
 874         {
 875                 .number = U300_DMA_MSL_RX_4,
 876                 .name = "MSL RX 4",
 877                 .priority_high = 0,
 878                 .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x220,
 879                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 880                                 COH901318_CX_CFG_LCR_DISABLE |
 881                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 882                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 883                 .param.ctrl_lli_chained = 0 |
 884                                 COH901318_CX_CTRL_TC_ENABLE |
 885                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 886                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 887                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 888                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 889                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 890                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 891                                 COH901318_CX_CTRL_TCP_DISABLE |
 892                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 893                                 COH901318_CX_CTRL_HSP_ENABLE |
 894                                 COH901318_CX_CTRL_HSS_DISABLE |
 895                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 896                                 COH901318_CX_CTRL_PRDD_DEST,
 897                 .param.ctrl_lli = 0 |
 898                                 COH901318_CX_CTRL_TC_ENABLE |
 899                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 900                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 901                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 902                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 903                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 904                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 905                                 COH901318_CX_CTRL_TCP_DISABLE |
 906                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 907                                 COH901318_CX_CTRL_HSP_ENABLE |
 908                                 COH901318_CX_CTRL_HSS_DISABLE |
 909                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 910                                 COH901318_CX_CTRL_PRDD_DEST,
 911                 .param.ctrl_lli_last = 0 |
 912                                 COH901318_CX_CTRL_TC_ENABLE |
 913                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 914                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 915                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 916                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 917                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 918                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 919                                 COH901318_CX_CTRL_TCP_DISABLE |
 920                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 921                                 COH901318_CX_CTRL_HSP_ENABLE |
 922                                 COH901318_CX_CTRL_HSS_DISABLE |
 923                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 924                                 COH901318_CX_CTRL_PRDD_DEST,
 925         },
 926         {
 927                 .number = U300_DMA_MSL_RX_5,
 928                 .name = "MSL RX 5",
 929                 .priority_high = 0,
 930                 .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x220,
 931                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 932                                 COH901318_CX_CFG_LCR_DISABLE |
 933                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 934                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 935                 .param.ctrl_lli_chained = 0 |
 936                                 COH901318_CX_CTRL_TC_ENABLE |
 937                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 938                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 939                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 940                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 941                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 942                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 943                                 COH901318_CX_CTRL_TCP_DISABLE |
 944                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 945                                 COH901318_CX_CTRL_HSP_ENABLE |
 946                                 COH901318_CX_CTRL_HSS_DISABLE |
 947                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 948                                 COH901318_CX_CTRL_PRDD_DEST,
 949                 .param.ctrl_lli = 0 |
 950                                 COH901318_CX_CTRL_TC_ENABLE |
 951                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 952                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 953                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 954                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 955                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 956                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 957                                 COH901318_CX_CTRL_TCP_DISABLE |
 958                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 959                                 COH901318_CX_CTRL_HSP_ENABLE |
 960                                 COH901318_CX_CTRL_HSS_DISABLE |
 961                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 962                                 COH901318_CX_CTRL_PRDD_DEST,
 963                 .param.ctrl_lli_last = 0 |
 964                                 COH901318_CX_CTRL_TC_ENABLE |
 965                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 966                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 967                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 968                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 969                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 970                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 971                                 COH901318_CX_CTRL_TCP_DISABLE |
 972                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 973                                 COH901318_CX_CTRL_HSP_ENABLE |
 974                                 COH901318_CX_CTRL_HSS_DISABLE |
 975                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 976                                 COH901318_CX_CTRL_PRDD_DEST,
 977         },
 978         {
 979                 .number = U300_DMA_MSL_RX_6,
 980                 .name = "MSL RX 6",
 981                 .priority_high = 0,
 982                 .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x220,
 983         },
 984         /*
 985          * Don't set up device address, burst count or size of src
 986          * or dst bus for this peripheral - handled by PrimeCell
 987          * DMA extension.
 988          */
 989         {
 990                 .number = U300_DMA_MMCSD_RX_TX,
 991                 .name = "MMCSD RX TX",
 992                 .priority_high = 0,
 993                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 994                                 COH901318_CX_CFG_LCR_DISABLE |
 995                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 996                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 997                 .param.ctrl_lli_chained = 0 |
 998                                 COH901318_CX_CTRL_TC_ENABLE |
 999                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1000                                 COH901318_CX_CTRL_TCP_ENABLE |
1001                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1002                                 COH901318_CX_CTRL_HSP_ENABLE |
1003                                 COH901318_CX_CTRL_HSS_DISABLE |
1004                                 COH901318_CX_CTRL_DDMA_LEGACY,
1005                 .param.ctrl_lli = 0 |
1006                                 COH901318_CX_CTRL_TC_ENABLE |
1007                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1008                                 COH901318_CX_CTRL_TCP_ENABLE |
1009                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1010                                 COH901318_CX_CTRL_HSP_ENABLE |
1011                                 COH901318_CX_CTRL_HSS_DISABLE |
1012                                 COH901318_CX_CTRL_DDMA_LEGACY,
1013                 .param.ctrl_lli_last = 0 |
1014                                 COH901318_CX_CTRL_TC_ENABLE |
1015                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1016                                 COH901318_CX_CTRL_TCP_DISABLE |
1017                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1018                                 COH901318_CX_CTRL_HSP_ENABLE |
1019                                 COH901318_CX_CTRL_HSS_DISABLE |
1020                                 COH901318_CX_CTRL_DDMA_LEGACY,
1021
1022         },
1023         {
1024                 .number = U300_DMA_MSPRO_TX,
1025                 .name = "MSPRO TX",
1026                 .priority_high = 0,
1027         },
1028         {
1029                 .number = U300_DMA_MSPRO_RX,
1030                 .name = "MSPRO RX",
1031                 .priority_high = 0,
1032         },
1033         /*
1034          * Don't set up device address, burst count or size of src
1035          * or dst bus for this peripheral - handled by PrimeCell
1036          * DMA extension.
1037          */
1038         {
1039                 .number = U300_DMA_UART0_TX,
1040                 .name = "UART0 TX",
1041                 .priority_high = 0,
1042                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1043                                 COH901318_CX_CFG_LCR_DISABLE |
1044                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1045                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1046                 .param.ctrl_lli_chained = 0 |
1047                                 COH901318_CX_CTRL_TC_ENABLE |
1048                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1049                                 COH901318_CX_CTRL_TCP_ENABLE |
1050                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1051                                 COH901318_CX_CTRL_HSP_ENABLE |
1052                                 COH901318_CX_CTRL_HSS_DISABLE |
1053                                 COH901318_CX_CTRL_DDMA_LEGACY,
1054                 .param.ctrl_lli = 0 |
1055                                 COH901318_CX_CTRL_TC_ENABLE |
1056                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1057                                 COH901318_CX_CTRL_TCP_ENABLE |
1058                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1059                                 COH901318_CX_CTRL_HSP_ENABLE |
1060                                 COH901318_CX_CTRL_HSS_DISABLE |
1061                                 COH901318_CX_CTRL_DDMA_LEGACY,
1062                 .param.ctrl_lli_last = 0 |
1063                                 COH901318_CX_CTRL_TC_ENABLE |
1064                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1065                                 COH901318_CX_CTRL_TCP_ENABLE |
1066                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1067                                 COH901318_CX_CTRL_HSP_ENABLE |
1068                                 COH901318_CX_CTRL_HSS_DISABLE |
1069                                 COH901318_CX_CTRL_DDMA_LEGACY,
1070         },
1071         {
1072                 .number = U300_DMA_UART0_RX,
1073                 .name = "UART0 RX",
1074                 .priority_high = 0,
1075                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1076                                 COH901318_CX_CFG_LCR_DISABLE |
1077                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1078                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1079                 .param.ctrl_lli_chained = 0 |
1080                                 COH901318_CX_CTRL_TC_ENABLE |
1081                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1082                                 COH901318_CX_CTRL_TCP_ENABLE |
1083                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1084                                 COH901318_CX_CTRL_HSP_ENABLE |
1085                                 COH901318_CX_CTRL_HSS_DISABLE |
1086                                 COH901318_CX_CTRL_DDMA_LEGACY,
1087                 .param.ctrl_lli = 0 |
1088                                 COH901318_CX_CTRL_TC_ENABLE |
1089                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1090                                 COH901318_CX_CTRL_TCP_ENABLE |
1091                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1092                                 COH901318_CX_CTRL_HSP_ENABLE |
1093                                 COH901318_CX_CTRL_HSS_DISABLE |
1094                                 COH901318_CX_CTRL_DDMA_LEGACY,
1095                 .param.ctrl_lli_last = 0 |
1096                                 COH901318_CX_CTRL_TC_ENABLE |
1097                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1098                                 COH901318_CX_CTRL_TCP_ENABLE |
1099                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1100                                 COH901318_CX_CTRL_HSP_ENABLE |
1101                                 COH901318_CX_CTRL_HSS_DISABLE |
1102                                 COH901318_CX_CTRL_DDMA_LEGACY,
1103         },
1104         {
1105                 .number = U300_DMA_APEX_TX,
1106                 .name = "APEX TX",
1107                 .priority_high = 0,
1108         },
1109         {
1110                 .number = U300_DMA_APEX_RX,
1111                 .name = "APEX RX",
1112                 .priority_high = 0,
1113         },
1114         {
1115                 .number = U300_DMA_PCM_I2S0_TX,
1116                 .name = "PCM I2S0 TX",
1117                 .priority_high = 1,
1118                 .dev_addr = U300_PCM_I2S0_BASE + 0x14,
1119                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1120                                 COH901318_CX_CFG_LCR_DISABLE |
1121                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1122                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1123                 .param.ctrl_lli_chained = 0 |
1124                                 COH901318_CX_CTRL_TC_ENABLE |
1125                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1126                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1127                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1128                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1129                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1130                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1131                                 COH901318_CX_CTRL_TCP_DISABLE |
1132                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1133                                 COH901318_CX_CTRL_HSP_ENABLE |
1134                                 COH901318_CX_CTRL_HSS_DISABLE |
1135                                 COH901318_CX_CTRL_DDMA_LEGACY |
1136                                 COH901318_CX_CTRL_PRDD_SOURCE,
1137                 .param.ctrl_lli = 0 |
1138                                 COH901318_CX_CTRL_TC_ENABLE |
1139                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1140                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1141                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1142                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1143                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1144                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1145                                 COH901318_CX_CTRL_TCP_ENABLE |
1146                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1147                                 COH901318_CX_CTRL_HSP_ENABLE |
1148                                 COH901318_CX_CTRL_HSS_DISABLE |
1149                                 COH901318_CX_CTRL_DDMA_LEGACY |
1150                                 COH901318_CX_CTRL_PRDD_SOURCE,
1151                 .param.ctrl_lli_last = 0 |
1152                                 COH901318_CX_CTRL_TC_ENABLE |
1153                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1154                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1155                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1156                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1157                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1158                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1159                                 COH901318_CX_CTRL_TCP_ENABLE |
1160                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1161                                 COH901318_CX_CTRL_HSP_ENABLE |
1162                                 COH901318_CX_CTRL_HSS_DISABLE |
1163                                 COH901318_CX_CTRL_DDMA_LEGACY |
1164                                 COH901318_CX_CTRL_PRDD_SOURCE,
1165         },
1166         {
1167                 .number = U300_DMA_PCM_I2S0_RX,
1168                 .name = "PCM I2S0 RX",
1169                 .priority_high = 1,
1170                 .dev_addr = U300_PCM_I2S0_BASE + 0x10,
1171                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1172                                 COH901318_CX_CFG_LCR_DISABLE |
1173                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1174                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1175                 .param.ctrl_lli_chained = 0 |
1176                                 COH901318_CX_CTRL_TC_ENABLE |
1177                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1178                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1179                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1180                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1181                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1182                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1183                                 COH901318_CX_CTRL_TCP_DISABLE |
1184                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1185                                 COH901318_CX_CTRL_HSP_ENABLE |
1186                                 COH901318_CX_CTRL_HSS_DISABLE |
1187                                 COH901318_CX_CTRL_DDMA_LEGACY |
1188                                 COH901318_CX_CTRL_PRDD_DEST,
1189                 .param.ctrl_lli = 0 |
1190                                 COH901318_CX_CTRL_TC_ENABLE |
1191                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1192                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1193                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1194                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1195                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1196                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1197                                 COH901318_CX_CTRL_TCP_ENABLE |
1198                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1199                                 COH901318_CX_CTRL_HSP_ENABLE |
1200                                 COH901318_CX_CTRL_HSS_DISABLE |
1201                                 COH901318_CX_CTRL_DDMA_LEGACY |
1202                                 COH901318_CX_CTRL_PRDD_DEST,
1203                 .param.ctrl_lli_last = 0 |
1204                                 COH901318_CX_CTRL_TC_ENABLE |
1205                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1206                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1207                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1208                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1209                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1210                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1211                                 COH901318_CX_CTRL_TCP_ENABLE |
1212                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1213                                 COH901318_CX_CTRL_HSP_ENABLE |
1214                                 COH901318_CX_CTRL_HSS_DISABLE |
1215                                 COH901318_CX_CTRL_DDMA_LEGACY |
1216                                 COH901318_CX_CTRL_PRDD_DEST,
1217         },
1218         {
1219                 .number = U300_DMA_PCM_I2S1_TX,
1220                 .name = "PCM I2S1 TX",
1221                 .priority_high = 1,
1222                 .dev_addr =  U300_PCM_I2S1_BASE + 0x14,
1223                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1224                                 COH901318_CX_CFG_LCR_DISABLE |
1225                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1226                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1227                 .param.ctrl_lli_chained = 0 |
1228                                 COH901318_CX_CTRL_TC_ENABLE |
1229                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1230                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1231                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1232                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1233                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1234                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1235                                 COH901318_CX_CTRL_TCP_DISABLE |
1236                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1237                                 COH901318_CX_CTRL_HSP_ENABLE |
1238                                 COH901318_CX_CTRL_HSS_DISABLE |
1239                                 COH901318_CX_CTRL_DDMA_LEGACY |
1240                                 COH901318_CX_CTRL_PRDD_SOURCE,
1241                 .param.ctrl_lli = 0 |
1242                                 COH901318_CX_CTRL_TC_ENABLE |
1243                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1244                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1245                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1246                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1247                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1248                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1249                                 COH901318_CX_CTRL_TCP_ENABLE |
1250                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1251                                 COH901318_CX_CTRL_HSP_ENABLE |
1252                                 COH901318_CX_CTRL_HSS_DISABLE |
1253                                 COH901318_CX_CTRL_DDMA_LEGACY |
1254                                 COH901318_CX_CTRL_PRDD_SOURCE,
1255                 .param.ctrl_lli_last = 0 |
1256                                 COH901318_CX_CTRL_TC_ENABLE |
1257                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1258                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1259                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1260                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1261                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1262                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1263                                 COH901318_CX_CTRL_TCP_ENABLE |
1264                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1265                                 COH901318_CX_CTRL_HSP_ENABLE |
1266                                 COH901318_CX_CTRL_HSS_DISABLE |
1267                                 COH901318_CX_CTRL_DDMA_LEGACY |
1268                                 COH901318_CX_CTRL_PRDD_SOURCE,
1269         },
1270         {
1271                 .number = U300_DMA_PCM_I2S1_RX,
1272                 .name = "PCM I2S1 RX",
1273                 .priority_high = 1,
1274                 .dev_addr = U300_PCM_I2S1_BASE + 0x10,
1275                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1276                                 COH901318_CX_CFG_LCR_DISABLE |
1277                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1278                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1279                 .param.ctrl_lli_chained = 0 |
1280                                 COH901318_CX_CTRL_TC_ENABLE |
1281                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1282                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1283                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1284                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1285                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1286                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1287                                 COH901318_CX_CTRL_TCP_DISABLE |
1288                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1289                                 COH901318_CX_CTRL_HSP_ENABLE |
1290                                 COH901318_CX_CTRL_HSS_DISABLE |
1291                                 COH901318_CX_CTRL_DDMA_LEGACY |
1292                                 COH901318_CX_CTRL_PRDD_DEST,
1293                 .param.ctrl_lli = 0 |
1294                                 COH901318_CX_CTRL_TC_ENABLE |
1295                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1296                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1297                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1298                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1299                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1300                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1301                                 COH901318_CX_CTRL_TCP_ENABLE |
1302                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1303                                 COH901318_CX_CTRL_HSP_ENABLE |
1304                                 COH901318_CX_CTRL_HSS_DISABLE |
1305                                 COH901318_CX_CTRL_DDMA_LEGACY |
1306                                 COH901318_CX_CTRL_PRDD_DEST,
1307                 .param.ctrl_lli_last = 0 |
1308                                 COH901318_CX_CTRL_TC_ENABLE |
1309                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1310                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1311                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1312                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1313                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1314                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1315                                 COH901318_CX_CTRL_TCP_ENABLE |
1316                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1317                                 COH901318_CX_CTRL_HSP_ENABLE |
1318                                 COH901318_CX_CTRL_HSS_DISABLE |
1319                                 COH901318_CX_CTRL_DDMA_LEGACY |
1320                                 COH901318_CX_CTRL_PRDD_DEST,
1321         },
1322         {
1323                 .number = U300_DMA_XGAM_CDI,
1324                 .name = "XGAM CDI",
1325                 .priority_high = 0,
1326         },
1327         {
1328                 .number = U300_DMA_XGAM_PDI,
1329                 .name = "XGAM PDI",
1330                 .priority_high = 0,
1331         },
1332         /*
1333          * Don't set up device address, burst count or size of src
1334          * or dst bus for this peripheral - handled by PrimeCell
1335          * DMA extension.
1336          */
1337         {
1338                 .number = U300_DMA_SPI_TX,
1339                 .name = "SPI TX",
1340                 .priority_high = 0,
1341                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1342                                 COH901318_CX_CFG_LCR_DISABLE |
1343                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1344                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1345                 .param.ctrl_lli_chained = 0 |
1346                                 COH901318_CX_CTRL_TC_ENABLE |
1347                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1348                                 COH901318_CX_CTRL_TCP_DISABLE |
1349                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1350                                 COH901318_CX_CTRL_HSP_ENABLE |
1351                                 COH901318_CX_CTRL_HSS_DISABLE |
1352                                 COH901318_CX_CTRL_DDMA_LEGACY,
1353                 .param.ctrl_lli = 0 |
1354                                 COH901318_CX_CTRL_TC_ENABLE |
1355                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1356                                 COH901318_CX_CTRL_TCP_DISABLE |
1357                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1358                                 COH901318_CX_CTRL_HSP_ENABLE |
1359                                 COH901318_CX_CTRL_HSS_DISABLE |
1360                                 COH901318_CX_CTRL_DDMA_LEGACY,
1361                 .param.ctrl_lli_last = 0 |
1362                                 COH901318_CX_CTRL_TC_ENABLE |
1363                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1364                                 COH901318_CX_CTRL_TCP_DISABLE |
1365                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1366                                 COH901318_CX_CTRL_HSP_ENABLE |
1367                                 COH901318_CX_CTRL_HSS_DISABLE |
1368                                 COH901318_CX_CTRL_DDMA_LEGACY,
1369         },
1370         {
1371                 .number = U300_DMA_SPI_RX,
1372                 .name = "SPI RX",
1373                 .priority_high = 0,
1374                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1375                                 COH901318_CX_CFG_LCR_DISABLE |
1376                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1377                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1378                 .param.ctrl_lli_chained = 0 |
1379                                 COH901318_CX_CTRL_TC_ENABLE |
1380                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1381                                 COH901318_CX_CTRL_TCP_DISABLE |
1382                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1383                                 COH901318_CX_CTRL_HSP_ENABLE |
1384                                 COH901318_CX_CTRL_HSS_DISABLE |
1385                                 COH901318_CX_CTRL_DDMA_LEGACY,
1386                 .param.ctrl_lli = 0 |
1387                                 COH901318_CX_CTRL_TC_ENABLE |
1388                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1389                                 COH901318_CX_CTRL_TCP_DISABLE |
1390                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1391                                 COH901318_CX_CTRL_HSP_ENABLE |
1392                                 COH901318_CX_CTRL_HSS_DISABLE |
1393                                 COH901318_CX_CTRL_DDMA_LEGACY,
1394                 .param.ctrl_lli_last = 0 |
1395                                 COH901318_CX_CTRL_TC_ENABLE |
1396                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1397                                 COH901318_CX_CTRL_TCP_DISABLE |
1398                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1399                                 COH901318_CX_CTRL_HSP_ENABLE |
1400                                 COH901318_CX_CTRL_HSS_DISABLE |
1401                                 COH901318_CX_CTRL_DDMA_LEGACY,
1402
1403         },
1404         {
1405                 .number = U300_DMA_GENERAL_PURPOSE_0,
1406                 .name = "GENERAL 00",
1407                 .priority_high = 0,
1408
1409                 .param.config = flags_memcpy_config,
1410                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1411                 .param.ctrl_lli = flags_memcpy_lli,
1412                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1413         },
1414         {
1415                 .number = U300_DMA_GENERAL_PURPOSE_1,
1416                 .name = "GENERAL 01",
1417                 .priority_high = 0,
1418
1419                 .param.config = flags_memcpy_config,
1420                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1421                 .param.ctrl_lli = flags_memcpy_lli,
1422                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1423         },
1424         {
1425                 .number = U300_DMA_GENERAL_PURPOSE_2,
1426                 .name = "GENERAL 02",
1427                 .priority_high = 0,
1428
1429                 .param.config = flags_memcpy_config,
1430                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1431                 .param.ctrl_lli = flags_memcpy_lli,
1432                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1433         },
1434         {
1435                 .number = U300_DMA_GENERAL_PURPOSE_3,
1436                 .name = "GENERAL 03",
1437                 .priority_high = 0,
1438
1439                 .param.config = flags_memcpy_config,
1440                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1441                 .param.ctrl_lli = flags_memcpy_lli,
1442                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1443         },
1444         {
1445                 .number = U300_DMA_GENERAL_PURPOSE_4,
1446                 .name = "GENERAL 04",
1447                 .priority_high = 0,
1448
1449                 .param.config = flags_memcpy_config,
1450                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1451                 .param.ctrl_lli = flags_memcpy_lli,
1452                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1453         },
1454         {
1455                 .number = U300_DMA_GENERAL_PURPOSE_5,
1456                 .name = "GENERAL 05",
1457                 .priority_high = 0,
1458
1459                 .param.config = flags_memcpy_config,
1460                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1461                 .param.ctrl_lli = flags_memcpy_lli,
1462                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1463         },
1464         {
1465                 .number = U300_DMA_GENERAL_PURPOSE_6,
1466                 .name = "GENERAL 06",
1467                 .priority_high = 0,
1468
1469                 .param.config = flags_memcpy_config,
1470                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1471                 .param.ctrl_lli = flags_memcpy_lli,
1472                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1473         },
1474         {
1475                 .number = U300_DMA_GENERAL_PURPOSE_7,
1476                 .name = "GENERAL 07",
1477                 .priority_high = 0,
1478
1479                 .param.config = flags_memcpy_config,
1480                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1481                 .param.ctrl_lli = flags_memcpy_lli,
1482                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1483         },
1484         {
1485                 .number = U300_DMA_GENERAL_PURPOSE_8,
1486                 .name = "GENERAL 08",
1487                 .priority_high = 0,
1488
1489                 .param.config = flags_memcpy_config,
1490                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1491                 .param.ctrl_lli = flags_memcpy_lli,
1492                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1493         },
1494 #ifdef CONFIG_MACH_U300_BS335
1495         {
1496                 .number = U300_DMA_UART1_TX,
1497                 .name = "UART1 TX",
1498                 .priority_high = 0,
1499         },
1500         {
1501                 .number = U300_DMA_UART1_RX,
1502                 .name = "UART1 RX",
1503                 .priority_high = 0,
1504         }
1505 #else
1506         {
1507                 .number = U300_DMA_GENERAL_PURPOSE_9,
1508                 .name = "GENERAL 09",
1509                 .priority_high = 0,
1510
1511                 .param.config = flags_memcpy_config,
1512                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1513                 .param.ctrl_lli = flags_memcpy_lli,
1514                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1515         },
1516         {
1517                 .number = U300_DMA_GENERAL_PURPOSE_10,
1518                 .name = "GENERAL 10",
1519                 .priority_high = 0,
1520
1521                 .param.config = flags_memcpy_config,
1522                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1523                 .param.ctrl_lli = flags_memcpy_lli,
1524                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1525         }
1526 #endif
1527 };
1528
1529
1530 static struct coh901318_platform coh901318_platform = {
1531         .chans_slave = dma_slave_channels,
1532         .chans_memcpy = dma_memcpy_channels,
1533         .access_memory_state = coh901318_access_memory_state,
1534         .chan_conf = chan_config,
1535         .max_channels = U300_DMA_CHANNELS,
1536 };
1537
1538 static struct platform_device wdog_device = {
1539         .name = "coh901327_wdog",
1540         .id = -1,
1541         .num_resources = ARRAY_SIZE(wdog_resources),
1542         .resource = wdog_resources,
1543 };
1544
1545 static struct platform_device i2c0_device = {
1546         .name = "stu300",
1547         .id = 0,
1548         .num_resources = ARRAY_SIZE(i2c0_resources),
1549         .resource = i2c0_resources,
1550 };
1551
1552 static struct platform_device i2c1_device = {
1553         .name = "stu300",
1554         .id = 1,
1555         .num_resources = ARRAY_SIZE(i2c1_resources),
1556         .resource = i2c1_resources,
1557 };
1558
1559 static struct platform_device gpio_device = {
1560         .name = "u300-gpio",
1561         .id = -1,
1562         .num_resources = ARRAY_SIZE(gpio_resources),
1563         .resource = gpio_resources,
1564 };
1565
1566 static struct platform_device keypad_device = {
1567         .name = "keypad",
1568         .id = -1,
1569         .num_resources = ARRAY_SIZE(keypad_resources),
1570         .resource = keypad_resources,
1571 };
1572
1573 static struct platform_device rtc_device = {
1574         .name = "rtc-coh901331",
1575         .id = -1,
1576         .num_resources = ARRAY_SIZE(rtc_resources),
1577         .resource = rtc_resources,
1578 };
1579
1580 static struct mtd_partition u300_partitions[] = {
1581         {
1582                 .name = "bootrecords",
1583                 .offset = 0,
1584                 .size = SZ_128K,
1585         },
1586         {
1587                 .name = "free",
1588                 .offset = SZ_128K,
1589                 .size = 8064 * SZ_1K,
1590         },
1591         {
1592                 .name = "platform",
1593                 .offset = 8192 * SZ_1K,
1594                 .size = 253952 * SZ_1K,
1595         },
1596 };
1597
1598 static struct fsmc_nand_platform_data nand_platform_data = {
1599         .partitions = u300_partitions,
1600         .nr_partitions = ARRAY_SIZE(u300_partitions),
1601         .options = NAND_SKIP_BBTSCAN,
1602         .width = FSMC_NAND_BW8,
1603 };
1604
1605 static struct platform_device nand_device = {
1606         .name = "fsmc-nand",
1607         .id = -1,
1608         .resource = fsmc_resources,
1609         .num_resources = ARRAY_SIZE(fsmc_resources),
1610         .dev = {
1611                 .platform_data = &nand_platform_data,
1612         },
1613 };
1614
1615 static struct platform_device ave_device = {
1616         .name = "video_enc",
1617         .id = -1,
1618         .num_resources = ARRAY_SIZE(ave_resources),
1619         .resource = ave_resources,
1620 };
1621
1622 static struct platform_device dma_device = {
1623         .name           = "coh901318",
1624         .id             = -1,
1625         .resource       = dma_resource,
1626         .num_resources  = ARRAY_SIZE(dma_resource),
1627         .dev = {
1628                 .platform_data = &coh901318_platform,
1629                 .coherent_dma_mask = ~0,
1630         },
1631 };
1632
1633 /*
1634  * Notice that AMBA devices are initialized before platform devices.
1635  *
1636  */
1637 static struct platform_device *platform_devs[] __initdata = {
1638         &dma_device,
1639         &i2c0_device,
1640         &i2c1_device,
1641         &keypad_device,
1642         &rtc_device,
1643         &gpio_device,
1644         &nand_device,
1645         &wdog_device,
1646         &ave_device
1647 };
1648
1649
1650 /*
1651  * Interrupts: the U300 platforms have two pl190 ARM PrimeCells connected
1652  * together so some interrupts are connected to the first one and some
1653  * to the second one.
1654  */
1655 void __init u300_init_irq(void)
1656 {
1657         u32 mask[2] = {0, 0};
1658         struct clk *clk;
1659         int i;
1660
1661         /* initialize clocking early, we want to clock the INTCON */
1662         u300_clock_init();
1663
1664         /* Clock the interrupt controller */
1665         clk = clk_get_sys("intcon", NULL);
1666         BUG_ON(IS_ERR(clk));
1667         clk_enable(clk);
1668
1669         for (i = 0; i < NR_IRQS; i++)
1670                 set_bit(i, (unsigned long *) &mask[0]);
1671         vic_init((void __iomem *) U300_INTCON0_VBASE, 0, mask[0], mask[0]);
1672         vic_init((void __iomem *) U300_INTCON1_VBASE, 32, mask[1], mask[1]);
1673 }
1674
1675
1676 /*
1677  * U300 platforms peripheral handling
1678  */
1679 struct db_chip {
1680         u16 chipid;
1681         const char *name;
1682 };
1683
1684 /*
1685  * This is a list of the Digital Baseband chips used in the U300 platform.
1686  */
1687 static struct db_chip db_chips[] __initdata = {
1688         {
1689                 .chipid = 0xb800,
1690                 .name = "DB3000",
1691         },
1692         {
1693                 .chipid = 0xc000,
1694                 .name = "DB3100",
1695         },
1696         {
1697                 .chipid = 0xc800,
1698                 .name = "DB3150",
1699         },
1700         {
1701                 .chipid = 0xd800,
1702                 .name = "DB3200",
1703         },
1704         {
1705                 .chipid = 0xe000,
1706                 .name = "DB3250",
1707         },
1708         {
1709                 .chipid = 0xe800,
1710                 .name = "DB3210",
1711         },
1712         {
1713                 .chipid = 0xf000,
1714                 .name = "DB3350 P1x",
1715         },
1716         {
1717                 .chipid = 0xf100,
1718                 .name = "DB3350 P2x",
1719         },
1720         {
1721                 .chipid = 0x0000, /* List terminator */
1722                 .name = NULL,
1723         }
1724 };
1725
1726 static void __init u300_init_check_chip(void)
1727 {
1728
1729         u16 val;
1730         struct db_chip *chip;
1731         const char *chipname;
1732         const char unknown[] = "UNKNOWN";
1733
1734         /* Read out and print chip ID */
1735         val = readw(U300_SYSCON_VBASE + U300_SYSCON_CIDR);
1736         /* This is in funky bigendian order... */
1737         val = (val & 0xFFU) << 8 | (val >> 8);
1738         chip = db_chips;
1739         chipname = unknown;
1740
1741         for ( ; chip->chipid; chip++) {
1742                 if (chip->chipid == (val & 0xFF00U)) {
1743                         chipname = chip->name;
1744                         break;
1745                 }
1746         }
1747         printk(KERN_INFO "Initializing U300 system on %s baseband chip " \
1748                "(chip ID 0x%04x)\n", chipname, val);
1749
1750 #ifdef CONFIG_MACH_U300_BS330
1751         if ((val & 0xFF00U) != 0xd800) {
1752                 printk(KERN_ERR "Platform configured for BS330 " \
1753                        "with DB3200 but %s detected, expect problems!",
1754                        chipname);
1755         }
1756 #endif
1757 #ifdef CONFIG_MACH_U300_BS335
1758         if ((val & 0xFF00U) != 0xf000 && (val & 0xFF00U) != 0xf100) {
1759                 printk(KERN_ERR "Platform configured for BS335 " \
1760                        " with DB3350 but %s detected, expect problems!",
1761                        chipname);
1762         }
1763 #endif
1764 #ifdef CONFIG_MACH_U300_BS365
1765         if ((val & 0xFF00U) != 0xe800) {
1766                 printk(KERN_ERR "Platform configured for BS365 " \
1767                        "with DB3210 but %s detected, expect problems!",
1768                        chipname);
1769         }
1770 #endif
1771
1772
1773 }
1774
1775 /*
1776  * Some devices and their resources require reserved physical memory from
1777  * the end of the available RAM. This function traverses the list of devices
1778  * and assigns actual addresses to these.
1779  */
1780 static void __init u300_assign_physmem(void)
1781 {
1782         unsigned long curr_start = __pa(high_memory);
1783         int i, j;
1784
1785         for (i = 0; i < ARRAY_SIZE(platform_devs); i++) {
1786                 for (j = 0; j < platform_devs[i]->num_resources; j++) {
1787                         struct resource *const res =
1788                           &platform_devs[i]->resource[j];
1789
1790                         if (IORESOURCE_MEM == res->flags &&
1791                                      0 == res->start) {
1792                                 res->start  = curr_start;
1793                                 res->end   += curr_start;
1794                                 curr_start += resource_size(res);
1795
1796                                 printk(KERN_INFO "core.c: Mapping RAM " \
1797                                        "%#x-%#x to device %s:%s\n",
1798                                         res->start, res->end,
1799                                        platform_devs[i]->name, res->name);
1800                         }
1801                 }
1802         }
1803 }
1804
1805 void __init u300_init_devices(void)
1806 {
1807         int i;
1808         u16 val;
1809
1810         /* Check what platform we run and print some status information */
1811         u300_init_check_chip();
1812
1813         /* Set system to run at PLL208, max performance, a known state. */
1814         val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
1815         val &= ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
1816         writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
1817         /* Wait for the PLL208 to lock if not locked in yet */
1818         while (!(readw(U300_SYSCON_VBASE + U300_SYSCON_CSR) &
1819                  U300_SYSCON_CSR_PLL208_LOCK_IND));
1820         /* Initialize SPI device with some board specifics */
1821         u300_spi_init(&pl022_device);
1822
1823         /* Register the AMBA devices in the AMBA bus abstraction layer */
1824         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
1825                 struct amba_device *d = amba_devs[i];
1826                 amba_device_register(d, &iomem_resource);
1827         }
1828
1829         u300_assign_physmem();
1830
1831         /* Register subdevices on the I2C buses */
1832         u300_i2c_register_board_devices();
1833
1834         /* Register the platform devices */
1835         platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
1836
1837         /* Register subdevices on the SPI bus */
1838         u300_spi_register_board_devices();
1839
1840 #ifndef CONFIG_MACH_U300_SEMI_IS_SHARED
1841         /*
1842          * Enable SEMI self refresh. Self-refresh of the SDRAM is entered when
1843          * both subsystems are requesting this mode.
1844          * If we not share the Acc SDRAM, this is never the case. Therefore
1845          * enable it here from the App side.
1846          */
1847         val = readw(U300_SYSCON_VBASE + U300_SYSCON_SMCR) |
1848                 U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE;
1849         writew(val, U300_SYSCON_VBASE + U300_SYSCON_SMCR);
1850 #endif /* CONFIG_MACH_U300_SEMI_IS_SHARED */
1851 }
1852
1853 static int core_module_init(void)
1854 {
1855         /*
1856          * This needs to be initialized later: it needs the input framework
1857          * to be initialized first.
1858          */
1859         return mmc_init(&mmcsd_device);
1860 }
1861 module_init(core_module_init);