2 * arch/arch/mach-tegra/timer.c
4 * Copyright (C) 2010 Google, Inc.
7 * Colin Cross <ccross@google.com>
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
20 #include <linux/init.h>
21 #include <linux/err.h>
22 #include <linux/time.h>
23 #include <linux/interrupt.h>
24 #include <linux/irq.h>
25 #include <linux/clockchips.h>
26 #include <linux/clocksource.h>
27 #include <linux/clk.h>
30 #include <asm/mach/time.h>
31 #include <asm/localtimer.h>
32 #include <asm/sched_clock.h>
34 #include <mach/iomap.h>
35 #include <mach/irqs.h>
36 #include <mach/suspend.h>
41 #define RTC_SECONDS 0x08
42 #define RTC_SHADOW_SECONDS 0x0c
43 #define RTC_MILLISECONDS 0x10
45 #define TIMERUS_CNTR_1US 0x10
46 #define TIMERUS_USEC_CFG 0x14
47 #define TIMERUS_CNTR_FREEZE 0x4c
49 #define TIMER1_BASE 0x0
50 #define TIMER2_BASE 0x8
51 #define TIMER3_BASE 0x50
52 #define TIMER4_BASE 0x58
57 static void __iomem *timer_reg_base = IO_ADDRESS(TEGRA_TMR1_BASE);
58 static void __iomem *rtc_base = IO_ADDRESS(TEGRA_RTC_BASE);
60 static struct timespec persistent_ts;
61 static u64 persistent_ms, last_persistent_ms;
63 #define timer_writel(value, reg) \
64 __raw_writel(value, timer_reg_base + (reg))
65 #define timer_readl(reg) \
66 __raw_readl(timer_reg_base + (reg))
68 static int tegra_timer_set_next_event(unsigned long cycles,
69 struct clock_event_device *evt)
73 reg = 0x80000000 | ((cycles > 1) ? (cycles-1) : 0);
74 timer_writel(reg, TIMER3_BASE + TIMER_PTV);
79 static void tegra_timer_set_mode(enum clock_event_mode mode,
80 struct clock_event_device *evt)
84 timer_writel(0, TIMER3_BASE + TIMER_PTV);
87 case CLOCK_EVT_MODE_PERIODIC:
88 reg = 0xC0000000 | ((1000000/HZ)-1);
89 timer_writel(reg, TIMER3_BASE + TIMER_PTV);
91 case CLOCK_EVT_MODE_ONESHOT:
93 case CLOCK_EVT_MODE_UNUSED:
94 case CLOCK_EVT_MODE_SHUTDOWN:
95 case CLOCK_EVT_MODE_RESUME:
100 static struct clock_event_device tegra_clockevent = {
103 .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
104 .set_next_event = tegra_timer_set_next_event,
105 .set_mode = tegra_timer_set_mode,
108 static u32 notrace tegra_read_sched_clock(void)
110 return timer_readl(TIMERUS_CNTR_1US);
114 * tegra_rtc_read - Reads the Tegra RTC registers
115 * Care must be taken that this funciton is not called while the
116 * tegra_rtc driver could be executing to avoid race conditions
117 * on the RTC shadow register
119 static u64 tegra_rtc_read_ms(void)
121 u32 ms = readl(rtc_base + RTC_MILLISECONDS);
122 u32 s = readl(rtc_base + RTC_SHADOW_SECONDS);
123 return (u64)s * MSEC_PER_SEC + ms;
127 * read_persistent_clock - Return time from a persistent clock.
129 * Reads the time from a source which isn't disabled during PM, the
130 * 32k sync timer. Convert the cycles elapsed since last read into
131 * nsecs and adds to a monotonically increasing timespec.
132 * Care must be taken that this funciton is not called while the
133 * tegra_rtc driver could be executing to avoid race conditions
134 * on the RTC shadow register
136 void read_persistent_clock(struct timespec *ts)
139 struct timespec *tsp = &persistent_ts;
141 last_persistent_ms = persistent_ms;
142 persistent_ms = tegra_rtc_read_ms();
143 delta = persistent_ms - last_persistent_ms;
145 timespec_add_ns(tsp, delta * NSEC_PER_MSEC);
149 static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id)
151 struct clock_event_device *evt = (struct clock_event_device *)dev_id;
152 timer_writel(1<<30, TIMER3_BASE + TIMER_PCR);
153 evt->event_handler(evt);
157 static struct irqaction tegra_timer_irq = {
159 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_HIGH,
160 .handler = tegra_timer_interrupt,
161 .dev_id = &tegra_clockevent,
165 static void __init tegra_init_timer(void)
168 unsigned long rate = clk_measure_input_freq();
171 clk = clk_get_sys("timer", NULL);
176 * rtc registers are used by read_persistent_clock, keep the rtc clock
179 clk = clk_get_sys("rtc-tegra", NULL);
183 #ifdef CONFIG_HAVE_ARM_TWD
184 twd_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x600);
189 timer_writel(0x000b, TIMERUS_USEC_CFG);
192 timer_writel(0x000c, TIMERUS_USEC_CFG);
195 timer_writel(0x045f, TIMERUS_USEC_CFG);
198 timer_writel(0x0019, TIMERUS_USEC_CFG);
201 WARN(1, "Unknown clock rate");
204 setup_sched_clock(tegra_read_sched_clock, 32, 1000000);
206 if (clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
207 "timer_us", 1000000, 300, 32, clocksource_mmio_readl_up)) {
208 printk(KERN_ERR "Failed to register clocksource\n");
212 ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq);
214 printk(KERN_ERR "Failed to register timer IRQ: %d\n", ret);
218 clockevents_calc_mult_shift(&tegra_clockevent, 1000000, 5);
219 tegra_clockevent.max_delta_ns =
220 clockevent_delta2ns(0x1fffffff, &tegra_clockevent);
221 tegra_clockevent.min_delta_ns =
222 clockevent_delta2ns(0x1, &tegra_clockevent);
223 tegra_clockevent.cpumask = cpu_all_mask;
224 tegra_clockevent.irq = tegra_timer_irq.irq;
225 clockevents_register_device(&tegra_clockevent);
228 struct sys_timer tegra_timer = {
229 .init = tegra_init_timer,
233 static u32 usec_config;
235 void tegra_timer_suspend(void)
237 usec_config = timer_readl(TIMERUS_USEC_CFG);
240 void tegra_timer_resume(void)
242 timer_writel(usec_config, TIMERUS_USEC_CFG);