2 * linux/arch/arm/mach-tegra/pinmux.c
4 * Copyright (C) 2010 Google, Inc.
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/errno.h>
21 #include <linux/spinlock.h>
23 #include <linux/platform_device.h>
25 #include <mach/iomap.h>
26 #include <mach/pinmux.h>
28 #define HSM_EN(reg) (((reg) >> 2) & 0x1)
29 #define SCHMT_EN(reg) (((reg) >> 3) & 0x1)
30 #define LPMD(reg) (((reg) >> 4) & 0x3)
31 #define DRVDN(reg) (((reg) >> 12) & 0x1f)
32 #define DRVUP(reg) (((reg) >> 20) & 0x1f)
33 #define SLWR(reg) (((reg) >> 28) & 0x3)
34 #define SLWF(reg) (((reg) >> 30) & 0x3)
36 static const struct tegra_pingroup_desc *const pingroups = tegra_soc_pingroups;
37 static const struct tegra_drive_pingroup_desc *const drive_pingroups = tegra_soc_drive_pingroups;
39 static char *tegra_mux_names[TEGRA_MAX_MUX] = {
40 [TEGRA_MUX_AHB_CLK] = "AHB_CLK",
41 [TEGRA_MUX_APB_CLK] = "APB_CLK",
42 [TEGRA_MUX_AUDIO_SYNC] = "AUDIO_SYNC",
43 [TEGRA_MUX_CRT] = "CRT",
44 [TEGRA_MUX_DAP1] = "DAP1",
45 [TEGRA_MUX_DAP2] = "DAP2",
46 [TEGRA_MUX_DAP3] = "DAP3",
47 [TEGRA_MUX_DAP4] = "DAP4",
48 [TEGRA_MUX_DAP5] = "DAP5",
49 [TEGRA_MUX_DISPLAYA] = "DISPLAYA",
50 [TEGRA_MUX_DISPLAYB] = "DISPLAYB",
51 [TEGRA_MUX_EMC_TEST0_DLL] = "EMC_TEST0_DLL",
52 [TEGRA_MUX_EMC_TEST1_DLL] = "EMC_TEST1_DLL",
53 [TEGRA_MUX_GMI] = "GMI",
54 [TEGRA_MUX_GMI_INT] = "GMI_INT",
55 [TEGRA_MUX_HDMI] = "HDMI",
56 [TEGRA_MUX_I2C] = "I2C",
57 [TEGRA_MUX_I2C2] = "I2C2",
58 [TEGRA_MUX_I2C3] = "I2C3",
59 [TEGRA_MUX_IDE] = "IDE",
60 [TEGRA_MUX_IRDA] = "IRDA",
61 [TEGRA_MUX_KBC] = "KBC",
62 [TEGRA_MUX_MIO] = "MIO",
63 [TEGRA_MUX_MIPI_HS] = "MIPI_HS",
64 [TEGRA_MUX_NAND] = "NAND",
65 [TEGRA_MUX_OSC] = "OSC",
66 [TEGRA_MUX_OWR] = "OWR",
67 [TEGRA_MUX_PCIE] = "PCIE",
68 [TEGRA_MUX_PLLA_OUT] = "PLLA_OUT",
69 [TEGRA_MUX_PLLC_OUT1] = "PLLC_OUT1",
70 [TEGRA_MUX_PLLM_OUT1] = "PLLM_OUT1",
71 [TEGRA_MUX_PLLP_OUT2] = "PLLP_OUT2",
72 [TEGRA_MUX_PLLP_OUT3] = "PLLP_OUT3",
73 [TEGRA_MUX_PLLP_OUT4] = "PLLP_OUT4",
74 [TEGRA_MUX_PWM] = "PWM",
75 [TEGRA_MUX_PWR_INTR] = "PWR_INTR",
76 [TEGRA_MUX_PWR_ON] = "PWR_ON",
77 [TEGRA_MUX_RTCK] = "RTCK",
78 [TEGRA_MUX_SDIO1] = "SDIO1",
79 [TEGRA_MUX_SDIO2] = "SDIO2",
80 [TEGRA_MUX_SDIO3] = "SDIO3",
81 [TEGRA_MUX_SDIO4] = "SDIO4",
82 [TEGRA_MUX_SFLASH] = "SFLASH",
83 [TEGRA_MUX_SPDIF] = "SPDIF",
84 [TEGRA_MUX_SPI1] = "SPI1",
85 [TEGRA_MUX_SPI2] = "SPI2",
86 [TEGRA_MUX_SPI2_ALT] = "SPI2_ALT",
87 [TEGRA_MUX_SPI3] = "SPI3",
88 [TEGRA_MUX_SPI4] = "SPI4",
89 [TEGRA_MUX_TRACE] = "TRACE",
90 [TEGRA_MUX_TWC] = "TWC",
91 [TEGRA_MUX_UARTA] = "UARTA",
92 [TEGRA_MUX_UARTB] = "UARTB",
93 [TEGRA_MUX_UARTC] = "UARTC",
94 [TEGRA_MUX_UARTD] = "UARTD",
95 [TEGRA_MUX_UARTE] = "UARTE",
96 [TEGRA_MUX_ULPI] = "ULPI",
97 [TEGRA_MUX_VI] = "VI",
98 [TEGRA_MUX_VI_SENSOR_CLK] = "VI_SENSOR_CLK",
99 [TEGRA_MUX_XIO] = "XIO",
100 [TEGRA_MUX_SAFE] = "<safe>",
103 static const char *tegra_drive_names[TEGRA_MAX_DRIVE] = {
104 [TEGRA_DRIVE_DIV_8] = "DIV_8",
105 [TEGRA_DRIVE_DIV_4] = "DIV_4",
106 [TEGRA_DRIVE_DIV_2] = "DIV_2",
107 [TEGRA_DRIVE_DIV_1] = "DIV_1",
110 static const char *tegra_slew_names[TEGRA_MAX_SLEW] = {
111 [TEGRA_SLEW_FASTEST] = "FASTEST",
112 [TEGRA_SLEW_FAST] = "FAST",
113 [TEGRA_SLEW_SLOW] = "SLOW",
114 [TEGRA_SLEW_SLOWEST] = "SLOWEST",
117 static DEFINE_SPINLOCK(mux_lock);
119 static const char *pingroup_name(enum tegra_pingroup pg)
121 if (pg < 0 || pg >= TEGRA_MAX_PINGROUP)
124 return pingroups[pg].name;
127 static const char *func_name(enum tegra_mux_func func)
129 if (func == TEGRA_MUX_RSVD1)
132 if (func == TEGRA_MUX_RSVD2)
135 if (func == TEGRA_MUX_RSVD3)
138 if (func == TEGRA_MUX_RSVD4)
141 if (func == TEGRA_MUX_NONE)
144 if (func < 0 || func >= TEGRA_MAX_MUX)
147 return tegra_mux_names[func];
151 static const char *tri_name(unsigned long val)
153 return val ? "TRISTATE" : "NORMAL";
156 static const char *pupd_name(unsigned long val)
174 static void __iomem **regs;
176 static inline u32 pg_readl(u32 bank, u32 reg)
178 return readl(regs[bank] + reg);
181 static inline void pg_writel(u32 val, u32 bank, u32 reg)
183 writel(val, regs[bank] + reg);
186 static int tegra_pinmux_set_func(const struct tegra_pingroup_config *config)
192 enum tegra_pingroup pg = config->pingroup;
193 enum tegra_mux_func func = config->func;
195 if (pg < 0 || pg >= TEGRA_MAX_PINGROUP)
198 if (pingroups[pg].mux_reg < 0)
204 if (func == TEGRA_MUX_SAFE)
205 func = pingroups[pg].func_safe;
207 if (func & TEGRA_MUX_RSVD) {
210 for (i = 0; i < 4; i++) {
211 if (pingroups[pg].funcs[i] == func) {
221 spin_lock_irqsave(&mux_lock, flags);
223 reg = pg_readl(pingroups[pg].mux_bank, pingroups[pg].mux_reg);
224 reg &= ~(0x3 << pingroups[pg].mux_bit);
225 reg |= mux << pingroups[pg].mux_bit;
226 pg_writel(reg, pingroups[pg].mux_bank, pingroups[pg].mux_reg);
228 spin_unlock_irqrestore(&mux_lock, flags);
233 int tegra_pinmux_set_tristate(enum tegra_pingroup pg,
234 enum tegra_tristate tristate)
239 if (pg < 0 || pg >= TEGRA_MAX_PINGROUP)
242 if (pingroups[pg].tri_reg < 0)
245 spin_lock_irqsave(&mux_lock, flags);
247 reg = pg_readl(pingroups[pg].tri_bank, pingroups[pg].tri_reg);
248 reg &= ~(0x1 << pingroups[pg].tri_bit);
250 reg |= 1 << pingroups[pg].tri_bit;
251 pg_writel(reg, pingroups[pg].tri_bank, pingroups[pg].tri_reg);
253 spin_unlock_irqrestore(&mux_lock, flags);
258 int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg,
259 enum tegra_pullupdown pupd)
264 if (pg < 0 || pg >= TEGRA_MAX_PINGROUP)
267 if (pingroups[pg].pupd_reg < 0)
270 if (pupd != TEGRA_PUPD_NORMAL &&
271 pupd != TEGRA_PUPD_PULL_DOWN &&
272 pupd != TEGRA_PUPD_PULL_UP)
276 spin_lock_irqsave(&mux_lock, flags);
278 reg = pg_readl(pingroups[pg].pupd_bank, pingroups[pg].pupd_reg);
279 reg &= ~(0x3 << pingroups[pg].pupd_bit);
280 reg |= pupd << pingroups[pg].pupd_bit;
281 pg_writel(reg, pingroups[pg].pupd_bank, pingroups[pg].pupd_reg);
283 spin_unlock_irqrestore(&mux_lock, flags);
288 static void tegra_pinmux_config_pingroup(const struct tegra_pingroup_config *config)
290 enum tegra_pingroup pingroup = config->pingroup;
291 enum tegra_mux_func func = config->func;
292 enum tegra_pullupdown pupd = config->pupd;
293 enum tegra_tristate tristate = config->tristate;
296 if (pingroups[pingroup].mux_reg >= 0) {
297 err = tegra_pinmux_set_func(config);
299 pr_err("pinmux: can't set pingroup %s func to %s: %d\n",
300 pingroup_name(pingroup), func_name(func), err);
303 if (pingroups[pingroup].pupd_reg >= 0) {
304 err = tegra_pinmux_set_pullupdown(pingroup, pupd);
306 pr_err("pinmux: can't set pingroup %s pullupdown to %s: %d\n",
307 pingroup_name(pingroup), pupd_name(pupd), err);
310 if (pingroups[pingroup].tri_reg >= 0) {
311 err = tegra_pinmux_set_tristate(pingroup, tristate);
313 pr_err("pinmux: can't set pingroup %s tristate to %s: %d\n",
314 pingroup_name(pingroup), tri_name(func), err);
318 void tegra_pinmux_config_table(const struct tegra_pingroup_config *config, int len)
322 for (i = 0; i < len; i++)
323 tegra_pinmux_config_pingroup(&config[i]);
326 static const char *drive_pinmux_name(enum tegra_drive_pingroup pg)
328 if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP)
331 return drive_pingroups[pg].name;
334 static const char *enable_name(unsigned long val)
336 return val ? "ENABLE" : "DISABLE";
339 static const char *drive_name(unsigned long val)
341 if (val >= TEGRA_MAX_DRIVE)
344 return tegra_drive_names[val];
347 static const char *slew_name(unsigned long val)
349 if (val >= TEGRA_MAX_SLEW)
352 return tegra_slew_names[val];
355 static int tegra_drive_pinmux_set_hsm(enum tegra_drive_pingroup pg,
360 if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP)
363 if (hsm != TEGRA_HSM_ENABLE && hsm != TEGRA_HSM_DISABLE)
366 spin_lock_irqsave(&mux_lock, flags);
368 reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
369 if (hsm == TEGRA_HSM_ENABLE)
373 pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
375 spin_unlock_irqrestore(&mux_lock, flags);
380 static int tegra_drive_pinmux_set_schmitt(enum tegra_drive_pingroup pg,
381 enum tegra_schmitt schmitt)
385 if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP)
388 if (schmitt != TEGRA_SCHMITT_ENABLE && schmitt != TEGRA_SCHMITT_DISABLE)
391 spin_lock_irqsave(&mux_lock, flags);
393 reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
394 if (schmitt == TEGRA_SCHMITT_ENABLE)
398 pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
400 spin_unlock_irqrestore(&mux_lock, flags);
405 static int tegra_drive_pinmux_set_drive(enum tegra_drive_pingroup pg,
406 enum tegra_drive drive)
410 if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP)
413 if (drive < 0 || drive >= TEGRA_MAX_DRIVE)
416 spin_lock_irqsave(&mux_lock, flags);
418 reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
421 pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
423 spin_unlock_irqrestore(&mux_lock, flags);
428 static int tegra_drive_pinmux_set_pull_down(enum tegra_drive_pingroup pg,
429 enum tegra_pull_strength pull_down)
433 if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP)
436 if (pull_down < 0 || pull_down >= TEGRA_MAX_PULL)
439 spin_lock_irqsave(&mux_lock, flags);
441 reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
442 reg &= ~(0x1f << 12);
443 reg |= pull_down << 12;
444 pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
446 spin_unlock_irqrestore(&mux_lock, flags);
451 static int tegra_drive_pinmux_set_pull_up(enum tegra_drive_pingroup pg,
452 enum tegra_pull_strength pull_up)
456 if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP)
459 if (pull_up < 0 || pull_up >= TEGRA_MAX_PULL)
462 spin_lock_irqsave(&mux_lock, flags);
464 reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
465 reg &= ~(0x1f << 12);
466 reg |= pull_up << 12;
467 pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
469 spin_unlock_irqrestore(&mux_lock, flags);
474 static int tegra_drive_pinmux_set_slew_rising(enum tegra_drive_pingroup pg,
475 enum tegra_slew slew_rising)
479 if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP)
482 if (slew_rising < 0 || slew_rising >= TEGRA_MAX_SLEW)
485 spin_lock_irqsave(&mux_lock, flags);
487 reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
489 reg |= slew_rising << 28;
490 pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
492 spin_unlock_irqrestore(&mux_lock, flags);
497 static int tegra_drive_pinmux_set_slew_falling(enum tegra_drive_pingroup pg,
498 enum tegra_slew slew_falling)
502 if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP)
505 if (slew_falling < 0 || slew_falling >= TEGRA_MAX_SLEW)
508 spin_lock_irqsave(&mux_lock, flags);
510 reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
512 reg |= slew_falling << 30;
513 pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
515 spin_unlock_irqrestore(&mux_lock, flags);
520 static void tegra_drive_pinmux_config_pingroup(enum tegra_drive_pingroup pingroup,
522 enum tegra_schmitt schmitt,
523 enum tegra_drive drive,
524 enum tegra_pull_strength pull_down,
525 enum tegra_pull_strength pull_up,
526 enum tegra_slew slew_rising,
527 enum tegra_slew slew_falling)
531 err = tegra_drive_pinmux_set_hsm(pingroup, hsm);
533 pr_err("pinmux: can't set pingroup %s hsm to %s: %d\n",
534 drive_pinmux_name(pingroup),
535 enable_name(hsm), err);
537 err = tegra_drive_pinmux_set_schmitt(pingroup, schmitt);
539 pr_err("pinmux: can't set pingroup %s schmitt to %s: %d\n",
540 drive_pinmux_name(pingroup),
541 enable_name(schmitt), err);
543 err = tegra_drive_pinmux_set_drive(pingroup, drive);
545 pr_err("pinmux: can't set pingroup %s drive to %s: %d\n",
546 drive_pinmux_name(pingroup),
547 drive_name(drive), err);
549 err = tegra_drive_pinmux_set_pull_down(pingroup, pull_down);
551 pr_err("pinmux: can't set pingroup %s pull down to %d: %d\n",
552 drive_pinmux_name(pingroup),
555 err = tegra_drive_pinmux_set_pull_up(pingroup, pull_up);
557 pr_err("pinmux: can't set pingroup %s pull up to %d: %d\n",
558 drive_pinmux_name(pingroup),
561 err = tegra_drive_pinmux_set_slew_rising(pingroup, slew_rising);
563 pr_err("pinmux: can't set pingroup %s rising slew to %s: %d\n",
564 drive_pinmux_name(pingroup),
565 slew_name(slew_rising), err);
567 err = tegra_drive_pinmux_set_slew_falling(pingroup, slew_falling);
569 pr_err("pinmux: can't set pingroup %s falling slew to %s: %d\n",
570 drive_pinmux_name(pingroup),
571 slew_name(slew_falling), err);
574 void tegra_drive_pinmux_config_table(struct tegra_drive_pingroup_config *config,
579 for (i = 0; i < len; i++)
580 tegra_drive_pinmux_config_pingroup(config[i].pingroup,
586 config[i].slew_rising,
587 config[i].slew_falling);
590 void tegra_pinmux_set_safe_pinmux_table(const struct tegra_pingroup_config *config,
594 struct tegra_pingroup_config c;
596 for (i = 0; i < len; i++) {
599 if (c.pingroup < 0 || c.pingroup >= TEGRA_MAX_PINGROUP) {
603 c.func = pingroups[c.pingroup].func_safe;
604 err = tegra_pinmux_set_func(&c);
606 pr_err("%s: tegra_pinmux_set_func returned %d setting "
607 "%s to %s\n", __func__, err,
608 pingroup_name(c.pingroup), func_name(c.func));
612 void tegra_pinmux_config_pinmux_table(const struct tegra_pingroup_config *config,
617 for (i = 0; i < len; i++) {
619 if (config[i].pingroup < 0 ||
620 config[i].pingroup >= TEGRA_MAX_PINGROUP) {
624 err = tegra_pinmux_set_func(&config[i]);
626 pr_err("%s: tegra_pinmux_set_func returned %d setting "
627 "%s to %s\n", __func__, err,
628 pingroup_name(config[i].pingroup),
629 func_name(config[i].func));
633 void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *config,
634 int len, enum tegra_tristate tristate)
638 enum tegra_pingroup pingroup;
640 for (i = 0; i < len; i++) {
641 pingroup = config[i].pingroup;
642 if (pingroups[pingroup].tri_reg >= 0) {
643 err = tegra_pinmux_set_tristate(pingroup, tristate);
645 pr_err("pinmux: can't set pingroup %s tristate"
646 " to %s: %d\n", pingroup_name(pingroup),
647 tri_name(tristate), err);
652 void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *config,
653 int len, enum tegra_pullupdown pupd)
657 enum tegra_pingroup pingroup;
659 for (i = 0; i < len; i++) {
660 pingroup = config[i].pingroup;
661 if (pingroups[pingroup].pupd_reg >= 0) {
662 err = tegra_pinmux_set_pullupdown(pingroup, pupd);
664 pr_err("pinmux: can't set pingroup %s pullupdown"
665 " to %s: %d\n", pingroup_name(pingroup),
666 pupd_name(pupd), err);
671 static int __devinit tegra_pinmux_probe(struct platform_device *pdev)
673 struct resource *res;
678 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
684 for (i = 0; i < TEGRA_MAX_PINGROUP; i++) {
685 if (pingroups[i].tri_bank >= nbanks) {
686 dev_err(&pdev->dev, "pingroup %d: bad tri_bank\n", i);
690 if (pingroups[i].mux_bank >= nbanks) {
691 dev_err(&pdev->dev, "pingroup %d: bad mux_bank\n", i);
695 if (pingroups[i].pupd_bank >= nbanks) {
696 dev_err(&pdev->dev, "pingroup %d: bad pupd_bank\n", i);
701 for (i = 0; i < TEGRA_MAX_DRIVE_PINGROUP; i++) {
702 if (drive_pingroups[i].reg_bank >= nbanks) {
704 "drive pingroup %d: bad reg_bank\n", i);
712 regs = devm_kzalloc(&pdev->dev, nbanks * sizeof(*regs), GFP_KERNEL);
714 dev_err(&pdev->dev, "Can't alloc regs pointer\n");
718 for (i = 0; i < nbanks; i++) {
719 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
721 dev_err(&pdev->dev, "Missing MEM resource\n");
725 if (!devm_request_mem_region(&pdev->dev, res->start,
727 dev_name(&pdev->dev))) {
729 "Couldn't request MEM resource %d\n", i);
733 regs[i] = devm_ioremap(&pdev->dev, res->start,
736 dev_err(&pdev->dev, "Couldn't ioremap regs %d\n", i);
744 static struct of_device_id tegra_pinmux_of_match[] __devinitdata = {
745 { .compatible = "nvidia,tegra20-pinmux", },
749 static struct platform_driver tegra_pinmux_driver = {
751 .name = "tegra-pinmux",
752 .owner = THIS_MODULE,
753 .of_match_table = tegra_pinmux_of_match,
755 .probe = tegra_pinmux_probe,
758 static int __init tegra_pinmux_init(void)
760 return platform_driver_register(&tegra_pinmux_driver);
762 postcore_initcall(tegra_pinmux_init);
764 #ifdef CONFIG_DEBUG_FS
766 #include <linux/debugfs.h>
767 #include <linux/seq_file.h>
769 static void dbg_pad_field(struct seq_file *s, int len)
777 static int dbg_pinmux_show(struct seq_file *s, void *unused)
782 for (i = 0; i < TEGRA_MAX_PINGROUP; i++) {
788 seq_printf(s, "\t{TEGRA_PINGROUP_%s", pingroups[i].name);
789 len = strlen(pingroups[i].name);
790 dbg_pad_field(s, 5 - len);
792 if (pingroups[i].mux_reg < 0) {
793 seq_printf(s, "TEGRA_MUX_NONE");
794 len = strlen("NONE");
796 reg = pg_readl(pingroups[i].mux_bank,
797 pingroups[i].mux_reg);
798 mux = (reg >> pingroups[i].mux_bit) & 0x3;
799 if (pingroups[i].funcs[mux] == TEGRA_MUX_RSVD) {
800 seq_printf(s, "TEGRA_MUX_RSVD%1lu", mux+1);
803 seq_printf(s, "TEGRA_MUX_%s",
804 tegra_mux_names[pingroups[i].funcs[mux]]);
805 len = strlen(tegra_mux_names[pingroups[i].funcs[mux]]);
808 dbg_pad_field(s, 13-len);
810 if (pingroups[i].pupd_reg < 0) {
811 seq_printf(s, "TEGRA_PUPD_NORMAL");
812 len = strlen("NORMAL");
814 reg = pg_readl(pingroups[i].pupd_bank,
815 pingroups[i].pupd_reg);
816 pupd = (reg >> pingroups[i].pupd_bit) & 0x3;
817 seq_printf(s, "TEGRA_PUPD_%s", pupd_name(pupd));
818 len = strlen(pupd_name(pupd));
820 dbg_pad_field(s, 9 - len);
822 if (pingroups[i].tri_reg < 0) {
823 seq_printf(s, "TEGRA_TRI_NORMAL");
825 reg = pg_readl(pingroups[i].tri_bank,
826 pingroups[i].tri_reg);
827 tri = (reg >> pingroups[i].tri_bit) & 0x1;
829 seq_printf(s, "TEGRA_TRI_%s", tri_name(tri));
831 seq_printf(s, "},\n");
836 static int dbg_pinmux_open(struct inode *inode, struct file *file)
838 return single_open(file, dbg_pinmux_show, &inode->i_private);
841 static const struct file_operations debug_fops = {
842 .open = dbg_pinmux_open,
845 .release = single_release,
848 static int dbg_drive_pinmux_show(struct seq_file *s, void *unused)
853 for (i = 0; i < TEGRA_MAX_DRIVE_PINGROUP; i++) {
856 seq_printf(s, "\t{TEGRA_DRIVE_PINGROUP_%s",
857 drive_pingroups[i].name);
858 len = strlen(drive_pingroups[i].name);
859 dbg_pad_field(s, 7 - len);
862 reg = pg_readl(drive_pingroups[i].reg_bank,
863 drive_pingroups[i].reg);
865 seq_printf(s, "TEGRA_HSM_ENABLE");
868 seq_printf(s, "TEGRA_HSM_DISABLE");
871 dbg_pad_field(s, 17 - len);
874 seq_printf(s, "TEGRA_SCHMITT_ENABLE");
877 seq_printf(s, "TEGRA_SCHMITT_DISABLE");
880 dbg_pad_field(s, 22 - len);
882 seq_printf(s, "TEGRA_DRIVE_%s", drive_name(LPMD(reg)));
883 len = strlen(drive_name(LPMD(reg)));
884 dbg_pad_field(s, 5 - len);
886 seq_printf(s, "TEGRA_PULL_%d", DRVDN(reg));
887 len = DRVDN(reg) < 10 ? 1 : 2;
888 dbg_pad_field(s, 2 - len);
890 seq_printf(s, "TEGRA_PULL_%d", DRVUP(reg));
891 len = DRVUP(reg) < 10 ? 1 : 2;
892 dbg_pad_field(s, 2 - len);
894 seq_printf(s, "TEGRA_SLEW_%s", slew_name(SLWR(reg)));
895 len = strlen(slew_name(SLWR(reg)));
896 dbg_pad_field(s, 7 - len);
898 seq_printf(s, "TEGRA_SLEW_%s", slew_name(SLWF(reg)));
900 seq_printf(s, "},\n");
905 static int dbg_drive_pinmux_open(struct inode *inode, struct file *file)
907 return single_open(file, dbg_drive_pinmux_show, &inode->i_private);
910 static const struct file_operations debug_drive_fops = {
911 .open = dbg_drive_pinmux_open,
914 .release = single_release,
917 static int __init tegra_pinmux_debuginit(void)
919 (void) debugfs_create_file("tegra_pinmux", S_IRUGO,
920 NULL, NULL, &debug_fops);
921 (void) debugfs_create_file("tegra_pinmux_drive", S_IRUGO,
922 NULL, NULL, &debug_drive_fops);
925 late_initcall(tegra_pinmux_debuginit);