arch/arm/mach-stmp37xx/include/mach/regs-i2c.h

   1 /*
   2  * stmp37xx: I2C register definitions
   3  *
   4  * Copyright (c) 2008 Freescale Semiconductor
   5  * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  20  */
  21 #define REGS_I2C_BASE   (STMP3XXX_REGS_BASE + 0x58000)
  22 #define REGS_I2C_PHYS   0x80058000
  23 #define REGS_I2C_SIZE   0x2000
  24
  25 #define HW_I2C_CTRL0            0x0
  26 #define BM_I2C_CTRL0_XFER_COUNT 0x0000FFFF
  27 #define BP_I2C_CTRL0_XFER_COUNT 0
  28 #define BM_I2C_CTRL0_DIRECTION  0x00010000
  29 #define BM_I2C_CTRL0_MASTER_MODE        0x00020000
  30 #define BM_I2C_CTRL0_PRE_SEND_START     0x00080000
  31 #define BM_I2C_CTRL0_POST_SEND_STOP     0x00100000
  32 #define BM_I2C_CTRL0_RETAIN_CLOCK       0x00200000
  33 #define BM_I2C_CTRL0_SEND_NAK_ON_LAST   0x02000000
  34 #define BM_I2C_CTRL0_CLKGATE    0x40000000
  35 #define BM_I2C_CTRL0_SFTRST     0x80000000
  36
  37 #define HW_I2C_TIMING0          0x10
  38
  39 #define HW_I2C_TIMING1          0x20
  40
  41 #define HW_I2C_TIMING2          0x30
  42
  43 #define HW_I2C_CTRL1            0x40
  44 #define BM_I2C_CTRL1_SLAVE_IRQ  0x00000001
  45 #define BP_I2C_CTRL1_SLAVE_IRQ  0
  46 #define BM_I2C_CTRL1_SLAVE_STOP_IRQ     0x00000002
  47 #define BM_I2C_CTRL1_MASTER_LOSS_IRQ    0x00000004
  48 #define BM_I2C_CTRL1_EARLY_TERM_IRQ     0x00000008
  49 #define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ     0x00000010
  50 #define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ   0x00000020
  51 #define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ      0x00000040
  52 #define BM_I2C_CTRL1_BUS_FREE_IRQ       0x00000080
  53 #define BM_I2C_CTRL1_CLR_GOT_A_NAK      0x10000000
  54
  55 #define HW_I2C_VERSION          0x90