arch/arm/mach-stmp378x/include/mach/regs-dcp.h

   1 /*
   2  * stmp378x: DCP register definitions
   3  *
   4  * Copyright (c) 2008 Freescale Semiconductor
   5  * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  20  */
  21 #define REGS_DCP_BASE   (STMP3XXX_REGS_BASE + 0x28000)
  22 #define REGS_DCP_PHYS   0x80028000
  23 #define REGS_DCP_SIZE   0x2000
  24
  25 #define HW_DCP_CTRL             0x0
  26 #define BM_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE    0x000000FF
  27 #define BP_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE    0
  28 #define BM_DCP_CTRL_ENABLE_CONTEXT_CACHING      0x00400000
  29 #define BM_DCP_CTRL_GATHER_RESIDUAL_WRITES      0x00800000
  30 #define BM_DCP_CTRL_CLKGATE     0x40000000
  31 #define BM_DCP_CTRL_SFTRST      0x80000000
  32
  33 #define HW_DCP_STAT             0x10
  34 #define BM_DCP_STAT_IRQ         0x0000000F
  35 #define BP_DCP_STAT_IRQ         0
  36
  37 #define HW_DCP_CHANNELCTRL      0x20
  38 #define BM_DCP_CHANNELCTRL_ENABLE_CHANNEL       0x000000FF
  39 #define BP_DCP_CHANNELCTRL_ENABLE_CHANNEL       0
  40
  41 #define HW_DCP_CONTEXT          0x50
  42 #define BM_DCP_PACKET1_INTERRUPT        0x00000001
  43 #define BP_DCP_PACKET1_INTERRUPT        0
  44 #define BM_DCP_PACKET1_DECR_SEMAPHORE   0x00000002
  45 #define BM_DCP_PACKET1_CHAIN    0x00000004
  46 #define BM_DCP_PACKET1_CHAIN_CONTIGUOUS 0x00000008
  47 #define BM_DCP_PACKET1_ENABLE_CIPHER    0x00000020
  48 #define BM_DCP_PACKET1_ENABLE_HASH      0x00000040
  49 #define BM_DCP_PACKET1_CIPHER_ENCRYPT   0x00000100
  50 #define BM_DCP_PACKET1_CIPHER_INIT      0x00000200
  51 #define BM_DCP_PACKET1_OTP_KEY  0x00000400
  52 #define BM_DCP_PACKET1_PAYLOAD_KEY      0x00000800
  53 #define BM_DCP_PACKET1_HASH_INIT        0x00001000
  54 #define BM_DCP_PACKET1_HASH_TERM        0x00002000
  55 #define BM_DCP_PACKET2_CIPHER_SELECT    0x0000000F
  56 #define BP_DCP_PACKET2_CIPHER_SELECT    0
  57 #define BM_DCP_PACKET2_CIPHER_MODE      0x000000F0
  58 #define BP_DCP_PACKET2_CIPHER_MODE      4
  59 #define BM_DCP_PACKET2_KEY_SELECT       0x0000FF00
  60 #define BP_DCP_PACKET2_KEY_SELECT       8
  61 #define BM_DCP_PACKET2_HASH_SELECT      0x000F0000
  62 #define BP_DCP_PACKET2_HASH_SELECT      16
  63 #define BM_DCP_PACKET2_CIPHER_CFG       0xFF000000
  64 #define BP_DCP_PACKET2_CIPHER_CFG       24
  65
  66 #define HW_DCP_CH0CMDPTR        (0x100 + 0 * 0x40)
  67 #define HW_DCP_CH1CMDPTR        (0x100 + 1 * 0x40)
  68 #define HW_DCP_CH2CMDPTR        (0x100 + 2 * 0x40)
  69 #define HW_DCP_CH3CMDPTR        (0x100 + 3 * 0x40)
  70
  71 #define HW_DCP_CHnCMDPTR        0x100
  72
  73 #define HW_DCP_CH0SEMA          (0x110 + 0 * 0x40)
  74 #define HW_DCP_CH1SEMA          (0x110 + 1 * 0x40)
  75 #define HW_DCP_CH2SEMA          (0x110 + 2 * 0x40)
  76 #define HW_DCP_CH3SEMA          (0x110 + 3 * 0x40)
  77
  78 #define HW_DCP_CHnSEMA          0x110
  79 #define BM_DCP_CHnSEMA_INCREMENT        0x000000FF
  80 #define BP_DCP_CHnSEMA_INCREMENT        0
  81
  82 #define HW_DCP_CH0STAT          (0x120 + 0 * 0x40)
  83 #define HW_DCP_CH1STAT          (0x120 + 1 * 0x40)
  84 #define HW_DCP_CH2STAT          (0x120 + 2 * 0x40)
  85 #define HW_DCP_CH3STAT          (0x120 + 3 * 0x40)
  86
  87 #define HW_DCP_CHnSTAT          0x120