arch/arm/mach-spear3xx/include/mach/spear310.h

   1 /*
   2  * arch/arm/mach-spear3xx/include/mach/spear310.h
   3  *
   4  * SPEAr310 Machine specific definition
   5  *
   6  * Copyright (C) 2009 ST Microelectronics
   7  * Viresh Kumar<viresh.kumar@st.com>
   8  *
   9  * This file is licensed under the terms of the GNU General Public
  10  * License version 2. This program is licensed "as is" without any
  11  * warranty of any kind, whether express or implied.
  12  */
  13
  14 #ifdef  CONFIG_MACH_SPEAR310
  15
  16 #ifndef __MACH_SPEAR310_H
  17 #define __MACH_SPEAR310_H
  18
  19 #define SPEAR310_NAND_BASE              0x40000000
  20 #define SPEAR310_NAND_SIZE              0x04000000
  21
  22 #define SPEAR310_FSMC_BASE              0x44000000
  23 #define SPEAR310_FSMC_SIZE              0x01000000
  24
  25 #define SPEAR310_UART1_BASE             0xB2000000
  26 #define SPEAR310_UART2_BASE             0xB2080000
  27 #define SPEAR310_UART3_BASE             0xB2100000
  28 #define SPEAR310_UART4_BASE             0xB2180000
  29 #define SPEAR310_UART5_BASE             0xB2200000
  30 #define SPEAR310_UART_SIZE              0x00080000
  31
  32 #define SPEAR310_HDLC_BASE              0xB2800000
  33 #define SPEAR310_HDLC_SIZE              0x00800000
  34
  35 #define SPEAR310_RS485_0_BASE           0xB3000000
  36 #define SPEAR310_RS485_0_SIZE           0x00800000
  37
  38 #define SPEAR310_RS485_1_BASE           0xB3800000
  39 #define SPEAR310_RS485_1_SIZE           0x00800000
  40
  41 #define SPEAR310_SOC_CONFIG_BASE        0xB4000000
  42 #define SPEAR310_SOC_CONFIG_SIZE        0x00000070
  43 /* Interrupt registers offsets and masks */
  44 #define INT_STS_MASK_REG                0x04
  45 #define SMII0_IRQ_MASK                  (1 << 0)
  46 #define SMII1_IRQ_MASK                  (1 << 1)
  47 #define SMII2_IRQ_MASK                  (1 << 2)
  48 #define SMII3_IRQ_MASK                  (1 << 3)
  49 #define WAKEUP_SMII0_IRQ_MASK           (1 << 4)
  50 #define WAKEUP_SMII1_IRQ_MASK           (1 << 5)
  51 #define WAKEUP_SMII2_IRQ_MASK           (1 << 6)
  52 #define WAKEUP_SMII3_IRQ_MASK           (1 << 7)
  53 #define UART1_IRQ_MASK                  (1 << 8)
  54 #define UART2_IRQ_MASK                  (1 << 9)
  55 #define UART3_IRQ_MASK                  (1 << 10)
  56 #define UART4_IRQ_MASK                  (1 << 11)
  57 #define UART5_IRQ_MASK                  (1 << 12)
  58 #define EMI_IRQ_MASK                    (1 << 13)
  59 #define TDM_HDLC_IRQ_MASK               (1 << 14)
  60 #define RS485_0_IRQ_MASK                (1 << 15)
  61 #define RS485_1_IRQ_MASK                (1 << 16)
  62
  63 #define SHIRQ_RAS1_MASK                 0x000FF
  64 #define SHIRQ_RAS2_MASK                 0x01F00
  65 #define SHIRQ_RAS3_MASK                 0x02000
  66 #define SHIRQ_INTRCOMM_RAS_MASK         0x1C000
  67
  68 #endif /* __MACH_SPEAR310_H */
  69
  70 #endif /* CONFIG_MACH_SPEAR310 */