arch/arm/mach-shmobile/setup-sh73a0.c

   1 /*
   2  * sh73a0 processor support
   3  *
   4  * Copyright (C) 2010  Takashi Yoshii
   5  * Copyright (C) 2010  Magnus Damm
   6  * Copyright (C) 2008  Yoshihiro Shimoda
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  20  */
  21 #include <linux/kernel.h>
  22 #include <linux/init.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/irq.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/delay.h>
  27 #include <linux/input.h>
  28 #include <linux/io.h>
  29 #include <linux/serial_sci.h>
  30 #include <linux/sh_dma.h>
  31 #include <linux/sh_intc.h>
  32 #include <linux/sh_timer.h>
  33 #include <mach/hardware.h>
  34 #include <mach/sh73a0.h>
  35 #include <asm/mach-types.h>
  36 #include <asm/mach/arch.h>
  37
  38 static struct plat_sci_port scif0_platform_data = {
  39         .mapbase        = 0xe6c40000,
  40         .flags          = UPF_BOOT_AUTOCONF,
  41         .scscr          = SCSCR_RE | SCSCR_TE,
  42         .scbrr_algo_id  = SCBRR_ALGO_4,
  43         .type           = PORT_SCIFA,
  44         .irqs           = { gic_spi(72), gic_spi(72),
  45                             gic_spi(72), gic_spi(72) },
  46 };
  47
  48 static struct platform_device scif0_device = {
  49         .name           = "sh-sci",
  50         .id             = 0,
  51         .dev            = {
  52                 .platform_data  = &scif0_platform_data,
  53         },
  54 };
  55
  56 static struct plat_sci_port scif1_platform_data = {
  57         .mapbase        = 0xe6c50000,
  58         .flags          = UPF_BOOT_AUTOCONF,
  59         .scscr          = SCSCR_RE | SCSCR_TE,
  60         .scbrr_algo_id  = SCBRR_ALGO_4,
  61         .type           = PORT_SCIFA,
  62         .irqs           = { gic_spi(73), gic_spi(73),
  63                             gic_spi(73), gic_spi(73) },
  64 };
  65
  66 static struct platform_device scif1_device = {
  67         .name           = "sh-sci",
  68         .id             = 1,
  69         .dev            = {
  70                 .platform_data  = &scif1_platform_data,
  71         },
  72 };
  73
  74 static struct plat_sci_port scif2_platform_data = {
  75         .mapbase        = 0xe6c60000,
  76         .flags          = UPF_BOOT_AUTOCONF,
  77         .scscr          = SCSCR_RE | SCSCR_TE,
  78         .scbrr_algo_id  = SCBRR_ALGO_4,
  79         .type           = PORT_SCIFA,
  80         .irqs           = { gic_spi(74), gic_spi(74),
  81                             gic_spi(74), gic_spi(74) },
  82 };
  83
  84 static struct platform_device scif2_device = {
  85         .name           = "sh-sci",
  86         .id             = 2,
  87         .dev            = {
  88                 .platform_data  = &scif2_platform_data,
  89         },
  90 };
  91
  92 static struct plat_sci_port scif3_platform_data = {
  93         .mapbase        = 0xe6c70000,
  94         .flags          = UPF_BOOT_AUTOCONF,
  95         .scscr          = SCSCR_RE | SCSCR_TE,
  96         .scbrr_algo_id  = SCBRR_ALGO_4,
  97         .type           = PORT_SCIFA,
  98         .irqs           = { gic_spi(75), gic_spi(75),
  99                             gic_spi(75), gic_spi(75) },
 100 };
 101
 102 static struct platform_device scif3_device = {
 103         .name           = "sh-sci",
 104         .id             = 3,
 105         .dev            = {
 106                 .platform_data  = &scif3_platform_data,
 107         },
 108 };
 109
 110 static struct plat_sci_port scif4_platform_data = {
 111         .mapbase        = 0xe6c80000,
 112         .flags          = UPF_BOOT_AUTOCONF,
 113         .scscr          = SCSCR_RE | SCSCR_TE,
 114         .scbrr_algo_id  = SCBRR_ALGO_4,
 115         .type           = PORT_SCIFA,
 116         .irqs           = { gic_spi(78), gic_spi(78),
 117                             gic_spi(78), gic_spi(78) },
 118 };
 119
 120 static struct platform_device scif4_device = {
 121         .name           = "sh-sci",
 122         .id             = 4,
 123         .dev            = {
 124                 .platform_data  = &scif4_platform_data,
 125         },
 126 };
 127
 128 static struct plat_sci_port scif5_platform_data = {
 129         .mapbase        = 0xe6cb0000,
 130         .flags          = UPF_BOOT_AUTOCONF,
 131         .scscr          = SCSCR_RE | SCSCR_TE,
 132         .scbrr_algo_id  = SCBRR_ALGO_4,
 133         .type           = PORT_SCIFA,
 134         .irqs           = { gic_spi(79), gic_spi(79),
 135                             gic_spi(79), gic_spi(79) },
 136 };
 137
 138 static struct platform_device scif5_device = {
 139         .name           = "sh-sci",
 140         .id             = 5,
 141         .dev            = {
 142                 .platform_data  = &scif5_platform_data,
 143         },
 144 };
 145
 146 static struct plat_sci_port scif6_platform_data = {
 147         .mapbase        = 0xe6cc0000,
 148         .flags          = UPF_BOOT_AUTOCONF,
 149         .scscr          = SCSCR_RE | SCSCR_TE,
 150         .scbrr_algo_id  = SCBRR_ALGO_4,
 151         .type           = PORT_SCIFA,
 152         .irqs           = { gic_spi(156), gic_spi(156),
 153                             gic_spi(156), gic_spi(156) },
 154 };
 155
 156 static struct platform_device scif6_device = {
 157         .name           = "sh-sci",
 158         .id             = 6,
 159         .dev            = {
 160                 .platform_data  = &scif6_platform_data,
 161         },
 162 };
 163
 164 static struct plat_sci_port scif7_platform_data = {
 165         .mapbase        = 0xe6cd0000,
 166         .flags          = UPF_BOOT_AUTOCONF,
 167         .scscr          = SCSCR_RE | SCSCR_TE,
 168         .scbrr_algo_id  = SCBRR_ALGO_4,
 169         .type           = PORT_SCIFA,
 170         .irqs           = { gic_spi(143), gic_spi(143),
 171                             gic_spi(143), gic_spi(143) },
 172 };
 173
 174 static struct platform_device scif7_device = {
 175         .name           = "sh-sci",
 176         .id             = 7,
 177         .dev            = {
 178                 .platform_data  = &scif7_platform_data,
 179         },
 180 };
 181
 182 static struct plat_sci_port scif8_platform_data = {
 183         .mapbase        = 0xe6c30000,
 184         .flags          = UPF_BOOT_AUTOCONF,
 185         .scscr          = SCSCR_RE | SCSCR_TE,
 186         .scbrr_algo_id  = SCBRR_ALGO_4,
 187         .type           = PORT_SCIFB,
 188         .irqs           = { gic_spi(80), gic_spi(80),
 189                             gic_spi(80), gic_spi(80) },
 190 };
 191
 192 static struct platform_device scif8_device = {
 193         .name           = "sh-sci",
 194         .id             = 8,
 195         .dev            = {
 196                 .platform_data  = &scif8_platform_data,
 197         },
 198 };
 199
 200 static struct sh_timer_config cmt10_platform_data = {
 201         .name = "CMT10",
 202         .channel_offset = 0x10,
 203         .timer_bit = 0,
 204         .clockevent_rating = 125,
 205         .clocksource_rating = 125,
 206 };
 207
 208 static struct resource cmt10_resources[] = {
 209         [0] = {
 210                 .name   = "CMT10",
 211                 .start  = 0xe6138010,
 212                 .end    = 0xe613801b,
 213                 .flags  = IORESOURCE_MEM,
 214         },
 215         [1] = {
 216                 .start  = gic_spi(65),
 217                 .flags  = IORESOURCE_IRQ,
 218         },
 219 };
 220
 221 static struct platform_device cmt10_device = {
 222         .name           = "sh_cmt",
 223         .id             = 10,
 224         .dev = {
 225                 .platform_data  = &cmt10_platform_data,
 226         },
 227         .resource       = cmt10_resources,
 228         .num_resources  = ARRAY_SIZE(cmt10_resources),
 229 };
 230
 231 /* TMU */
 232 static struct sh_timer_config tmu00_platform_data = {
 233         .name = "TMU00",
 234         .channel_offset = 0x4,
 235         .timer_bit = 0,
 236         .clockevent_rating = 200,
 237 };
 238
 239 static struct resource tmu00_resources[] = {
 240         [0] = {
 241                 .name   = "TMU00",
 242                 .start  = 0xfff60008,
 243                 .end    = 0xfff60013,
 244                 .flags  = IORESOURCE_MEM,
 245         },
 246         [1] = {
 247                 .start  = intcs_evt2irq(0x0e80), /* TMU0_TUNI00 */
 248                 .flags  = IORESOURCE_IRQ,
 249         },
 250 };
 251
 252 static struct platform_device tmu00_device = {
 253         .name           = "sh_tmu",
 254         .id             = 0,
 255         .dev = {
 256                 .platform_data  = &tmu00_platform_data,
 257         },
 258         .resource       = tmu00_resources,
 259         .num_resources  = ARRAY_SIZE(tmu00_resources),
 260 };
 261
 262 static struct sh_timer_config tmu01_platform_data = {
 263         .name = "TMU01",
 264         .channel_offset = 0x10,
 265         .timer_bit = 1,
 266         .clocksource_rating = 200,
 267 };
 268
 269 static struct resource tmu01_resources[] = {
 270         [0] = {
 271                 .name   = "TMU01",
 272                 .start  = 0xfff60014,
 273                 .end    = 0xfff6001f,
 274                 .flags  = IORESOURCE_MEM,
 275         },
 276         [1] = {
 277                 .start  = intcs_evt2irq(0x0ea0), /* TMU0_TUNI01 */
 278                 .flags  = IORESOURCE_IRQ,
 279         },
 280 };
 281
 282 static struct platform_device tmu01_device = {
 283         .name           = "sh_tmu",
 284         .id             = 1,
 285         .dev = {
 286                 .platform_data  = &tmu01_platform_data,
 287         },
 288         .resource       = tmu01_resources,
 289         .num_resources  = ARRAY_SIZE(tmu01_resources),
 290 };
 291
 292 static struct resource i2c0_resources[] = {
 293         [0] = {
 294                 .name   = "IIC0",
 295                 .start  = 0xe6820000,
 296                 .end    = 0xe6820425 - 1,
 297                 .flags  = IORESOURCE_MEM,
 298         },
 299         [1] = {
 300                 .start  = gic_spi(167),
 301                 .end    = gic_spi(170),
 302                 .flags  = IORESOURCE_IRQ,
 303         },
 304 };
 305
 306 static struct resource i2c1_resources[] = {
 307         [0] = {
 308                 .name   = "IIC1",
 309                 .start  = 0xe6822000,
 310                 .end    = 0xe6822425 - 1,
 311                 .flags  = IORESOURCE_MEM,
 312         },
 313         [1] = {
 314                 .start  = gic_spi(51),
 315                 .end    = gic_spi(54),
 316                 .flags  = IORESOURCE_IRQ,
 317         },
 318 };
 319
 320 static struct resource i2c2_resources[] = {
 321         [0] = {
 322                 .name   = "IIC2",
 323                 .start  = 0xe6824000,
 324                 .end    = 0xe6824425 - 1,
 325                 .flags  = IORESOURCE_MEM,
 326         },
 327         [1] = {
 328                 .start  = gic_spi(171),
 329                 .end    = gic_spi(174),
 330                 .flags  = IORESOURCE_IRQ,
 331         },
 332 };
 333
 334 static struct resource i2c3_resources[] = {
 335         [0] = {
 336                 .name   = "IIC3",
 337                 .start  = 0xe6826000,
 338                 .end    = 0xe6826425 - 1,
 339                 .flags  = IORESOURCE_MEM,
 340         },
 341         [1] = {
 342                 .start  = gic_spi(183),
 343                 .end    = gic_spi(186),
 344                 .flags  = IORESOURCE_IRQ,
 345         },
 346 };
 347
 348 static struct resource i2c4_resources[] = {
 349         [0] = {
 350                 .name   = "IIC4",
 351                 .start  = 0xe6828000,
 352                 .end    = 0xe6828425 - 1,
 353                 .flags  = IORESOURCE_MEM,
 354         },
 355         [1] = {
 356                 .start  = gic_spi(187),
 357                 .end    = gic_spi(190),
 358                 .flags  = IORESOURCE_IRQ,
 359         },
 360 };
 361
 362 static struct platform_device i2c0_device = {
 363         .name           = "i2c-sh_mobile",
 364         .id             = 0,
 365         .resource       = i2c0_resources,
 366         .num_resources  = ARRAY_SIZE(i2c0_resources),
 367 };
 368
 369 static struct platform_device i2c1_device = {
 370         .name           = "i2c-sh_mobile",
 371         .id             = 1,
 372         .resource       = i2c1_resources,
 373         .num_resources  = ARRAY_SIZE(i2c1_resources),
 374 };
 375
 376 static struct platform_device i2c2_device = {
 377         .name           = "i2c-sh_mobile",
 378         .id             = 2,
 379         .resource       = i2c2_resources,
 380         .num_resources  = ARRAY_SIZE(i2c2_resources),
 381 };
 382
 383 static struct platform_device i2c3_device = {
 384         .name           = "i2c-sh_mobile",
 385         .id             = 3,
 386         .resource       = i2c3_resources,
 387         .num_resources  = ARRAY_SIZE(i2c3_resources),
 388 };
 389
 390 static struct platform_device i2c4_device = {
 391         .name           = "i2c-sh_mobile",
 392         .id             = 4,
 393         .resource       = i2c4_resources,
 394         .num_resources  = ARRAY_SIZE(i2c4_resources),
 395 };
 396
 397 /* Transmit sizes and respective CHCR register values */
 398 enum {
 399         XMIT_SZ_8BIT            = 0,
 400         XMIT_SZ_16BIT           = 1,
 401         XMIT_SZ_32BIT           = 2,
 402         XMIT_SZ_64BIT           = 7,
 403         XMIT_SZ_128BIT          = 3,
 404         XMIT_SZ_256BIT          = 4,
 405         XMIT_SZ_512BIT          = 5,
 406 };
 407
 408 /* log2(size / 8) - used to calculate number of transfers */
 409 #define TS_SHIFT {                      \
 410         [XMIT_SZ_8BIT]          = 0,    \
 411         [XMIT_SZ_16BIT]         = 1,    \
 412         [XMIT_SZ_32BIT]         = 2,    \
 413         [XMIT_SZ_64BIT]         = 3,    \
 414         [XMIT_SZ_128BIT]        = 4,    \
 415         [XMIT_SZ_256BIT]        = 5,    \
 416         [XMIT_SZ_512BIT]        = 6,    \
 417 }
 418
 419 #define TS_INDEX2VAL(i) ((((i) & 3) << 3) | (((i) & 0xc) << (20 - 2)))
 420 #define CHCR_TX(xmit_sz) (DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL((xmit_sz)))
 421 #define CHCR_RX(xmit_sz) (DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL((xmit_sz)))
 422
 423 static const struct sh_dmae_slave_config sh73a0_dmae_slaves[] = {
 424         {
 425                 .slave_id       = SHDMA_SLAVE_SCIF0_TX,
 426                 .addr           = 0xe6c40020,
 427                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 428                 .mid_rid        = 0x21,
 429         }, {
 430                 .slave_id       = SHDMA_SLAVE_SCIF0_RX,
 431                 .addr           = 0xe6c40024,
 432                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 433                 .mid_rid        = 0x22,
 434         }, {
 435                 .slave_id       = SHDMA_SLAVE_SCIF1_TX,
 436                 .addr           = 0xe6c50020,
 437                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 438                 .mid_rid        = 0x25,
 439         }, {
 440                 .slave_id       = SHDMA_SLAVE_SCIF1_RX,
 441                 .addr           = 0xe6c50024,
 442                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 443                 .mid_rid        = 0x26,
 444         }, {
 445                 .slave_id       = SHDMA_SLAVE_SCIF2_TX,
 446                 .addr           = 0xe6c60020,
 447                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 448                 .mid_rid        = 0x29,
 449         }, {
 450                 .slave_id       = SHDMA_SLAVE_SCIF2_RX,
 451                 .addr           = 0xe6c60024,
 452                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 453                 .mid_rid        = 0x2a,
 454         }, {
 455                 .slave_id       = SHDMA_SLAVE_SCIF3_TX,
 456                 .addr           = 0xe6c70020,
 457                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 458                 .mid_rid        = 0x2d,
 459         }, {
 460                 .slave_id       = SHDMA_SLAVE_SCIF3_RX,
 461                 .addr           = 0xe6c70024,
 462                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 463                 .mid_rid        = 0x2e,
 464         }, {
 465                 .slave_id       = SHDMA_SLAVE_SCIF4_TX,
 466                 .addr           = 0xe6c80020,
 467                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 468                 .mid_rid        = 0x39,
 469         }, {
 470                 .slave_id       = SHDMA_SLAVE_SCIF4_RX,
 471                 .addr           = 0xe6c80024,
 472                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 473                 .mid_rid        = 0x3a,
 474         }, {
 475                 .slave_id       = SHDMA_SLAVE_SCIF5_TX,
 476                 .addr           = 0xe6cb0020,
 477                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 478                 .mid_rid        = 0x35,
 479         }, {
 480                 .slave_id       = SHDMA_SLAVE_SCIF5_RX,
 481                 .addr           = 0xe6cb0024,
 482                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 483                 .mid_rid        = 0x36,
 484         }, {
 485                 .slave_id       = SHDMA_SLAVE_SCIF6_TX,
 486                 .addr           = 0xe6cc0020,
 487                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 488                 .mid_rid        = 0x1d,
 489         }, {
 490                 .slave_id       = SHDMA_SLAVE_SCIF6_RX,
 491                 .addr           = 0xe6cc0024,
 492                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 493                 .mid_rid        = 0x1e,
 494         }, {
 495                 .slave_id       = SHDMA_SLAVE_SCIF7_TX,
 496                 .addr           = 0xe6cd0020,
 497                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 498                 .mid_rid        = 0x19,
 499         }, {
 500                 .slave_id       = SHDMA_SLAVE_SCIF7_RX,
 501                 .addr           = 0xe6cd0024,
 502                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 503                 .mid_rid        = 0x1a,
 504         }, {
 505                 .slave_id       = SHDMA_SLAVE_SCIF8_TX,
 506                 .addr           = 0xe6c30040,
 507                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 508                 .mid_rid        = 0x3d,
 509         }, {
 510                 .slave_id       = SHDMA_SLAVE_SCIF8_RX,
 511                 .addr           = 0xe6c30060,
 512                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 513                 .mid_rid        = 0x3e,
 514         }, {
 515                 .slave_id       = SHDMA_SLAVE_SDHI0_TX,
 516                 .addr           = 0xee100030,
 517                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 518                 .mid_rid        = 0xc1,
 519         }, {
 520                 .slave_id       = SHDMA_SLAVE_SDHI0_RX,
 521                 .addr           = 0xee100030,
 522                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 523                 .mid_rid        = 0xc2,
 524         }, {
 525                 .slave_id       = SHDMA_SLAVE_SDHI1_TX,
 526                 .addr           = 0xee120030,
 527                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 528                 .mid_rid        = 0xc9,
 529         }, {
 530                 .slave_id       = SHDMA_SLAVE_SDHI1_RX,
 531                 .addr           = 0xee120030,
 532                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 533                 .mid_rid        = 0xca,
 534         }, {
 535                 .slave_id       = SHDMA_SLAVE_SDHI2_TX,
 536                 .addr           = 0xee140030,
 537                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 538                 .mid_rid        = 0xcd,
 539         }, {
 540                 .slave_id       = SHDMA_SLAVE_SDHI2_RX,
 541                 .addr           = 0xee140030,
 542                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 543                 .mid_rid        = 0xce,
 544         }, {
 545                 .slave_id       = SHDMA_SLAVE_MMCIF_TX,
 546                 .addr           = 0xe6bd0034,
 547                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 548                 .mid_rid        = 0xd1,
 549         }, {
 550                 .slave_id       = SHDMA_SLAVE_MMCIF_RX,
 551                 .addr           = 0xe6bd0034,
 552                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 553                 .mid_rid        = 0xd2,
 554         },
 555 };
 556
 557 #define DMAE_CHANNEL(_offset)                                   \
 558         {                                                       \
 559                 .offset         = _offset - 0x20,               \
 560                 .dmars          = _offset - 0x20 + 0x40,        \
 561         }
 562
 563 static const struct sh_dmae_channel sh73a0_dmae_channels[] = {
 564         DMAE_CHANNEL(0x8000),
 565         DMAE_CHANNEL(0x8080),
 566         DMAE_CHANNEL(0x8100),
 567         DMAE_CHANNEL(0x8180),
 568         DMAE_CHANNEL(0x8200),
 569         DMAE_CHANNEL(0x8280),
 570         DMAE_CHANNEL(0x8300),
 571         DMAE_CHANNEL(0x8380),
 572         DMAE_CHANNEL(0x8400),
 573         DMAE_CHANNEL(0x8480),
 574         DMAE_CHANNEL(0x8500),
 575         DMAE_CHANNEL(0x8580),
 576         DMAE_CHANNEL(0x8600),
 577         DMAE_CHANNEL(0x8680),
 578         DMAE_CHANNEL(0x8700),
 579         DMAE_CHANNEL(0x8780),
 580         DMAE_CHANNEL(0x8800),
 581         DMAE_CHANNEL(0x8880),
 582         DMAE_CHANNEL(0x8900),
 583         DMAE_CHANNEL(0x8980),
 584 };
 585
 586 static const unsigned int ts_shift[] = TS_SHIFT;
 587
 588 static struct sh_dmae_pdata sh73a0_dmae_platform_data = {
 589         .slave          = sh73a0_dmae_slaves,
 590         .slave_num      = ARRAY_SIZE(sh73a0_dmae_slaves),
 591         .channel        = sh73a0_dmae_channels,
 592         .channel_num    = ARRAY_SIZE(sh73a0_dmae_channels),
 593         .ts_low_shift   = 3,
 594         .ts_low_mask    = 0x18,
 595         .ts_high_shift  = (20 - 2),     /* 2 bits for shifted low TS */
 596         .ts_high_mask   = 0x00300000,
 597         .ts_shift       = ts_shift,
 598         .ts_shift_num   = ARRAY_SIZE(ts_shift),
 599         .dmaor_init     = DMAOR_DME,
 600 };
 601
 602 static struct resource sh73a0_dmae_resources[] = {
 603         {
 604                 /* Registers including DMAOR and channels including DMARSx */
 605                 .start  = 0xfe000020,
 606                 .end    = 0xfe008a00 - 1,
 607                 .flags  = IORESOURCE_MEM,
 608         },
 609         {
 610                 /* DMA error IRQ */
 611                 .start  = gic_spi(129),
 612                 .end    = gic_spi(129),
 613                 .flags  = IORESOURCE_IRQ,
 614         },
 615         {
 616                 /* IRQ for channels 0-19 */
 617                 .start  = gic_spi(109),
 618                 .end    = gic_spi(128),
 619                 .flags  = IORESOURCE_IRQ,
 620         },
 621 };
 622
 623 static struct platform_device dma0_device = {
 624         .name           = "sh-dma-engine",
 625         .id             = 0,
 626         .resource       = sh73a0_dmae_resources,
 627         .num_resources  = ARRAY_SIZE(sh73a0_dmae_resources),
 628         .dev            = {
 629                 .platform_data  = &sh73a0_dmae_platform_data,
 630         },
 631 };
 632
 633 static struct platform_device *sh73a0_early_devices[] __initdata = {
 634         &scif0_device,
 635         &scif1_device,
 636         &scif2_device,
 637         &scif3_device,
 638         &scif4_device,
 639         &scif5_device,
 640         &scif6_device,
 641         &scif7_device,
 642         &scif8_device,
 643         &cmt10_device,
 644         &tmu00_device,
 645         &tmu01_device,
 646 };
 647
 648 static struct platform_device *sh73a0_late_devices[] __initdata = {
 649         &i2c0_device,
 650         &i2c1_device,
 651         &i2c2_device,
 652         &i2c3_device,
 653         &i2c4_device,
 654         &dma0_device,
 655 };
 656
 657 #define SRCR2          0xe61580b0
 658
 659 void __init sh73a0_add_standard_devices(void)
 660 {
 661         /* Clear software reset bit on SY-DMAC module */
 662         __raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2);
 663
 664         platform_add_devices(sh73a0_early_devices,
 665                             ARRAY_SIZE(sh73a0_early_devices));
 666         platform_add_devices(sh73a0_late_devices,
 667                             ARRAY_SIZE(sh73a0_late_devices));
 668 }
 669
 670 void __init sh73a0_add_early_devices(void)
 671 {
 672         early_platform_add_devices(sh73a0_early_devices,
 673                                    ARRAY_SIZE(sh73a0_early_devices));
 674 }