arch/arm/mach-s5pv310/irq-combiner.c

   1 /* linux/arch/arm/mach-s5pv310/irq-combiner.c
   2  *
   3  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * Based on arch/arm/common/gic.c
   7  *
   8  * IRQ COMBINER support
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13 */
  14
  15 #include <linux/io.h>
  16
  17 #include <asm/mach/irq.h>
  18
  19 #define COMBINER_ENABLE_SET     0x0
  20 #define COMBINER_ENABLE_CLEAR   0x4
  21 #define COMBINER_INT_STATUS     0xC
  22
  23 static DEFINE_SPINLOCK(irq_controller_lock);
  24
  25 struct combiner_chip_data {
  26         unsigned int irq_offset;
  27         void __iomem *base;
  28 };
  29
  30 static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
  31
  32 static inline void __iomem *combiner_base(unsigned int irq)
  33 {
  34         struct combiner_chip_data *combiner_data = get_irq_chip_data(irq);
  35         return combiner_data->base;
  36 }
  37
  38 static void combiner_mask_irq(unsigned int irq)
  39 {
  40         u32 mask = 1 << (irq % 32);
  41
  42         __raw_writel(mask, combiner_base(irq) + COMBINER_ENABLE_CLEAR);
  43 }
  44
  45 static void combiner_unmask_irq(unsigned int irq)
  46 {
  47         u32 mask = 1 << (irq % 32);
  48
  49         __raw_writel(mask, combiner_base(irq) + COMBINER_ENABLE_SET);
  50 }
  51
  52 static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
  53 {
  54         struct combiner_chip_data *chip_data = get_irq_data(irq);
  55         struct irq_chip *chip = get_irq_chip(irq);
  56         unsigned int cascade_irq, combiner_irq;
  57         unsigned long status;
  58
  59         /* primary controller ack'ing */
  60         chip->ack(irq);
  61
  62         spin_lock(&irq_controller_lock);
  63         status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
  64         spin_unlock(&irq_controller_lock);
  65
  66         if (status == 0)
  67                 goto out;
  68
  69         combiner_irq = __ffs(status);
  70
  71         cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
  72         if (unlikely(cascade_irq >= NR_IRQS))
  73                 do_bad_IRQ(cascade_irq, desc);
  74         else
  75                 generic_handle_irq(cascade_irq);
  76
  77  out:
  78         /* primary controller unmasking */
  79         chip->unmask(irq);
  80 }
  81
  82 static struct irq_chip combiner_chip = {
  83         .name           = "COMBINER",
  84         .mask           = combiner_mask_irq,
  85         .unmask         = combiner_unmask_irq,
  86 };
  87
  88 void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
  89 {
  90         if (combiner_nr >= MAX_COMBINER_NR)
  91                 BUG();
  92         if (set_irq_data(irq, &combiner_data[combiner_nr]) != 0)
  93                 BUG();
  94         set_irq_chained_handler(irq, combiner_handle_cascade_irq);
  95 }
  96
  97 void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
  98                           unsigned int irq_start)
  99 {
 100         unsigned int i;
 101
 102         if (combiner_nr >= MAX_COMBINER_NR)
 103                 BUG();
 104
 105         combiner_data[combiner_nr].base = base;
 106         combiner_data[combiner_nr].irq_offset = irq_start;
 107
 108         /* Disable all interrupts */
 109
 110         __raw_writel(0xffffffff, base + COMBINER_ENABLE_CLEAR);
 111
 112         /* Setup the Linux IRQ subsystem */
 113
 114         for (i = irq_start; i < combiner_data[combiner_nr].irq_offset
 115                                 + MAX_IRQ_IN_COMBINER; i++) {
 116                 set_irq_chip(i, &combiner_chip);
 117                 set_irq_chip_data(i, &combiner_data[combiner_nr]);
 118                 set_irq_handler(i, handle_level_irq);
 119                 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 120         }
 121 }