arch/arm/mach-s5pv310/include/mach/map.h

   1 /* linux/arch/arm/mach-s5pv310/include/mach/map.h
   2  *
   3  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com/
   5  *
   6  * S5PV310 - Memory map definitions
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #ifndef __ASM_ARCH_MAP_H
  14 #define __ASM_ARCH_MAP_H __FILE__
  15
  16 #include <plat/map-base.h>
  17
  18 /*
  19  * S5PV310 UART offset is 0x10000 but the older S5P SoCs are 0x400.
  20  * So need to define it, and here is to avoid redefinition warning.
  21  */
  22 #define S3C_UART_OFFSET                 (0x10000)
  23
  24 #include <plat/map-s5p.h>
  25
  26 #define S5PV310_PA_SYSRAM               (0x02025000)
  27
  28 #define S5PV310_PA_SROM_BANK(x)         (0x04000000 + ((x) * 0x01000000))
  29
  30 #define S5PC210_PA_ONENAND              (0x0C000000)
  31 #define S5P_PA_ONENAND                  S5PC210_PA_ONENAND
  32
  33 #define S5PC210_PA_ONENAND_DMA          (0x0C600000)
  34 #define S5P_PA_ONENAND_DMA              S5PC210_PA_ONENAND_DMA
  35
  36 #define S5PV310_PA_CHIPID               (0x10000000)
  37 #define S5P_PA_CHIPID                   S5PV310_PA_CHIPID
  38
  39 #define S5PV310_PA_SYSCON               (0x10010000)
  40 #define S5P_PA_SYSCON                   S5PV310_PA_SYSCON
  41
  42 #define S5PV310_PA_CMU                  (0x10030000)
  43
  44 #define S5PV310_PA_WATCHDOG             (0x10060000)
  45 #define S5PV310_PA_RTC                  (0x10070000)
  46
  47 #define S5PV310_PA_COMBINER             (0x10448000)
  48
  49 #define S5PV310_PA_COREPERI             (0x10500000)
  50 #define S5PV310_PA_GIC_CPU              (0x10500100)
  51 #define S5PV310_PA_TWD                  (0x10500600)
  52 #define S5PV310_PA_GIC_DIST             (0x10501000)
  53 #define S5PV310_PA_L2CC                 (0x10502000)
  54
  55 /* DMA */
  56 #define S5PV310_PA_MDMA         0x10810000
  57 #define S5PV310_PA_PDMA0        0x12680000
  58 #define S5PV310_PA_PDMA1        0x12690000
  59
  60 #define S5PV310_PA_GPIO1                (0x11400000)
  61 #define S5PV310_PA_GPIO2                (0x11000000)
  62 #define S5PV310_PA_GPIO3                (0x03860000)
  63
  64 #define S5PV310_PA_HSMMC(x)             (0x12510000 + ((x) * 0x10000))
  65
  66 #define S5PV310_PA_SROMC                (0x12570000)
  67
  68 /* S/PDIF */
  69 #define S5PV310_PA_SPDIF        0xE1100000
  70
  71 /* I2S */
  72 #define S5PV310_PA_I2S0         0x03830000
  73 #define S5PV310_PA_I2S1         0xE3100000
  74 #define S5PV310_PA_I2S2         0xE2A00000
  75
  76 /* PCM */
  77 #define S5PV310_PA_PCM0         0x03840000
  78 #define S5PV310_PA_PCM1         0x13980000
  79 #define S5PV310_PA_PCM2         0x13990000
  80
  81 /* AC97 */
  82 #define S5PV310_PA_AC97         0x139A0000
  83
  84 #define S5PV310_PA_UART                 (0x13800000)
  85
  86 #define S5P_PA_UART(x)                  (S5PV310_PA_UART + ((x) * S3C_UART_OFFSET))
  87 #define S5P_PA_UART0                    S5P_PA_UART(0)
  88 #define S5P_PA_UART1                    S5P_PA_UART(1)
  89 #define S5P_PA_UART2                    S5P_PA_UART(2)
  90 #define S5P_PA_UART3                    S5P_PA_UART(3)
  91 #define S5P_PA_UART4                    S5P_PA_UART(4)
  92
  93 #define S5P_SZ_UART                     SZ_256
  94
  95 #define S5PV310_PA_IIC(x)               (0x13860000 + ((x) * 0x10000))
  96
  97 #define S5PV310_PA_TIMER                (0x139D0000)
  98 #define S5P_PA_TIMER                    S5PV310_PA_TIMER
  99
 100 #define S5PV310_PA_SDRAM                (0x40000000)
 101 #define S5P_PA_SDRAM                    S5PV310_PA_SDRAM
 102
 103 /* compatibiltiy defines. */
 104 #define S3C_PA_UART                     S5PV310_PA_UART
 105 #define S3C_PA_HSMMC0                   S5PV310_PA_HSMMC(0)
 106 #define S3C_PA_HSMMC1                   S5PV310_PA_HSMMC(1)
 107 #define S3C_PA_HSMMC2                   S5PV310_PA_HSMMC(2)
 108 #define S3C_PA_HSMMC3                   S5PV310_PA_HSMMC(3)
 109 #define S3C_PA_IIC                      S5PV310_PA_IIC(0)
 110 #define S3C_PA_IIC1                     S5PV310_PA_IIC(1)
 111 #define S3C_PA_IIC2                     S5PV310_PA_IIC(2)
 112 #define S3C_PA_IIC3                     S5PV310_PA_IIC(3)
 113 #define S3C_PA_IIC4                     S5PV310_PA_IIC(4)
 114 #define S3C_PA_IIC5                     S5PV310_PA_IIC(5)
 115 #define S3C_PA_IIC6                     S5PV310_PA_IIC(6)
 116 #define S3C_PA_IIC7                     S5PV310_PA_IIC(7)
 117 #define S3C_PA_RTC                      S5PV310_PA_RTC
 118 #define S3C_PA_WDT                      S5PV310_PA_WATCHDOG
 119
 120 #endif /* __ASM_ARCH_MAP_H */