arch/arm/mach-s5pv310/cpu.c

   1 /* linux/arch/arm/mach-s5pv310/cpu.c
   2  *
   3  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com/
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9 */
  10
  11 #include <linux/sched.h>
  12 #include <linux/sysdev.h>
  13
  14 #include <asm/mach/map.h>
  15 #include <asm/mach/irq.h>
  16
  17 #include <asm/proc-fns.h>
  18 #include <asm/hardware/cache-l2x0.h>
  19
  20 #include <plat/cpu.h>
  21 #include <plat/clock.h>
  22 #include <plat/s5pv310.h>
  23 #include <plat/sdhci.h>
  24
  25 #include <mach/regs-irq.h>
  26
  27 extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
  28                          unsigned int irq_start);
  29 extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
  30
  31 /* Initial IO mappings */
  32 static struct map_desc s5pv310_iodesc[] __initdata = {
  33         {
  34                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
  35                 .pfn            = __phys_to_pfn(S5PV310_PA_SYSRAM),
  36                 .length         = SZ_4K,
  37                 .type           = MT_DEVICE,
  38         }, {
  39                 .virtual        = (unsigned long)S5P_VA_CMU,
  40                 .pfn            = __phys_to_pfn(S5PV310_PA_CMU),
  41                 .length         = SZ_128K,
  42                 .type           = MT_DEVICE,
  43         }, {
  44                 .virtual        = (unsigned long)S5P_VA_PMU,
  45                 .pfn            = __phys_to_pfn(S5PV310_PA_PMU),
  46                 .length         = SZ_64K,
  47                 .type           = MT_DEVICE,
  48         }, {
  49                 .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
  50                 .pfn            = __phys_to_pfn(S5PV310_PA_COMBINER),
  51                 .length         = SZ_4K,
  52                 .type           = MT_DEVICE,
  53         }, {
  54                 .virtual        = (unsigned long)S5P_VA_COREPERI_BASE,
  55                 .pfn            = __phys_to_pfn(S5PV310_PA_COREPERI),
  56                 .length         = SZ_8K,
  57                 .type           = MT_DEVICE,
  58         }, {
  59                 .virtual        = (unsigned long)S5P_VA_L2CC,
  60                 .pfn            = __phys_to_pfn(S5PV310_PA_L2CC),
  61                 .length         = SZ_4K,
  62                 .type           = MT_DEVICE,
  63         }, {
  64                 .virtual        = (unsigned long)S5P_VA_GPIO1,
  65                 .pfn            = __phys_to_pfn(S5PV310_PA_GPIO1),
  66                 .length         = SZ_4K,
  67                 .type           = MT_DEVICE,
  68         }, {
  69                 .virtual        = (unsigned long)S5P_VA_GPIO2,
  70                 .pfn            = __phys_to_pfn(S5PV310_PA_GPIO2),
  71                 .length         = SZ_4K,
  72                 .type           = MT_DEVICE,
  73         }, {
  74                 .virtual        = (unsigned long)S5P_VA_GPIO3,
  75                 .pfn            = __phys_to_pfn(S5PV310_PA_GPIO3),
  76                 .length         = SZ_256,
  77                 .type           = MT_DEVICE,
  78         }, {
  79                 .virtual        = (unsigned long)S5P_VA_DMC0,
  80                 .pfn            = __phys_to_pfn(S5PV310_PA_DMC0),
  81                 .length         = SZ_4K,
  82                 .type           = MT_DEVICE,
  83         }, {
  84                 .virtual        = (unsigned long)S3C_VA_UART,
  85                 .pfn            = __phys_to_pfn(S3C_PA_UART),
  86                 .length         = SZ_512K,
  87                 .type           = MT_DEVICE,
  88         }, {
  89                 .virtual        = (unsigned long)S5P_VA_SROMC,
  90                 .pfn            = __phys_to_pfn(S5PV310_PA_SROMC),
  91                 .length         = SZ_4K,
  92                 .type           = MT_DEVICE,
  93         },
  94 };
  95
  96 static void s5pv310_idle(void)
  97 {
  98         if (!need_resched())
  99                 cpu_do_idle();
 100
 101         local_irq_enable();
 102 }
 103
 104 /* s5pv310_map_io
 105  *
 106  * register the standard cpu IO areas
 107 */
 108 void __init s5pv310_map_io(void)
 109 {
 110         iotable_init(s5pv310_iodesc, ARRAY_SIZE(s5pv310_iodesc));
 111
 112         /* initialize device information early */
 113         s5pv310_default_sdhci0();
 114         s5pv310_default_sdhci1();
 115         s5pv310_default_sdhci2();
 116         s5pv310_default_sdhci3();
 117 }
 118
 119 void __init s5pv310_init_clocks(int xtal)
 120 {
 121         printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
 122
 123         s3c24xx_register_baseclocks(xtal);
 124         s5p_register_clocks(xtal);
 125         s5pv310_register_clocks();
 126         s5pv310_setup_clocks();
 127 }
 128
 129 void __init s5pv310_init_irq(void)
 130 {
 131         int irq;
 132
 133         gic_init(0, IRQ_LOCALTIMER, S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
 134
 135         for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
 136
 137                 /*
 138                  * From SPI(0) to SPI(39) and SPI(51), SPI(53) are
 139                  * connected to the interrupt combiner. These irqs
 140                  * should be initialized to support cascade interrupt.
 141                  */
 142                 if ((irq >= 40) && !(irq == 51) && !(irq == 53))
 143                         continue;
 144
 145                 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
 146                                 COMBINER_IRQ(irq, 0));
 147                 combiner_cascade_irq(irq, IRQ_SPI(irq));
 148         }
 149
 150         /* The parameters of s5p_init_irq() are for VIC init.
 151          * Theses parameters should be NULL and 0 because S5PV310
 152          * uses GIC instead of VIC.
 153          */
 154         s5p_init_irq(NULL, 0);
 155 }
 156
 157 struct sysdev_class s5pv310_sysclass = {
 158         .name   = "s5pv310-core",
 159 };
 160
 161 static struct sys_device s5pv310_sysdev = {
 162         .cls    = &s5pv310_sysclass,
 163 };
 164
 165 static int __init s5pv310_core_init(void)
 166 {
 167         return sysdev_class_register(&s5pv310_sysclass);
 168 }
 169
 170 core_initcall(s5pv310_core_init);
 171
 172 #ifdef CONFIG_CACHE_L2X0
 173 static int __init s5pv310_l2x0_cache_init(void)
 174 {
 175         /* TAG, Data Latency Control: 2cycle */
 176         __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
 177         __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
 178
 179         /* L2X0 Prefetch Control */
 180         __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
 181
 182         /* L2X0 Power Control */
 183         __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
 184                      S5P_VA_L2CC + L2X0_POWER_CTRL);
 185
 186         l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
 187
 188         return 0;
 189 }
 190
 191 early_initcall(s5pv310_l2x0_cache_init);
 192 #endif
 193
 194 int __init s5pv310_init(void)
 195 {
 196         printk(KERN_INFO "S5PV310: Initializing architecture\n");
 197
 198         /* set idle function */
 199         pm_idle = s5pv310_idle;
 200
 201         return sysdev_register(&s5pv310_sysdev);
 202 }