arch/arm/mach-s5pv210/cpufreq.c

   1 /* linux/arch/arm/mach-s5pv210/cpufreq.c
   2  *
   3  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * CPU frequency scaling for S5PC110/S5PV210
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #include <linux/types.h>
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/err.h>
  17 #include <linux/clk.h>
  18 #include <linux/io.h>
  19 #include <linux/cpufreq.h>
  20
  21 #include <mach/map.h>
  22 #include <mach/regs-clock.h>
  23
  24 static struct clk *cpu_clk;
  25 static struct clk *dmc0_clk;
  26 static struct clk *dmc1_clk;
  27 static struct cpufreq_freqs freqs;
  28
  29 /* APLL M,P,S values for 1G/800Mhz */
  30 #define APLL_VAL_1000   ((1 << 31) | (125 << 16) | (3 << 8) | 1)
  31 #define APLL_VAL_800    ((1 << 31) | (100 << 16) | (3 << 8) | 1)
  32
  33 /*
  34  * DRAM configurations to calculate refresh counter for changing
  35  * frequency of memory.
  36  */
  37 struct dram_conf {
  38         unsigned long freq;     /* HZ */
  39         unsigned long refresh;  /* DRAM refresh counter * 1000 */
  40 };
  41
  42 /* DRAM configuration (DMC0 and DMC1) */
  43 static struct dram_conf s5pv210_dram_conf[2];
  44
  45 enum perf_level {
  46         L0, L1, L2, L3, L4,
  47 };
  48
  49 enum s5pv210_mem_type {
  50         LPDDR   = 0x1,
  51         LPDDR2  = 0x2,
  52         DDR2    = 0x4,
  53 };
  54
  55 enum s5pv210_dmc_port {
  56         DMC0 = 0,
  57         DMC1,
  58 };
  59
  60 static struct cpufreq_frequency_table s5pv210_freq_table[] = {
  61         {L0, 1000*1000},
  62         {L1, 800*1000},
  63         {L2, 400*1000},
  64         {L3, 200*1000},
  65         {L4, 100*1000},
  66         {0, CPUFREQ_TABLE_END},
  67 };
  68
  69 static u32 clkdiv_val[5][11] = {
  70         /*
  71          * Clock divider value for following
  72          * { APLL, A2M, HCLK_MSYS, PCLK_MSYS,
  73          *   HCLK_DSYS, PCLK_DSYS, HCLK_PSYS, PCLK_PSYS,
  74          *   ONEDRAM, MFC, G3D }
  75          */
  76
  77         /* L0 : [1000/200/100][166/83][133/66][200/200] */
  78         {0, 4, 4, 1, 3, 1, 4, 1, 3, 0, 0},
  79
  80         /* L1 : [800/200/100][166/83][133/66][200/200] */
  81         {0, 3, 3, 1, 3, 1, 4, 1, 3, 0, 0},
  82
  83         /* L2 : [400/200/100][166/83][133/66][200/200] */
  84         {1, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0},
  85
  86         /* L3 : [200/200/100][166/83][133/66][200/200] */
  87         {3, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0},
  88
  89         /* L4 : [100/100/100][83/83][66/66][100/100] */
  90         {7, 7, 0, 0, 7, 0, 9, 0, 7, 0, 0},
  91 };
  92
  93 /*
  94  * This function set DRAM refresh counter
  95  * accoriding to operating frequency of DRAM
  96  * ch: DMC port number 0 or 1
  97  * freq: Operating frequency of DRAM(KHz)
  98  */
  99 static void s5pv210_set_refresh(enum s5pv210_dmc_port ch, unsigned long freq)
 100 {
 101         unsigned long tmp, tmp1;
 102         void __iomem *reg = NULL;
 103
 104         if (ch == DMC0) {
 105                 reg = (S5P_VA_DMC0 + 0x30);
 106         } else if (ch == DMC1) {
 107                 reg = (S5P_VA_DMC1 + 0x30);
 108         } else {
 109                 printk(KERN_ERR "Cannot find DMC port\n");
 110                 return;
 111         }
 112
 113         /* Find current DRAM frequency */
 114         tmp = s5pv210_dram_conf[ch].freq;
 115
 116         do_div(tmp, freq);
 117
 118         tmp1 = s5pv210_dram_conf[ch].refresh;
 119
 120         do_div(tmp1, tmp);
 121
 122         __raw_writel(tmp1, reg);
 123 }
 124
 125 int s5pv210_verify_speed(struct cpufreq_policy *policy)
 126 {
 127         if (policy->cpu)
 128                 return -EINVAL;
 129
 130         return cpufreq_frequency_table_verify(policy, s5pv210_freq_table);
 131 }
 132
 133 unsigned int s5pv210_getspeed(unsigned int cpu)
 134 {
 135         if (cpu)
 136                 return 0;
 137
 138         return clk_get_rate(cpu_clk) / 1000;
 139 }
 140
 141 static int s5pv210_target(struct cpufreq_policy *policy,
 142                           unsigned int target_freq,
 143                           unsigned int relation)
 144 {
 145         unsigned long reg;
 146         unsigned int index, priv_index;
 147         unsigned int pll_changing = 0;
 148         unsigned int bus_speed_changing = 0;
 149
 150         freqs.old = s5pv210_getspeed(0);
 151
 152         if (cpufreq_frequency_table_target(policy, s5pv210_freq_table,
 153                                            target_freq, relation, &index))
 154                 return -EINVAL;
 155
 156         freqs.new = s5pv210_freq_table[index].frequency;
 157         freqs.cpu = 0;
 158
 159         if (freqs.new == freqs.old)
 160                 return 0;
 161
 162         /* Finding current running level index */
 163         if (cpufreq_frequency_table_target(policy, s5pv210_freq_table,
 164                                            freqs.old, relation, &priv_index))
 165                 return -EINVAL;
 166
 167         cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
 168
 169         if (freqs.new > freqs.old) {
 170                 /* Voltage up: will be implemented */
 171         }
 172
 173         /* Check if there need to change PLL */
 174         if ((index == L0) || (priv_index == L0))
 175                 pll_changing = 1;
 176
 177         /* Check if there need to change System bus clock */
 178         if ((index == L4) || (priv_index == L4))
 179                 bus_speed_changing = 1;
 180
 181         if (bus_speed_changing) {
 182                 /*
 183                  * Reconfigure DRAM refresh counter value for minimum
 184                  * temporary clock while changing divider.
 185                  * expected clock is 83Mhz : 7.8usec/(1/83Mhz) = 0x287
 186                  */
 187                 if (pll_changing)
 188                         s5pv210_set_refresh(DMC1, 83000);
 189                 else
 190                         s5pv210_set_refresh(DMC1, 100000);
 191
 192                 s5pv210_set_refresh(DMC0, 83000);
 193         }
 194
 195         /*
 196          * APLL should be changed in this level
 197          * APLL -> MPLL(for stable transition) -> APLL
 198          * Some clock source's clock API are not prepared.
 199          * Do not use clock API in below code.
 200          */
 201         if (pll_changing) {
 202                 /*
 203                  * 1. Temporary Change divider for MFC and G3D
 204                  * SCLKA2M(200/1=200)->(200/4=50)Mhz
 205                  */
 206                 reg = __raw_readl(S5P_CLK_DIV2);
 207                 reg &= ~(S5P_CLKDIV2_G3D_MASK | S5P_CLKDIV2_MFC_MASK);
 208                 reg |= (3 << S5P_CLKDIV2_G3D_SHIFT) |
 209                         (3 << S5P_CLKDIV2_MFC_SHIFT);
 210                 __raw_writel(reg, S5P_CLK_DIV2);
 211
 212                 /* For MFC, G3D dividing */
 213                 do {
 214                         reg = __raw_readl(S5P_CLKDIV_STAT0);
 215                 } while (reg & ((1 << 16) | (1 << 17)));
 216
 217                 /*
 218                  * 2. Change SCLKA2M(200Mhz)to SCLKMPLL in MFC_MUX, G3D MUX
 219                  * (200/4=50)->(667/4=166)Mhz
 220                  */
 221                 reg = __raw_readl(S5P_CLK_SRC2);
 222                 reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK);
 223                 reg |= (1 << S5P_CLKSRC2_G3D_SHIFT) |
 224                         (1 << S5P_CLKSRC2_MFC_SHIFT);
 225                 __raw_writel(reg, S5P_CLK_SRC2);
 226
 227                 do {
 228                         reg = __raw_readl(S5P_CLKMUX_STAT1);
 229                 } while (reg & ((1 << 7) | (1 << 3)));
 230
 231                 /*
 232                  * 3. DMC1 refresh count for 133Mhz if (index == L4) is
 233                  * true refresh counter is already programed in upper
 234                  * code. 0x287@83Mhz
 235                  */
 236                 if (!bus_speed_changing)
 237                         s5pv210_set_refresh(DMC1, 133000);
 238
 239                 /* 4. SCLKAPLL -> SCLKMPLL */
 240                 reg = __raw_readl(S5P_CLK_SRC0);
 241                 reg &= ~(S5P_CLKSRC0_MUX200_MASK);
 242                 reg |= (0x1 << S5P_CLKSRC0_MUX200_SHIFT);
 243                 __raw_writel(reg, S5P_CLK_SRC0);
 244
 245                 do {
 246                         reg = __raw_readl(S5P_CLKMUX_STAT0);
 247                 } while (reg & (0x1 << 18));
 248
 249         }
 250
 251         /* Change divider */
 252         reg = __raw_readl(S5P_CLK_DIV0);
 253
 254         reg &= ~(S5P_CLKDIV0_APLL_MASK | S5P_CLKDIV0_A2M_MASK |
 255                 S5P_CLKDIV0_HCLK200_MASK | S5P_CLKDIV0_PCLK100_MASK |
 256                 S5P_CLKDIV0_HCLK166_MASK | S5P_CLKDIV0_PCLK83_MASK |
 257                 S5P_CLKDIV0_HCLK133_MASK | S5P_CLKDIV0_PCLK66_MASK);
 258
 259         reg |= ((clkdiv_val[index][0] << S5P_CLKDIV0_APLL_SHIFT) |
 260                 (clkdiv_val[index][1] << S5P_CLKDIV0_A2M_SHIFT) |
 261                 (clkdiv_val[index][2] << S5P_CLKDIV0_HCLK200_SHIFT) |
 262                 (clkdiv_val[index][3] << S5P_CLKDIV0_PCLK100_SHIFT) |
 263                 (clkdiv_val[index][4] << S5P_CLKDIV0_HCLK166_SHIFT) |
 264                 (clkdiv_val[index][5] << S5P_CLKDIV0_PCLK83_SHIFT) |
 265                 (clkdiv_val[index][6] << S5P_CLKDIV0_HCLK133_SHIFT) |
 266                 (clkdiv_val[index][7] << S5P_CLKDIV0_PCLK66_SHIFT));
 267
 268         __raw_writel(reg, S5P_CLK_DIV0);
 269
 270         do {
 271                 reg = __raw_readl(S5P_CLKDIV_STAT0);
 272         } while (reg & 0xff);
 273
 274         /* ARM MCS value changed */
 275         reg = __raw_readl(S5P_ARM_MCS_CON);
 276         reg &= ~0x3;
 277         if (index >= L3)
 278                 reg |= 0x3;
 279         else
 280                 reg |= 0x1;
 281
 282         __raw_writel(reg, S5P_ARM_MCS_CON);
 283
 284         if (pll_changing) {
 285                 /* 5. Set Lock time = 30us*24Mhz = 0x2cf */
 286                 __raw_writel(0x2cf, S5P_APLL_LOCK);
 287
 288                 /*
 289                  * 6. Turn on APLL
 290                  * 6-1. Set PMS values
 291                  * 6-2. Wait untile the PLL is locked
 292                  */
 293                 if (index == L0)
 294                         __raw_writel(APLL_VAL_1000, S5P_APLL_CON);
 295                 else
 296                         __raw_writel(APLL_VAL_800, S5P_APLL_CON);
 297
 298                 do {
 299                         reg = __raw_readl(S5P_APLL_CON);
 300                 } while (!(reg & (0x1 << 29)));
 301
 302                 /*
 303                  * 7. Change souce clock from SCLKMPLL(667Mhz)
 304                  * to SCLKA2M(200Mhz) in MFC_MUX and G3D MUX
 305                  * (667/4=166)->(200/4=50)Mhz
 306                  */
 307                 reg = __raw_readl(S5P_CLK_SRC2);
 308                 reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK);
 309                 reg |= (0 << S5P_CLKSRC2_G3D_SHIFT) |
 310                         (0 << S5P_CLKSRC2_MFC_SHIFT);
 311                 __raw_writel(reg, S5P_CLK_SRC2);
 312
 313                 do {
 314                         reg = __raw_readl(S5P_CLKMUX_STAT1);
 315                 } while (reg & ((1 << 7) | (1 << 3)));
 316
 317                 /*
 318                  * 8. Change divider for MFC and G3D
 319                  * (200/4=50)->(200/1=200)Mhz
 320                  */
 321                 reg = __raw_readl(S5P_CLK_DIV2);
 322                 reg &= ~(S5P_CLKDIV2_G3D_MASK | S5P_CLKDIV2_MFC_MASK);
 323                 reg |= (clkdiv_val[index][10] << S5P_CLKDIV2_G3D_SHIFT) |
 324                         (clkdiv_val[index][9] << S5P_CLKDIV2_MFC_SHIFT);
 325                 __raw_writel(reg, S5P_CLK_DIV2);
 326
 327                 /* For MFC, G3D dividing */
 328                 do {
 329                         reg = __raw_readl(S5P_CLKDIV_STAT0);
 330                 } while (reg & ((1 << 16) | (1 << 17)));
 331
 332                 /* 9. Change MPLL to APLL in MSYS_MUX */
 333                 reg = __raw_readl(S5P_CLK_SRC0);
 334                 reg &= ~(S5P_CLKSRC0_MUX200_MASK);
 335                 reg |= (0x0 << S5P_CLKSRC0_MUX200_SHIFT);
 336                 __raw_writel(reg, S5P_CLK_SRC0);
 337
 338                 do {
 339                         reg = __raw_readl(S5P_CLKMUX_STAT0);
 340                 } while (reg & (0x1 << 18));
 341
 342                 /*
 343                  * 10. DMC1 refresh counter
 344                  * L4 : DMC1 = 100Mhz 7.8us/(1/100) = 0x30c
 345                  * Others : DMC1 = 200Mhz 7.8us/(1/200) = 0x618
 346                  */
 347                 if (!bus_speed_changing)
 348                         s5pv210_set_refresh(DMC1, 200000);
 349         }
 350
 351         /*
 352          * L4 level need to change memory bus speed, hence onedram clock divier
 353          * and memory refresh parameter should be changed
 354          */
 355         if (bus_speed_changing) {
 356                 reg = __raw_readl(S5P_CLK_DIV6);
 357                 reg &= ~S5P_CLKDIV6_ONEDRAM_MASK;
 358                 reg |= (clkdiv_val[index][8] << S5P_CLKDIV6_ONEDRAM_SHIFT);
 359                 __raw_writel(reg, S5P_CLK_DIV6);
 360
 361                 do {
 362                         reg = __raw_readl(S5P_CLKDIV_STAT1);
 363                 } while (reg & (1 << 15));
 364
 365                 /* Reconfigure DRAM refresh counter value */
 366                 if (index != L4) {
 367                         /*
 368                          * DMC0 : 166Mhz
 369                          * DMC1 : 200Mhz
 370                          */
 371                         s5pv210_set_refresh(DMC0, 166000);
 372                         s5pv210_set_refresh(DMC1, 200000);
 373                 } else {
 374                         /*
 375                          * DMC0 : 83Mhz
 376                          * DMC1 : 100Mhz
 377                          */
 378                         s5pv210_set_refresh(DMC0, 83000);
 379                         s5pv210_set_refresh(DMC1, 100000);
 380                 }
 381         }
 382
 383         if (freqs.new < freqs.old) {
 384                 /* Voltage down: will be implemented */
 385         }
 386
 387         cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
 388
 389         printk(KERN_DEBUG "Perf changed[L%d]\n", index);
 390
 391         return 0;
 392 }
 393
 394 #ifdef CONFIG_PM
 395 static int s5pv210_cpufreq_suspend(struct cpufreq_policy *policy)
 396 {
 397         return 0;
 398 }
 399
 400 static int s5pv210_cpufreq_resume(struct cpufreq_policy *policy)
 401 {
 402         return 0;
 403 }
 404 #endif
 405
 406 static int check_mem_type(void __iomem *dmc_reg)
 407 {
 408         unsigned long val;
 409
 410         val = __raw_readl(dmc_reg + 0x4);
 411         val = (val & (0xf << 8));
 412
 413         return val >> 8;
 414 }
 415
 416 static int __init s5pv210_cpu_init(struct cpufreq_policy *policy)
 417 {
 418         unsigned long mem_type;
 419
 420         cpu_clk = clk_get(NULL, "armclk");
 421         if (IS_ERR(cpu_clk))
 422                 return PTR_ERR(cpu_clk);
 423
 424         dmc0_clk = clk_get(NULL, "sclk_dmc0");
 425         if (IS_ERR(dmc0_clk)) {
 426                 clk_put(cpu_clk);
 427                 return PTR_ERR(dmc0_clk);
 428         }
 429
 430         dmc1_clk = clk_get(NULL, "hclk_msys");
 431         if (IS_ERR(dmc1_clk)) {
 432                 clk_put(dmc0_clk);
 433                 clk_put(cpu_clk);
 434                 return PTR_ERR(dmc1_clk);
 435         }
 436
 437         if (policy->cpu != 0)
 438                 return -EINVAL;
 439
 440         /*
 441          * check_mem_type : This driver only support LPDDR & LPDDR2.
 442          * other memory type is not supported.
 443          */
 444         mem_type = check_mem_type(S5P_VA_DMC0);
 445
 446         if ((mem_type != LPDDR) && (mem_type != LPDDR2)) {
 447                 printk(KERN_ERR "CPUFreq doesn't support this memory type\n");
 448                 return -EINVAL;
 449         }
 450
 451         /* Find current refresh counter and frequency each DMC */
 452         s5pv210_dram_conf[0].refresh = (__raw_readl(S5P_VA_DMC0 + 0x30) * 1000);
 453         s5pv210_dram_conf[0].freq = clk_get_rate(dmc0_clk);
 454
 455         s5pv210_dram_conf[1].refresh = (__raw_readl(S5P_VA_DMC1 + 0x30) * 1000);
 456         s5pv210_dram_conf[1].freq = clk_get_rate(dmc1_clk);
 457
 458         policy->cur = policy->min = policy->max = s5pv210_getspeed(0);
 459
 460         cpufreq_frequency_table_get_attr(s5pv210_freq_table, policy->cpu);
 461
 462         policy->cpuinfo.transition_latency = 40000;
 463
 464         return cpufreq_frequency_table_cpuinfo(policy, s5pv210_freq_table);
 465 }
 466
 467 static struct cpufreq_driver s5pv210_driver = {
 468         .flags          = CPUFREQ_STICKY,
 469         .verify         = s5pv210_verify_speed,
 470         .target         = s5pv210_target,
 471         .get            = s5pv210_getspeed,
 472         .init           = s5pv210_cpu_init,
 473         .name           = "s5pv210",
 474 #ifdef CONFIG_PM
 475         .suspend        = s5pv210_cpufreq_suspend,
 476         .resume         = s5pv210_cpufreq_resume,
 477 #endif
 478 };
 479
 480 static int __init s5pv210_cpufreq_init(void)
 481 {
 482         return cpufreq_register_driver(&s5pv210_driver);
 483 }
 484
 485 late_initcall(s5pv210_cpufreq_init);