arch/arm/mach-s5pv210/clock.c

   1 /* linux/arch/arm/mach-s5pv210/clock.c
   2  *
   3  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com/
   5  *
   6  * S5PV210 - Clock support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #include <linux/init.h>
  14 #include <linux/module.h>
  15 #include <linux/kernel.h>
  16 #include <linux/list.h>
  17 #include <linux/errno.h>
  18 #include <linux/err.h>
  19 #include <linux/clk.h>
  20 #include <linux/sysdev.h>
  21 #include <linux/io.h>
  22
  23 #include <mach/map.h>
  24
  25 #include <plat/cpu-freq.h>
  26 #include <mach/regs-clock.h>
  27 #include <plat/clock.h>
  28 #include <plat/cpu.h>
  29 #include <plat/pll.h>
  30 #include <plat/s5p-clock.h>
  31 #include <plat/clock-clksrc.h>
  32 #include <plat/s5pv210.h>
  33
  34 static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable)
  35 {
  36         return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable);
  37 }
  38
  39 static int s5pv210_clk_ip1_ctrl(struct clk *clk, int enable)
  40 {
  41         return s5p_gatectrl(S5P_CLKGATE_IP1, clk, enable);
  42 }
  43
  44 static int s5pv210_clk_ip2_ctrl(struct clk *clk, int enable)
  45 {
  46         return s5p_gatectrl(S5P_CLKGATE_IP2, clk, enable);
  47 }
  48
  49 static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable)
  50 {
  51         return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
  52 }
  53
  54 static struct clk clk_h200 = {
  55         .name           = "hclk200",
  56         .id             = -1,
  57 };
  58
  59 static struct clk clk_h100 = {
  60         .name           = "hclk100",
  61         .id             = -1,
  62 };
  63
  64 static struct clk clk_h166 = {
  65         .name           = "hclk166",
  66         .id             = -1,
  67 };
  68
  69 static struct clk clk_h133 = {
  70         .name           = "hclk133",
  71         .id             = -1,
  72 };
  73
  74 static struct clk clk_p100 = {
  75         .name           = "pclk100",
  76         .id             = -1,
  77 };
  78
  79 static struct clk clk_p83 = {
  80         .name           = "pclk83",
  81         .id             = -1,
  82 };
  83
  84 static struct clk clk_p66 = {
  85         .name           = "pclk66",
  86         .id             = -1,
  87 };
  88
  89 static struct clk *sys_clks[] = {
  90         &clk_h200,
  91         &clk_h100,
  92         &clk_h166,
  93         &clk_h133,
  94         &clk_p100,
  95         &clk_p83,
  96         &clk_p66
  97 };
  98
  99 static struct clk init_clocks_disable[] = {
 100         {
 101                 .name           = "rot",
 102                 .id             = -1,
 103                 .parent         = &clk_h166,
 104                 .enable         = s5pv210_clk_ip0_ctrl,
 105                 .ctrlbit        = (1<<29),
 106         }, {
 107                 .name           = "otg",
 108                 .id             = -1,
 109                 .parent         = &clk_h133,
 110                 .enable         = s5pv210_clk_ip1_ctrl,
 111                 .ctrlbit        = (1<<16),
 112         }, {
 113                 .name           = "usb-host",
 114                 .id             = -1,
 115                 .parent         = &clk_h133,
 116                 .enable         = s5pv210_clk_ip1_ctrl,
 117                 .ctrlbit        = (1<<17),
 118         }, {
 119                 .name           = "lcd",
 120                 .id             = -1,
 121                 .parent         = &clk_h166,
 122                 .enable         = s5pv210_clk_ip1_ctrl,
 123                 .ctrlbit        = (1<<0),
 124         }, {
 125                 .name           = "cfcon",
 126                 .id             = 0,
 127                 .parent         = &clk_h133,
 128                 .enable         = s5pv210_clk_ip1_ctrl,
 129                 .ctrlbit        = (1<<25),
 130         }, {
 131                 .name           = "hsmmc",
 132                 .id             = 0,
 133                 .parent         = &clk_h133,
 134                 .enable         = s5pv210_clk_ip2_ctrl,
 135                 .ctrlbit        = (1<<16),
 136         }, {
 137                 .name           = "hsmmc",
 138                 .id             = 1,
 139                 .parent         = &clk_h133,
 140                 .enable         = s5pv210_clk_ip2_ctrl,
 141                 .ctrlbit        = (1<<17),
 142         }, {
 143                 .name           = "hsmmc",
 144                 .id             = 2,
 145                 .parent         = &clk_h133,
 146                 .enable         = s5pv210_clk_ip2_ctrl,
 147                 .ctrlbit        = (1<<18),
 148         }, {
 149                 .name           = "hsmmc",
 150                 .id             = 3,
 151                 .parent         = &clk_h133,
 152                 .enable         = s5pv210_clk_ip2_ctrl,
 153                 .ctrlbit        = (1<<19),
 154         }, {
 155                 .name           = "systimer",
 156                 .id             = -1,
 157                 .parent         = &clk_p66,
 158                 .enable         = s5pv210_clk_ip3_ctrl,
 159                 .ctrlbit        = (1<<16),
 160         }, {
 161                 .name           = "watchdog",
 162                 .id             = -1,
 163                 .parent         = &clk_p66,
 164                 .enable         = s5pv210_clk_ip3_ctrl,
 165                 .ctrlbit        = (1<<22),
 166         }, {
 167                 .name           = "rtc",
 168                 .id             = -1,
 169                 .parent         = &clk_p66,
 170                 .enable         = s5pv210_clk_ip3_ctrl,
 171                 .ctrlbit        = (1<<15),
 172         }, {
 173                 .name           = "i2c",
 174                 .id             = 0,
 175                 .parent         = &clk_p66,
 176                 .enable         = s5pv210_clk_ip3_ctrl,
 177                 .ctrlbit        = (1<<7),
 178         }, {
 179                 .name           = "i2c",
 180                 .id             = 1,
 181                 .parent         = &clk_p66,
 182                 .enable         = s5pv210_clk_ip3_ctrl,
 183                 .ctrlbit        = (1<<8),
 184         }, {
 185                 .name           = "i2c",
 186                 .id             = 2,
 187                 .parent         = &clk_p66,
 188                 .enable         = s5pv210_clk_ip3_ctrl,
 189                 .ctrlbit        = (1<<9),
 190         }, {
 191                 .name           = "spi",
 192                 .id             = 0,
 193                 .parent         = &clk_p66,
 194                 .enable         = s5pv210_clk_ip3_ctrl,
 195                 .ctrlbit        = (1<<12),
 196         }, {
 197                 .name           = "spi",
 198                 .id             = 1,
 199                 .parent         = &clk_p66,
 200                 .enable         = s5pv210_clk_ip3_ctrl,
 201                 .ctrlbit        = (1<<13),
 202         }, {
 203                 .name           = "spi",
 204                 .id             = 2,
 205                 .parent         = &clk_p66,
 206                 .enable         = s5pv210_clk_ip3_ctrl,
 207                 .ctrlbit        = (1<<14),
 208         }, {
 209                 .name           = "timers",
 210                 .id             = -1,
 211                 .parent         = &clk_p66,
 212                 .enable         = s5pv210_clk_ip3_ctrl,
 213                 .ctrlbit        = (1<<23),
 214         }, {
 215                 .name           = "adc",
 216                 .id             = -1,
 217                 .parent         = &clk_p66,
 218                 .enable         = s5pv210_clk_ip3_ctrl,
 219                 .ctrlbit        = (1<<24),
 220         }, {
 221                 .name           = "keypad",
 222                 .id             = -1,
 223                 .parent         = &clk_p66,
 224                 .enable         = s5pv210_clk_ip3_ctrl,
 225                 .ctrlbit        = (1<<21),
 226         }, {
 227                 .name           = "i2s_v50",
 228                 .id             = 0,
 229                 .parent         = &clk_p,
 230                 .enable         = s5pv210_clk_ip3_ctrl,
 231                 .ctrlbit        = (1<<4),
 232         }, {
 233                 .name           = "i2s_v32",
 234                 .id             = 0,
 235                 .parent         = &clk_p,
 236                 .enable         = s5pv210_clk_ip3_ctrl,
 237                 .ctrlbit        = (1<<4),
 238         }, {
 239                 .name           = "i2s_v32",
 240                 .id             = 1,
 241                 .parent         = &clk_p,
 242                 .enable         = s5pv210_clk_ip3_ctrl,
 243                 .ctrlbit        = (1<<4),
 244         }
 245 };
 246
 247 static struct clk init_clocks[] = {
 248         {
 249                 .name           = "uart",
 250                 .id             = 0,
 251                 .parent         = &clk_p66,
 252                 .enable         = s5pv210_clk_ip3_ctrl,
 253                 .ctrlbit        = (1<<7),
 254         }, {
 255                 .name           = "uart",
 256                 .id             = 1,
 257                 .parent         = &clk_p66,
 258                 .enable         = s5pv210_clk_ip3_ctrl,
 259                 .ctrlbit        = (1<<8),
 260         }, {
 261                 .name           = "uart",
 262                 .id             = 2,
 263                 .parent         = &clk_p66,
 264                 .enable         = s5pv210_clk_ip3_ctrl,
 265                 .ctrlbit        = (1<<9),
 266         }, {
 267                 .name           = "uart",
 268                 .id             = 3,
 269                 .parent         = &clk_p66,
 270                 .enable         = s5pv210_clk_ip3_ctrl,
 271                 .ctrlbit        = (1<<10),
 272         },
 273 };
 274
 275 static struct clksrc_clk clk_mout_apll = {
 276         .clk    = {
 277                 .name           = "mout_apll",
 278                 .id             = -1,
 279         },
 280         .sources        = &clk_src_apll,
 281         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
 282 };
 283
 284 static struct clksrc_clk clk_mout_epll = {
 285         .clk    = {
 286                 .name           = "mout_epll",
 287                 .id             = -1,
 288         },
 289         .sources        = &clk_src_epll,
 290         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
 291 };
 292
 293 static struct clksrc_clk clk_mout_mpll = {
 294         .clk = {
 295                 .name           = "mout_mpll",
 296                 .id             = -1,
 297         },
 298         .sources        = &clk_src_mpll,
 299         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
 300 };
 301
 302 static struct clk *clkset_uart_list[] = {
 303         [6] = &clk_mout_mpll.clk,
 304         [7] = &clk_mout_epll.clk,
 305 };
 306
 307 static struct clksrc_sources clkset_uart = {
 308         .sources        = clkset_uart_list,
 309         .nr_sources     = ARRAY_SIZE(clkset_uart_list),
 310 };
 311
 312 static struct clksrc_clk clksrcs[] = {
 313         {
 314                 .clk    = {
 315                         .name           = "uclk1",
 316                         .id             = -1,
 317                         .ctrlbit        = (1<<17),
 318                         .enable         = s5pv210_clk_ip3_ctrl,
 319                 },
 320                 .sources = &clkset_uart,
 321                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
 322                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
 323         }
 324 };
 325
 326 /* Clock initialisation code */
 327 static struct clksrc_clk *init_parents[] = {
 328         &clk_mout_apll,
 329         &clk_mout_epll,
 330         &clk_mout_mpll,
 331 };
 332
 333 #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
 334
 335 void __init_or_cpufreq s5pv210_setup_clocks(void)
 336 {
 337         struct clk *xtal_clk;
 338         unsigned long xtal;
 339         unsigned long armclk;
 340         unsigned long hclk200;
 341         unsigned long hclk166;
 342         unsigned long hclk133;
 343         unsigned long pclk100;
 344         unsigned long pclk83;
 345         unsigned long pclk66;
 346         unsigned long apll;
 347         unsigned long mpll;
 348         unsigned long epll;
 349         unsigned int ptr;
 350         u32 clkdiv0, clkdiv1;
 351
 352         printk(KERN_DEBUG "%s: registering clocks\n", __func__);
 353
 354         clkdiv0 = __raw_readl(S5P_CLK_DIV0);
 355         clkdiv1 = __raw_readl(S5P_CLK_DIV1);
 356
 357         printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n",
 358                                 __func__, clkdiv0, clkdiv1);
 359
 360         xtal_clk = clk_get(NULL, "xtal");
 361         BUG_ON(IS_ERR(xtal_clk));
 362
 363         xtal = clk_get_rate(xtal_clk);
 364         clk_put(xtal_clk);
 365
 366         printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
 367
 368         apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
 369         mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
 370         epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500);
 371
 372         printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld",
 373                         apll, mpll, epll);
 374
 375         armclk = apll / GET_DIV(clkdiv0, S5P_CLKDIV0_APLL);
 376         if (__raw_readl(S5P_CLK_SRC0) & S5P_CLKSRC0_MUX200_MASK)
 377                 hclk200 = mpll / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK200);
 378         else
 379                 hclk200 = armclk / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK200);
 380
 381         if (__raw_readl(S5P_CLK_SRC0) & S5P_CLKSRC0_MUX166_MASK) {
 382                 hclk166 = apll / GET_DIV(clkdiv0, S5P_CLKDIV0_A2M);
 383                 hclk166 = hclk166 / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK166);
 384         } else
 385                 hclk166 = mpll / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK166);
 386
 387         if (__raw_readl(S5P_CLK_SRC0) & S5P_CLKSRC0_MUX133_MASK) {
 388                 hclk133 = apll / GET_DIV(clkdiv0, S5P_CLKDIV0_A2M);
 389                 hclk133 = hclk133 / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK133);
 390         } else
 391                 hclk133 = mpll / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK133);
 392
 393         pclk100 = hclk200 / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK100);
 394         pclk83 = hclk166 / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK83);
 395         pclk66 = hclk133 / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK66);
 396
 397         printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld, \
 398                         HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n",
 399                armclk, hclk200, hclk166, hclk133, pclk100, pclk83, pclk66);
 400
 401         clk_fout_apll.rate = apll;
 402         clk_fout_mpll.rate = mpll;
 403         clk_fout_epll.rate = epll;
 404
 405         clk_f.rate = armclk;
 406         clk_h.rate = hclk133;
 407         clk_p.rate = pclk66;
 408         clk_p66.rate = pclk66;
 409         clk_p83.rate = pclk83;
 410         clk_h133.rate = hclk133;
 411         clk_h166.rate = hclk166;
 412         clk_h200.rate = hclk200;
 413
 414         for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
 415                 s3c_set_clksrc(init_parents[ptr], true);
 416
 417         for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
 418                 s3c_set_clksrc(&clksrcs[ptr], true);
 419 }
 420
 421 static struct clk *clks[] __initdata = {
 422         &clk_mout_epll.clk,
 423         &clk_mout_mpll.clk,
 424 };
 425
 426 void __init s5pv210_register_clocks(void)
 427 {
 428         struct clk *clkp;
 429         int ret;
 430         int ptr;
 431
 432         ret = s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
 433         if (ret > 0)
 434                 printk(KERN_ERR "Failed to register %u clocks\n", ret);
 435
 436         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
 437         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
 438
 439         ret = s3c24xx_register_clocks(sys_clks, ARRAY_SIZE(sys_clks));
 440         if (ret > 0)
 441                 printk(KERN_ERR "Failed to register system clocks\n");
 442
 443         clkp = init_clocks_disable;
 444         for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
 445                 ret = s3c24xx_register_clock(clkp);
 446                 if (ret < 0) {
 447                         printk(KERN_ERR "Failed to register clock %s (%d)\n",
 448                                clkp->name, ret);
 449                 }
 450                 (clkp->enable)(clkp, 0);
 451         }
 452
 453         s3c_pwmclk_init();
 454 }