arch/arm/mach-s5pv210/clock.c

   1 /* linux/arch/arm/mach-s5pv210/clock.c
   2  *
   3  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com/
   5  *
   6  * S5PV210 - Clock support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #include <linux/init.h>
  14 #include <linux/module.h>
  15 #include <linux/kernel.h>
  16 #include <linux/list.h>
  17 #include <linux/errno.h>
  18 #include <linux/err.h>
  19 #include <linux/clk.h>
  20 #include <linux/sysdev.h>
  21 #include <linux/io.h>
  22
  23 #include <mach/map.h>
  24
  25 #include <plat/cpu-freq.h>
  26 #include <mach/regs-clock.h>
  27 #include <plat/clock.h>
  28 #include <plat/cpu.h>
  29 #include <plat/pll.h>
  30 #include <plat/s5p-clock.h>
  31 #include <plat/clock-clksrc.h>
  32 #include <plat/s5pv210.h>
  33
  34 static unsigned long xtal;
  35
  36 static struct clksrc_clk clk_mout_apll = {
  37         .clk    = {
  38                 .name           = "mout_apll",
  39                 .id             = -1,
  40         },
  41         .sources        = &clk_src_apll,
  42         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
  43 };
  44
  45 static struct clksrc_clk clk_mout_epll = {
  46         .clk    = {
  47                 .name           = "mout_epll",
  48                 .id             = -1,
  49         },
  50         .sources        = &clk_src_epll,
  51         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
  52 };
  53
  54 static struct clksrc_clk clk_mout_mpll = {
  55         .clk = {
  56                 .name           = "mout_mpll",
  57                 .id             = -1,
  58         },
  59         .sources        = &clk_src_mpll,
  60         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
  61 };
  62
  63 static struct clk *clkset_armclk_list[] = {
  64         [0] = &clk_mout_apll.clk,
  65         [1] = &clk_mout_mpll.clk,
  66 };
  67
  68 static struct clksrc_sources clkset_armclk = {
  69         .sources        = clkset_armclk_list,
  70         .nr_sources     = ARRAY_SIZE(clkset_armclk_list),
  71 };
  72
  73 static struct clksrc_clk clk_armclk = {
  74         .clk    = {
  75                 .name           = "armclk",
  76                 .id             = -1,
  77         },
  78         .sources        = &clkset_armclk,
  79         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
  80         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 },
  81 };
  82
  83 static struct clksrc_clk clk_hclk_msys = {
  84         .clk    = {
  85                 .name           = "hclk_msys",
  86                 .id             = -1,
  87                 .parent         = &clk_armclk.clk,
  88         },
  89         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
  90 };
  91
  92 static struct clksrc_clk clk_pclk_msys = {
  93         .clk    = {
  94                 .name           = "pclk_msys",
  95                 .id             = -1,
  96                 .parent         = &clk_hclk_msys.clk,
  97         },
  98         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
  99 };
 100
 101 static struct clksrc_clk clk_sclk_a2m = {
 102         .clk    = {
 103                 .name           = "sclk_a2m",
 104                 .id             = -1,
 105                 .parent         = &clk_mout_apll.clk,
 106         },
 107         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
 108 };
 109
 110 static struct clk *clkset_hclk_sys_list[] = {
 111         [0] = &clk_mout_mpll.clk,
 112         [1] = &clk_sclk_a2m.clk,
 113 };
 114
 115 static struct clksrc_sources clkset_hclk_sys = {
 116         .sources        = clkset_hclk_sys_list,
 117         .nr_sources     = ARRAY_SIZE(clkset_hclk_sys_list),
 118 };
 119
 120 static struct clksrc_clk clk_hclk_dsys = {
 121         .clk    = {
 122                 .name   = "hclk_dsys",
 123                 .id     = -1,
 124         },
 125         .sources        = &clkset_hclk_sys,
 126         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
 127         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 },
 128 };
 129
 130 static struct clksrc_clk clk_pclk_dsys = {
 131         .clk    = {
 132                 .name   = "pclk_dsys",
 133                 .id     = -1,
 134                 .parent = &clk_hclk_dsys.clk,
 135         },
 136         .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 },
 137 };
 138
 139 static struct clksrc_clk clk_hclk_psys = {
 140         .clk    = {
 141                 .name   = "hclk_psys",
 142                 .id     = -1,
 143         },
 144         .sources        = &clkset_hclk_sys,
 145         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
 146         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 },
 147 };
 148
 149 static struct clksrc_clk clk_pclk_psys = {
 150         .clk    = {
 151                 .name   = "pclk_psys",
 152                 .id     = -1,
 153                 .parent = &clk_hclk_psys.clk,
 154         },
 155         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 },
 156 };
 157
 158 static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable)
 159 {
 160         return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable);
 161 }
 162
 163 static int s5pv210_clk_ip1_ctrl(struct clk *clk, int enable)
 164 {
 165         return s5p_gatectrl(S5P_CLKGATE_IP1, clk, enable);
 166 }
 167
 168 static int s5pv210_clk_ip2_ctrl(struct clk *clk, int enable)
 169 {
 170         return s5p_gatectrl(S5P_CLKGATE_IP2, clk, enable);
 171 }
 172
 173 static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable)
 174 {
 175         return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
 176 }
 177
 178 static int s5pv210_clk_mask0_ctrl(struct clk *clk, int enable)
 179 {
 180         return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable);
 181 }
 182
 183 static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable)
 184 {
 185         return s5p_gatectrl(S5P_CLK_SRC_MASK1, clk, enable);
 186 }
 187
 188 static struct clk clk_sclk_hdmi27m = {
 189         .name           = "sclk_hdmi27m",
 190         .id             = -1,
 191         .rate           = 27000000,
 192 };
 193
 194 static struct clk clk_sclk_hdmiphy = {
 195         .name           = "sclk_hdmiphy",
 196         .id             = -1,
 197 };
 198
 199 static struct clk clk_sclk_usbphy0 = {
 200         .name           = "sclk_usbphy0",
 201         .id             = -1,
 202 };
 203
 204 static struct clk clk_sclk_usbphy1 = {
 205         .name           = "sclk_usbphy1",
 206         .id             = -1,
 207 };
 208
 209 static struct clk clk_pcmcdclk0 = {
 210         .name           = "pcmcdclk",
 211         .id             = -1,
 212 };
 213
 214 static struct clk clk_pcmcdclk1 = {
 215         .name           = "pcmcdclk",
 216         .id             = -1,
 217 };
 218
 219 static struct clk clk_pcmcdclk2 = {
 220         .name           = "pcmcdclk",
 221         .id             = -1,
 222 };
 223
 224 static struct clk *clkset_vpllsrc_list[] = {
 225         [0] = &clk_fin_vpll,
 226         [1] = &clk_sclk_hdmi27m,
 227 };
 228
 229 static struct clksrc_sources clkset_vpllsrc = {
 230         .sources        = clkset_vpllsrc_list,
 231         .nr_sources     = ARRAY_SIZE(clkset_vpllsrc_list),
 232 };
 233
 234 static struct clksrc_clk clk_vpllsrc = {
 235         .clk    = {
 236                 .name           = "vpll_src",
 237                 .id             = -1,
 238                 .enable         = s5pv210_clk_mask0_ctrl,
 239                 .ctrlbit        = (1 << 7),
 240         },
 241         .sources        = &clkset_vpllsrc,
 242         .reg_src        = { .reg = S5P_CLK_SRC1, .shift = 28, .size = 1 },
 243 };
 244
 245 static struct clk *clkset_sclk_vpll_list[] = {
 246         [0] = &clk_vpllsrc.clk,
 247         [1] = &clk_fout_vpll,
 248 };
 249
 250 static struct clksrc_sources clkset_sclk_vpll = {
 251         .sources        = clkset_sclk_vpll_list,
 252         .nr_sources     = ARRAY_SIZE(clkset_sclk_vpll_list),
 253 };
 254
 255 static struct clksrc_clk clk_sclk_vpll = {
 256         .clk    = {
 257                 .name           = "sclk_vpll",
 258                 .id             = -1,
 259         },
 260         .sources        = &clkset_sclk_vpll,
 261         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
 262 };
 263
 264 static struct clk *clkset_moutdmc0src_list[] = {
 265         [0] = &clk_sclk_a2m.clk,
 266         [1] = &clk_mout_mpll.clk,
 267         [2] = NULL,
 268         [3] = NULL,
 269 };
 270
 271 static struct clksrc_sources clkset_moutdmc0src = {
 272         .sources        = clkset_moutdmc0src_list,
 273         .nr_sources     = ARRAY_SIZE(clkset_moutdmc0src_list),
 274 };
 275
 276 static struct clksrc_clk clk_mout_dmc0 = {
 277         .clk    = {
 278                 .name           = "mout_dmc0",
 279                 .id             = -1,
 280         },
 281         .sources        = &clkset_moutdmc0src,
 282         .reg_src        = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
 283 };
 284
 285 static struct clksrc_clk clk_sclk_dmc0 = {
 286         .clk    = {
 287                 .name           = "sclk_dmc0",
 288                 .id             = -1,
 289                 .parent         = &clk_mout_dmc0.clk,
 290         },
 291         .reg_div        = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 },
 292 };
 293
 294 static unsigned long s5pv210_clk_imem_get_rate(struct clk *clk)
 295 {
 296         return clk_get_rate(clk->parent) / 2;
 297 }
 298
 299 static struct clk_ops clk_hclk_imem_ops = {
 300         .get_rate       = s5pv210_clk_imem_get_rate,
 301 };
 302
 303 static unsigned long s5pv210_clk_fout_apll_get_rate(struct clk *clk)
 304 {
 305         return s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
 306 }
 307
 308 static struct clk_ops clk_fout_apll_ops = {
 309         .get_rate       = s5pv210_clk_fout_apll_get_rate,
 310 };
 311
 312 static struct clk init_clocks_off[] = {
 313         {
 314                 .name           = "pdma",
 315                 .id             = 0,
 316                 .parent         = &clk_hclk_psys.clk,
 317                 .enable         = s5pv210_clk_ip0_ctrl,
 318                 .ctrlbit        = (1 << 3),
 319         }, {
 320                 .name           = "pdma",
 321                 .id             = 1,
 322                 .parent         = &clk_hclk_psys.clk,
 323                 .enable         = s5pv210_clk_ip0_ctrl,
 324                 .ctrlbit        = (1 << 4),
 325         }, {
 326                 .name           = "rot",
 327                 .id             = -1,
 328                 .parent         = &clk_hclk_dsys.clk,
 329                 .enable         = s5pv210_clk_ip0_ctrl,
 330                 .ctrlbit        = (1<<29),
 331         }, {
 332                 .name           = "fimc",
 333                 .id             = 0,
 334                 .parent         = &clk_hclk_dsys.clk,
 335                 .enable         = s5pv210_clk_ip0_ctrl,
 336                 .ctrlbit        = (1 << 24),
 337         }, {
 338                 .name           = "fimc",
 339                 .id             = 1,
 340                 .parent         = &clk_hclk_dsys.clk,
 341                 .enable         = s5pv210_clk_ip0_ctrl,
 342                 .ctrlbit        = (1 << 25),
 343         }, {
 344                 .name           = "fimc",
 345                 .id             = 2,
 346                 .parent         = &clk_hclk_dsys.clk,
 347                 .enable         = s5pv210_clk_ip0_ctrl,
 348                 .ctrlbit        = (1 << 26),
 349         }, {
 350                 .name           = "otg",
 351                 .id             = -1,
 352                 .parent         = &clk_hclk_psys.clk,
 353                 .enable         = s5pv210_clk_ip1_ctrl,
 354                 .ctrlbit        = (1<<16),
 355         }, {
 356                 .name           = "usb-host",
 357                 .id             = -1,
 358                 .parent         = &clk_hclk_psys.clk,
 359                 .enable         = s5pv210_clk_ip1_ctrl,
 360                 .ctrlbit        = (1<<17),
 361         }, {
 362                 .name           = "lcd",
 363                 .id             = -1,
 364                 .parent         = &clk_hclk_dsys.clk,
 365                 .enable         = s5pv210_clk_ip1_ctrl,
 366                 .ctrlbit        = (1<<0),
 367         }, {
 368                 .name           = "cfcon",
 369                 .id             = 0,
 370                 .parent         = &clk_hclk_psys.clk,
 371                 .enable         = s5pv210_clk_ip1_ctrl,
 372                 .ctrlbit        = (1<<25),
 373         }, {
 374                 .name           = "hsmmc",
 375                 .id             = 0,
 376                 .parent         = &clk_hclk_psys.clk,
 377                 .enable         = s5pv210_clk_ip2_ctrl,
 378                 .ctrlbit        = (1<<16),
 379         }, {
 380                 .name           = "hsmmc",
 381                 .id             = 1,
 382                 .parent         = &clk_hclk_psys.clk,
 383                 .enable         = s5pv210_clk_ip2_ctrl,
 384                 .ctrlbit        = (1<<17),
 385         }, {
 386                 .name           = "hsmmc",
 387                 .id             = 2,
 388                 .parent         = &clk_hclk_psys.clk,
 389                 .enable         = s5pv210_clk_ip2_ctrl,
 390                 .ctrlbit        = (1<<18),
 391         }, {
 392                 .name           = "hsmmc",
 393                 .id             = 3,
 394                 .parent         = &clk_hclk_psys.clk,
 395                 .enable         = s5pv210_clk_ip2_ctrl,
 396                 .ctrlbit        = (1<<19),
 397         }, {
 398                 .name           = "systimer",
 399                 .id             = -1,
 400                 .parent         = &clk_pclk_psys.clk,
 401                 .enable         = s5pv210_clk_ip3_ctrl,
 402                 .ctrlbit        = (1<<16),
 403         }, {
 404                 .name           = "watchdog",
 405                 .id             = -1,
 406                 .parent         = &clk_pclk_psys.clk,
 407                 .enable         = s5pv210_clk_ip3_ctrl,
 408                 .ctrlbit        = (1<<22),
 409         }, {
 410                 .name           = "rtc",
 411                 .id             = -1,
 412                 .parent         = &clk_pclk_psys.clk,
 413                 .enable         = s5pv210_clk_ip3_ctrl,
 414                 .ctrlbit        = (1<<15),
 415         }, {
 416                 .name           = "i2c",
 417                 .id             = 0,
 418                 .parent         = &clk_pclk_psys.clk,
 419                 .enable         = s5pv210_clk_ip3_ctrl,
 420                 .ctrlbit        = (1<<7),
 421         }, {
 422                 .name           = "i2c",
 423                 .id             = 1,
 424                 .parent         = &clk_pclk_psys.clk,
 425                 .enable         = s5pv210_clk_ip3_ctrl,
 426                 .ctrlbit        = (1 << 10),
 427         }, {
 428                 .name           = "i2c",
 429                 .id             = 2,
 430                 .parent         = &clk_pclk_psys.clk,
 431                 .enable         = s5pv210_clk_ip3_ctrl,
 432                 .ctrlbit        = (1<<9),
 433         }, {
 434                 .name           = "spi",
 435                 .id             = 0,
 436                 .parent         = &clk_pclk_psys.clk,
 437                 .enable         = s5pv210_clk_ip3_ctrl,
 438                 .ctrlbit        = (1<<12),
 439         }, {
 440                 .name           = "spi",
 441                 .id             = 1,
 442                 .parent         = &clk_pclk_psys.clk,
 443                 .enable         = s5pv210_clk_ip3_ctrl,
 444                 .ctrlbit        = (1<<13),
 445         }, {
 446                 .name           = "spi",
 447                 .id             = 2,
 448                 .parent         = &clk_pclk_psys.clk,
 449                 .enable         = s5pv210_clk_ip3_ctrl,
 450                 .ctrlbit        = (1<<14),
 451         }, {
 452                 .name           = "timers",
 453                 .id             = -1,
 454                 .parent         = &clk_pclk_psys.clk,
 455                 .enable         = s5pv210_clk_ip3_ctrl,
 456                 .ctrlbit        = (1<<23),
 457         }, {
 458                 .name           = "adc",
 459                 .id             = -1,
 460                 .parent         = &clk_pclk_psys.clk,
 461                 .enable         = s5pv210_clk_ip3_ctrl,
 462                 .ctrlbit        = (1<<24),
 463         }, {
 464                 .name           = "keypad",
 465                 .id             = -1,
 466                 .parent         = &clk_pclk_psys.clk,
 467                 .enable         = s5pv210_clk_ip3_ctrl,
 468                 .ctrlbit        = (1<<21),
 469         }, {
 470                 .name           = "iis",
 471                 .id             = 0,
 472                 .parent         = &clk_p,
 473                 .enable         = s5pv210_clk_ip3_ctrl,
 474                 .ctrlbit        = (1<<4),
 475         }, {
 476                 .name           = "iis",
 477                 .id             = 1,
 478                 .parent         = &clk_p,
 479                 .enable         = s5pv210_clk_ip3_ctrl,
 480                 .ctrlbit        = (1 << 5),
 481         }, {
 482                 .name           = "iis",
 483                 .id             = 2,
 484                 .parent         = &clk_p,
 485                 .enable         = s5pv210_clk_ip3_ctrl,
 486                 .ctrlbit        = (1 << 6),
 487         }, {
 488                 .name           = "spdif",
 489                 .id             = -1,
 490                 .parent         = &clk_p,
 491                 .enable         = s5pv210_clk_ip3_ctrl,
 492                 .ctrlbit        = (1 << 0),
 493         },
 494 };
 495
 496 static struct clk init_clocks[] = {
 497         {
 498                 .name           = "hclk_imem",
 499                 .id             = -1,
 500                 .parent         = &clk_hclk_msys.clk,
 501                 .ctrlbit        = (1 << 5),
 502                 .enable         = s5pv210_clk_ip0_ctrl,
 503                 .ops            = &clk_hclk_imem_ops,
 504         }, {
 505                 .name           = "uart",
 506                 .id             = 0,
 507                 .parent         = &clk_pclk_psys.clk,
 508                 .enable         = s5pv210_clk_ip3_ctrl,
 509                 .ctrlbit        = (1 << 17),
 510         }, {
 511                 .name           = "uart",
 512                 .id             = 1,
 513                 .parent         = &clk_pclk_psys.clk,
 514                 .enable         = s5pv210_clk_ip3_ctrl,
 515                 .ctrlbit        = (1 << 18),
 516         }, {
 517                 .name           = "uart",
 518                 .id             = 2,
 519                 .parent         = &clk_pclk_psys.clk,
 520                 .enable         = s5pv210_clk_ip3_ctrl,
 521                 .ctrlbit        = (1 << 19),
 522         }, {
 523                 .name           = "uart",
 524                 .id             = 3,
 525                 .parent         = &clk_pclk_psys.clk,
 526                 .enable         = s5pv210_clk_ip3_ctrl,
 527                 .ctrlbit        = (1 << 20),
 528         }, {
 529                 .name           = "sromc",
 530                 .id             = -1,
 531                 .parent         = &clk_hclk_psys.clk,
 532                 .enable         = s5pv210_clk_ip1_ctrl,
 533                 .ctrlbit        = (1 << 26),
 534         },
 535 };
 536
 537 static struct clk *clkset_uart_list[] = {
 538         [6] = &clk_mout_mpll.clk,
 539         [7] = &clk_mout_epll.clk,
 540 };
 541
 542 static struct clksrc_sources clkset_uart = {
 543         .sources        = clkset_uart_list,
 544         .nr_sources     = ARRAY_SIZE(clkset_uart_list),
 545 };
 546
 547 static struct clk *clkset_group1_list[] = {
 548         [0] = &clk_sclk_a2m.clk,
 549         [1] = &clk_mout_mpll.clk,
 550         [2] = &clk_mout_epll.clk,
 551         [3] = &clk_sclk_vpll.clk,
 552 };
 553
 554 static struct clksrc_sources clkset_group1 = {
 555         .sources        = clkset_group1_list,
 556         .nr_sources     = ARRAY_SIZE(clkset_group1_list),
 557 };
 558
 559 static struct clk *clkset_sclk_onenand_list[] = {
 560         [0] = &clk_hclk_psys.clk,
 561         [1] = &clk_hclk_dsys.clk,
 562 };
 563
 564 static struct clksrc_sources clkset_sclk_onenand = {
 565         .sources        = clkset_sclk_onenand_list,
 566         .nr_sources     = ARRAY_SIZE(clkset_sclk_onenand_list),
 567 };
 568
 569 static struct clk *clkset_sclk_dac_list[] = {
 570         [0] = &clk_sclk_vpll.clk,
 571         [1] = &clk_sclk_hdmiphy,
 572 };
 573
 574 static struct clksrc_sources clkset_sclk_dac = {
 575         .sources        = clkset_sclk_dac_list,
 576         .nr_sources     = ARRAY_SIZE(clkset_sclk_dac_list),
 577 };
 578
 579 static struct clksrc_clk clk_sclk_dac = {
 580         .clk            = {
 581                 .name           = "sclk_dac",
 582                 .id             = -1,
 583                 .enable         = s5pv210_clk_mask0_ctrl,
 584                 .ctrlbit        = (1 << 2),
 585         },
 586         .sources        = &clkset_sclk_dac,
 587         .reg_src        = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 1 },
 588 };
 589
 590 static struct clksrc_clk clk_sclk_pixel = {
 591         .clk            = {
 592                 .name           = "sclk_pixel",
 593                 .id             = -1,
 594                 .parent         = &clk_sclk_vpll.clk,
 595         },
 596         .reg_div        = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4},
 597 };
 598
 599 static struct clk *clkset_sclk_hdmi_list[] = {
 600         [0] = &clk_sclk_pixel.clk,
 601         [1] = &clk_sclk_hdmiphy,
 602 };
 603
 604 static struct clksrc_sources clkset_sclk_hdmi = {
 605         .sources        = clkset_sclk_hdmi_list,
 606         .nr_sources     = ARRAY_SIZE(clkset_sclk_hdmi_list),
 607 };
 608
 609 static struct clksrc_clk clk_sclk_hdmi = {
 610         .clk            = {
 611                 .name           = "sclk_hdmi",
 612                 .id             = -1,
 613                 .enable         = s5pv210_clk_mask0_ctrl,
 614                 .ctrlbit        = (1 << 0),
 615         },
 616         .sources        = &clkset_sclk_hdmi,
 617         .reg_src        = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
 618 };
 619
 620 static struct clk *clkset_sclk_mixer_list[] = {
 621         [0] = &clk_sclk_dac.clk,
 622         [1] = &clk_sclk_hdmi.clk,
 623 };
 624
 625 static struct clksrc_sources clkset_sclk_mixer = {
 626         .sources        = clkset_sclk_mixer_list,
 627         .nr_sources     = ARRAY_SIZE(clkset_sclk_mixer_list),
 628 };
 629
 630 static struct clk *clkset_sclk_audio0_list[] = {
 631         [0] = &clk_ext_xtal_mux,
 632         [1] = &clk_pcmcdclk0,
 633         [2] = &clk_sclk_hdmi27m,
 634         [3] = &clk_sclk_usbphy0,
 635         [4] = &clk_sclk_usbphy1,
 636         [5] = &clk_sclk_hdmiphy,
 637         [6] = &clk_mout_mpll.clk,
 638         [7] = &clk_mout_epll.clk,
 639         [8] = &clk_sclk_vpll.clk,
 640 };
 641
 642 static struct clksrc_sources clkset_sclk_audio0 = {
 643         .sources        = clkset_sclk_audio0_list,
 644         .nr_sources     = ARRAY_SIZE(clkset_sclk_audio0_list),
 645 };
 646
 647 static struct clksrc_clk clk_sclk_audio0 = {
 648         .clk            = {
 649                 .name           = "sclk_audio",
 650                 .id             = 0,
 651                 .enable         = s5pv210_clk_mask0_ctrl,
 652                 .ctrlbit        = (1 << 24),
 653         },
 654         .sources = &clkset_sclk_audio0,
 655         .reg_src = { .reg = S5P_CLK_SRC6, .shift = 0, .size = 4 },
 656         .reg_div = { .reg = S5P_CLK_DIV6, .shift = 0, .size = 4 },
 657 };
 658
 659 static struct clk *clkset_sclk_audio1_list[] = {
 660         [0] = &clk_ext_xtal_mux,
 661         [1] = &clk_pcmcdclk1,
 662         [2] = &clk_sclk_hdmi27m,
 663         [3] = &clk_sclk_usbphy0,
 664         [4] = &clk_sclk_usbphy1,
 665         [5] = &clk_sclk_hdmiphy,
 666         [6] = &clk_mout_mpll.clk,
 667         [7] = &clk_mout_epll.clk,
 668         [8] = &clk_sclk_vpll.clk,
 669 };
 670
 671 static struct clksrc_sources clkset_sclk_audio1 = {
 672         .sources        = clkset_sclk_audio1_list,
 673         .nr_sources     = ARRAY_SIZE(clkset_sclk_audio1_list),
 674 };
 675
 676 static struct clksrc_clk clk_sclk_audio1 = {
 677         .clk            = {
 678                 .name           = "sclk_audio",
 679                 .id             = 1,
 680                 .enable         = s5pv210_clk_mask0_ctrl,
 681                 .ctrlbit        = (1 << 25),
 682         },
 683         .sources = &clkset_sclk_audio1,
 684         .reg_src = { .reg = S5P_CLK_SRC6, .shift = 4, .size = 4 },
 685         .reg_div = { .reg = S5P_CLK_DIV6, .shift = 4, .size = 4 },
 686 };
 687
 688 static struct clk *clkset_sclk_audio2_list[] = {
 689         [0] = &clk_ext_xtal_mux,
 690         [1] = &clk_pcmcdclk0,
 691         [2] = &clk_sclk_hdmi27m,
 692         [3] = &clk_sclk_usbphy0,
 693         [4] = &clk_sclk_usbphy1,
 694         [5] = &clk_sclk_hdmiphy,
 695         [6] = &clk_mout_mpll.clk,
 696         [7] = &clk_mout_epll.clk,
 697         [8] = &clk_sclk_vpll.clk,
 698 };
 699
 700 static struct clksrc_sources clkset_sclk_audio2 = {
 701         .sources        = clkset_sclk_audio2_list,
 702         .nr_sources     = ARRAY_SIZE(clkset_sclk_audio2_list),
 703 };
 704
 705 static struct clksrc_clk clk_sclk_audio2 = {
 706         .clk            = {
 707                 .name           = "sclk_audio",
 708                 .id             = 2,
 709                 .enable         = s5pv210_clk_mask0_ctrl,
 710                 .ctrlbit        = (1 << 26),
 711         },
 712         .sources = &clkset_sclk_audio2,
 713         .reg_src = { .reg = S5P_CLK_SRC6, .shift = 8, .size = 4 },
 714         .reg_div = { .reg = S5P_CLK_DIV6, .shift = 8, .size = 4 },
 715 };
 716
 717 static struct clk *clkset_sclk_spdif_list[] = {
 718         [0] = &clk_sclk_audio0.clk,
 719         [1] = &clk_sclk_audio1.clk,
 720         [2] = &clk_sclk_audio2.clk,
 721 };
 722
 723 static struct clksrc_sources clkset_sclk_spdif = {
 724         .sources        = clkset_sclk_spdif_list,
 725         .nr_sources     = ARRAY_SIZE(clkset_sclk_spdif_list),
 726 };
 727
 728 static int s5pv210_spdif_set_rate(struct clk *clk, unsigned long rate)
 729 {
 730         struct clk *pclk;
 731         int ret;
 732
 733         pclk = clk_get_parent(clk);
 734         if (IS_ERR(pclk))
 735                 return -EINVAL;
 736
 737         ret = pclk->ops->set_rate(pclk, rate);
 738         clk_put(pclk);
 739
 740         return ret;
 741 }
 742
 743 static unsigned long s5pv210_spdif_get_rate(struct clk *clk)
 744 {
 745         struct clk *pclk;
 746         int rate;
 747
 748         pclk = clk_get_parent(clk);
 749         if (IS_ERR(pclk))
 750                 return -EINVAL;
 751
 752         rate = pclk->ops->get_rate(clk);
 753         clk_put(pclk);
 754
 755         return rate;
 756 }
 757
 758 static struct clk_ops s5pv210_sclk_spdif_ops = {
 759         .set_rate       = s5pv210_spdif_set_rate,
 760         .get_rate       = s5pv210_spdif_get_rate,
 761 };
 762
 763 static struct clksrc_clk clk_sclk_spdif = {
 764         .clk            = {
 765                 .name           = "sclk_spdif",
 766                 .id             = -1,
 767                 .enable         = s5pv210_clk_mask0_ctrl,
 768                 .ctrlbit        = (1 << 27),
 769                 .ops            = &s5pv210_sclk_spdif_ops,
 770         },
 771         .sources = &clkset_sclk_spdif,
 772         .reg_src = { .reg = S5P_CLK_SRC6, .shift = 12, .size = 2 },
 773 };
 774
 775 static struct clk *clkset_group2_list[] = {
 776         [0] = &clk_ext_xtal_mux,
 777         [1] = &clk_xusbxti,
 778         [2] = &clk_sclk_hdmi27m,
 779         [3] = &clk_sclk_usbphy0,
 780         [4] = &clk_sclk_usbphy1,
 781         [5] = &clk_sclk_hdmiphy,
 782         [6] = &clk_mout_mpll.clk,
 783         [7] = &clk_mout_epll.clk,
 784         [8] = &clk_sclk_vpll.clk,
 785 };
 786
 787 static struct clksrc_sources clkset_group2 = {
 788         .sources        = clkset_group2_list,
 789         .nr_sources     = ARRAY_SIZE(clkset_group2_list),
 790 };
 791
 792 static struct clksrc_clk clksrcs[] = {
 793         {
 794                 .clk    = {
 795                         .name           = "sclk_dmc",
 796                         .id             = -1,
 797                 },
 798                 .sources = &clkset_group1,
 799                 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
 800                 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 },
 801         }, {
 802                 .clk    = {
 803                         .name           = "sclk_onenand",
 804                         .id             = -1,
 805                 },
 806                 .sources = &clkset_sclk_onenand,
 807                 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 28, .size = 1 },
 808                 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 12, .size = 3 },
 809         }, {
 810                 .clk    = {
 811                         .name           = "uclk1",
 812                         .id             = 0,
 813                         .enable         = s5pv210_clk_mask0_ctrl,
 814                         .ctrlbit        = (1 << 12),
 815                 },
 816                 .sources = &clkset_uart,
 817                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
 818                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
 819         }, {
 820                 .clk            = {
 821                         .name           = "uclk1",
 822                         .id             = 1,
 823                         .enable         = s5pv210_clk_mask0_ctrl,
 824                         .ctrlbit        = (1 << 13),
 825                 },
 826                 .sources = &clkset_uart,
 827                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 },
 828                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
 829         }, {
 830                 .clk            = {
 831                         .name           = "uclk1",
 832                         .id             = 2,
 833                         .enable         = s5pv210_clk_mask0_ctrl,
 834                         .ctrlbit        = (1 << 14),
 835                 },
 836                 .sources = &clkset_uart,
 837                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 },
 838                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 24, .size = 4 },
 839         }, {
 840                 .clk            = {
 841                         .name           = "uclk1",
 842                         .id             = 3,
 843                         .enable         = s5pv210_clk_mask0_ctrl,
 844                         .ctrlbit        = (1 << 15),
 845                 },
 846                 .sources = &clkset_uart,
 847                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 },
 848                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 },
 849         }, {
 850                 .clk    = {
 851                         .name           = "sclk_mixer",
 852                         .id             = -1,
 853                         .enable         = s5pv210_clk_mask0_ctrl,
 854                         .ctrlbit        = (1 << 1),
 855                 },
 856                 .sources = &clkset_sclk_mixer,
 857                 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 },
 858         }, {
 859                 .clk    = {
 860                         .name           = "sclk_fimc",
 861                         .id             = 0,
 862                         .enable         = s5pv210_clk_mask1_ctrl,
 863                         .ctrlbit        = (1 << 2),
 864                 },
 865                 .sources = &clkset_group2,
 866                 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 4 },
 867                 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
 868         }, {
 869                 .clk    = {
 870                         .name           = "sclk_fimc",
 871                         .id             = 1,
 872                         .enable         = s5pv210_clk_mask1_ctrl,
 873                         .ctrlbit        = (1 << 3),
 874                 },
 875                 .sources = &clkset_group2,
 876                 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 4 },
 877                 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 16, .size = 4 },
 878         }, {
 879                 .clk    = {
 880                         .name           = "sclk_fimc",
 881                         .id             = 2,
 882                         .enable         = s5pv210_clk_mask1_ctrl,
 883                         .ctrlbit        = (1 << 4),
 884                 },
 885                 .sources = &clkset_group2,
 886                 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 4 },
 887                 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 },
 888         }, {
 889                 .clk            = {
 890                         .name           = "sclk_cam",
 891                         .id             = 0,
 892                         .enable         = s5pv210_clk_mask0_ctrl,
 893                         .ctrlbit        = (1 << 3),
 894                 },
 895                 .sources = &clkset_group2,
 896                 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 4 },
 897                 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 },
 898         }, {
 899                 .clk            = {
 900                         .name           = "sclk_cam",
 901                         .id             = 1,
 902                         .enable         = s5pv210_clk_mask0_ctrl,
 903                         .ctrlbit        = (1 << 4),
 904                 },
 905                 .sources = &clkset_group2,
 906                 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 4 },
 907                 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 4 },
 908         }, {
 909                 .clk            = {
 910                         .name           = "sclk_fimd",
 911                         .id             = -1,
 912                         .enable         = s5pv210_clk_mask0_ctrl,
 913                         .ctrlbit        = (1 << 5),
 914                 },
 915                 .sources = &clkset_group2,
 916                 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 4 },
 917                 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 },
 918         }, {
 919                 .clk            = {
 920                         .name           = "sclk_mmc",
 921                         .id             = 0,
 922                         .enable         = s5pv210_clk_mask0_ctrl,
 923                         .ctrlbit        = (1 << 8),
 924                 },
 925                 .sources = &clkset_group2,
 926                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
 927                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 },
 928         }, {
 929                 .clk            = {
 930                         .name           = "sclk_mmc",
 931                         .id             = 1,
 932                         .enable         = s5pv210_clk_mask0_ctrl,
 933                         .ctrlbit        = (1 << 9),
 934                 },
 935                 .sources = &clkset_group2,
 936                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
 937                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 },
 938         }, {
 939                 .clk            = {
 940                         .name           = "sclk_mmc",
 941                         .id             = 2,
 942                         .enable         = s5pv210_clk_mask0_ctrl,
 943                         .ctrlbit        = (1 << 10),
 944                 },
 945                 .sources = &clkset_group2,
 946                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
 947                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 },
 948         }, {
 949                 .clk            = {
 950                         .name           = "sclk_mmc",
 951                         .id             = 3,
 952                         .enable         = s5pv210_clk_mask0_ctrl,
 953                         .ctrlbit        = (1 << 11),
 954                 },
 955                 .sources = &clkset_group2,
 956                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
 957                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
 958         }, {
 959                 .clk            = {
 960                         .name           = "sclk_mfc",
 961                         .id             = -1,
 962                         .enable         = s5pv210_clk_ip0_ctrl,
 963                         .ctrlbit        = (1 << 16),
 964                 },
 965                 .sources = &clkset_group1,
 966                 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
 967                 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
 968         }, {
 969                 .clk            = {
 970                         .name           = "sclk_g2d",
 971                         .id             = -1,
 972                         .enable         = s5pv210_clk_ip0_ctrl,
 973                         .ctrlbit        = (1 << 12),
 974                 },
 975                 .sources = &clkset_group1,
 976                 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
 977                 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
 978         }, {
 979                 .clk            = {
 980                         .name           = "sclk_g3d",
 981                         .id             = -1,
 982                         .enable         = s5pv210_clk_ip0_ctrl,
 983                         .ctrlbit        = (1 << 8),
 984                 },
 985                 .sources = &clkset_group1,
 986                 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
 987                 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
 988         }, {
 989                 .clk            = {
 990                         .name           = "sclk_csis",
 991                         .id             = -1,
 992                         .enable         = s5pv210_clk_mask0_ctrl,
 993                         .ctrlbit        = (1 << 6),
 994                 },
 995                 .sources = &clkset_group2,
 996                 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 4 },
 997                 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 28, .size = 4 },
 998         }, {
 999                 .clk            = {
1000                         .name           = "sclk_spi",
1001                         .id             = 0,
1002                         .enable         = s5pv210_clk_mask0_ctrl,
1003                         .ctrlbit        = (1 << 16),
1004                 },
1005                 .sources = &clkset_group2,
1006                 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
1007                 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 },
1008         }, {
1009                 .clk            = {
1010                         .name           = "sclk_spi",
1011                         .id             = 1,
1012                         .enable         = s5pv210_clk_mask0_ctrl,
1013                         .ctrlbit        = (1 << 17),
1014                 },
1015                 .sources = &clkset_group2,
1016                 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
1017                 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 },
1018         }, {
1019                 .clk            = {
1020                         .name           = "sclk_pwi",
1021                         .id             = -1,
1022                         .enable         = s5pv210_clk_mask0_ctrl,
1023                         .ctrlbit        = (1 << 29),
1024                 },
1025                 .sources = &clkset_group2,
1026                 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 20, .size = 4 },
1027                 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 24, .size = 4 },
1028         }, {
1029                 .clk            = {
1030                         .name           = "sclk_pwm",
1031                         .id             = -1,
1032                         .enable         = s5pv210_clk_mask0_ctrl,
1033                         .ctrlbit        = (1 << 19),
1034                 },
1035                 .sources = &clkset_group2,
1036                 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 12, .size = 4 },
1037                 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 12, .size = 4 },
1038         },
1039 };
1040
1041 /* Clock initialisation code */
1042 static struct clksrc_clk *sysclks[] = {
1043         &clk_mout_apll,
1044         &clk_mout_epll,
1045         &clk_mout_mpll,
1046         &clk_armclk,
1047         &clk_hclk_msys,
1048         &clk_sclk_a2m,
1049         &clk_hclk_dsys,
1050         &clk_hclk_psys,
1051         &clk_pclk_msys,
1052         &clk_pclk_dsys,
1053         &clk_pclk_psys,
1054         &clk_vpllsrc,
1055         &clk_sclk_vpll,
1056         &clk_sclk_dac,
1057         &clk_sclk_pixel,
1058         &clk_sclk_hdmi,
1059         &clk_mout_dmc0,
1060         &clk_sclk_dmc0,
1061         &clk_sclk_audio0,
1062         &clk_sclk_audio1,
1063         &clk_sclk_audio2,
1064         &clk_sclk_spdif,
1065 };
1066
1067 static u32 epll_div[][6] = {
1068         {  48000000, 0, 48, 3, 3, 0 },
1069         {  96000000, 0, 48, 3, 2, 0 },
1070         { 144000000, 1, 72, 3, 2, 0 },
1071         { 192000000, 0, 48, 3, 1, 0 },
1072         { 288000000, 1, 72, 3, 1, 0 },
1073         {  32750000, 1, 65, 3, 4, 35127 },
1074         {  32768000, 1, 65, 3, 4, 35127 },
1075         {  45158400, 0, 45, 3, 3, 10355 },
1076         {  45000000, 0, 45, 3, 3, 10355 },
1077         {  45158000, 0, 45, 3, 3, 10355 },
1078         {  49125000, 0, 49, 3, 3, 9961 },
1079         {  49152000, 0, 49, 3, 3, 9961 },
1080         {  67737600, 1, 67, 3, 3, 48366 },
1081         {  67738000, 1, 67, 3, 3, 48366 },
1082         {  73800000, 1, 73, 3, 3, 47710 },
1083         {  73728000, 1, 73, 3, 3, 47710 },
1084         {  36000000, 1, 32, 3, 4, 0 },
1085         {  60000000, 1, 60, 3, 3, 0 },
1086         {  72000000, 1, 72, 3, 3, 0 },
1087         {  80000000, 1, 80, 3, 3, 0 },
1088         {  84000000, 0, 42, 3, 2, 0 },
1089         {  50000000, 0, 50, 3, 3, 0 },
1090 };
1091
1092 static int s5pv210_epll_set_rate(struct clk *clk, unsigned long rate)
1093 {
1094         unsigned int epll_con, epll_con_k;
1095         unsigned int i;
1096
1097         /* Return if nothing changed */
1098         if (clk->rate == rate)
1099                 return 0;
1100
1101         epll_con = __raw_readl(S5P_EPLL_CON);
1102         epll_con_k = __raw_readl(S5P_EPLL_CON1);
1103
1104         epll_con_k &= ~PLL46XX_KDIV_MASK;
1105         epll_con &= ~(1 << 27 |
1106                         PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |
1107                         PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT |
1108                         PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
1109
1110         for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
1111                 if (epll_div[i][0] == rate) {
1112                         epll_con_k |= epll_div[i][5] << 0;
1113                         epll_con |= (epll_div[i][1] << 27 |
1114                                         epll_div[i][2] << PLL46XX_MDIV_SHIFT |
1115                                         epll_div[i][3] << PLL46XX_PDIV_SHIFT |
1116                                         epll_div[i][4] << PLL46XX_SDIV_SHIFT);
1117                         break;
1118                 }
1119         }
1120
1121         if (i == ARRAY_SIZE(epll_div)) {
1122                 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
1123                                 __func__);
1124                 return -EINVAL;
1125         }
1126
1127         __raw_writel(epll_con, S5P_EPLL_CON);
1128         __raw_writel(epll_con_k, S5P_EPLL_CON1);
1129
1130         printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
1131                         clk->rate, rate);
1132
1133         clk->rate = rate;
1134
1135         return 0;
1136 }
1137
1138 static struct clk_ops s5pv210_epll_ops = {
1139         .set_rate = s5pv210_epll_set_rate,
1140         .get_rate = s5p_epll_get_rate,
1141 };
1142
1143 void __init_or_cpufreq s5pv210_setup_clocks(void)
1144 {
1145         struct clk *xtal_clk;
1146         unsigned long vpllsrc;
1147         unsigned long armclk;
1148         unsigned long hclk_msys;
1149         unsigned long hclk_dsys;
1150         unsigned long hclk_psys;
1151         unsigned long pclk_msys;
1152         unsigned long pclk_dsys;
1153         unsigned long pclk_psys;
1154         unsigned long apll;
1155         unsigned long mpll;
1156         unsigned long epll;
1157         unsigned long vpll;
1158         unsigned int ptr;
1159         u32 clkdiv0, clkdiv1;
1160
1161         /* Set functions for clk_fout_epll */
1162         clk_fout_epll.enable = s5p_epll_enable;
1163         clk_fout_epll.ops = &s5pv210_epll_ops;
1164
1165         printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1166
1167         clkdiv0 = __raw_readl(S5P_CLK_DIV0);
1168         clkdiv1 = __raw_readl(S5P_CLK_DIV1);
1169
1170         printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n",
1171                                 __func__, clkdiv0, clkdiv1);
1172
1173         xtal_clk = clk_get(NULL, "xtal");
1174         BUG_ON(IS_ERR(xtal_clk));
1175
1176         xtal = clk_get_rate(xtal_clk);
1177         clk_put(xtal_clk);
1178
1179         printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1180
1181         apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
1182         mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
1183         epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON),
1184                                 __raw_readl(S5P_EPLL_CON1), pll_4600);
1185         vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1186         vpll = s5p_get_pll45xx(vpllsrc, __raw_readl(S5P_VPLL_CON), pll_4502);
1187
1188         clk_fout_apll.ops = &clk_fout_apll_ops;
1189         clk_fout_mpll.rate = mpll;
1190         clk_fout_epll.rate = epll;
1191         clk_fout_vpll.rate = vpll;
1192
1193         printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1194                         apll, mpll, epll, vpll);
1195
1196         armclk = clk_get_rate(&clk_armclk.clk);
1197         hclk_msys = clk_get_rate(&clk_hclk_msys.clk);
1198         hclk_dsys = clk_get_rate(&clk_hclk_dsys.clk);
1199         hclk_psys = clk_get_rate(&clk_hclk_psys.clk);
1200         pclk_msys = clk_get_rate(&clk_pclk_msys.clk);
1201         pclk_dsys = clk_get_rate(&clk_pclk_dsys.clk);
1202         pclk_psys = clk_get_rate(&clk_pclk_psys.clk);
1203
1204         printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld\n"
1205                          "HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n",
1206                         armclk, hclk_msys, hclk_dsys, hclk_psys,
1207                         pclk_msys, pclk_dsys, pclk_psys);
1208
1209         clk_f.rate = armclk;
1210         clk_h.rate = hclk_psys;
1211         clk_p.rate = pclk_psys;
1212
1213         for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
1214                 s3c_set_clksrc(&clksrcs[ptr], true);
1215 }
1216
1217 static struct clk *clks[] __initdata = {
1218         &clk_sclk_hdmi27m,
1219         &clk_sclk_hdmiphy,
1220         &clk_sclk_usbphy0,
1221         &clk_sclk_usbphy1,
1222         &clk_pcmcdclk0,
1223         &clk_pcmcdclk1,
1224         &clk_pcmcdclk2,
1225 };
1226
1227 void __init s5pv210_register_clocks(void)
1228 {
1229         int ptr;
1230
1231         s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
1232
1233         for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1234                 s3c_register_clksrc(sysclks[ptr], 1);
1235
1236         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1237         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1238
1239         s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1240         s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1241
1242         s3c_pwmclk_init();
1243 }