arch/arm/mach-s5pc100/include/mach/irqs.h

   1 /* linux/arch/arm/mach-s5pc100/include/mach/irqs.h
   2  *
   3  * Copyright 2009 Samsung Electronics Co.
   4  *      Byungho Min <bhmin@samsung.com>
   5  *
   6  * S5PC100 - IRQ definitions
   7  */
   8
   9 #ifndef __ASM_ARCH_IRQS_H
  10 #define __ASM_ARCH_IRQS_H __FILE__
  11
  12 #include <plat/irqs.h>
  13
  14 /* VIC0: system, DMA, timer */
  15 #define IRQ_EINT16_31           S5P_IRQ_VIC0(16)
  16 #define IRQ_BATF                S5P_IRQ_VIC0(17)
  17 #define IRQ_MDMA                S5P_IRQ_VIC0(18)
  18 #define IRQ_PDMA0               S5P_IRQ_VIC0(19)
  19 #define IRQ_PDMA1               S5P_IRQ_VIC0(20)
  20 #define IRQ_TIMER0_VIC          S5P_IRQ_VIC0(21)
  21 #define IRQ_TIMER1_VIC          S5P_IRQ_VIC0(22)
  22 #define IRQ_TIMER2_VIC          S5P_IRQ_VIC0(23)
  23 #define IRQ_TIMER3_VIC          S5P_IRQ_VIC0(24)
  24 #define IRQ_TIMER4_VIC          S5P_IRQ_VIC0(25)
  25 #define IRQ_SYSTIMER            S5P_IRQ_VIC0(26)
  26 #define IRQ_WDT                 S5P_IRQ_VIC0(27)
  27 #define IRQ_RTC_ALARM           S5P_IRQ_VIC0(28)
  28 #define IRQ_RTC_TIC             S5P_IRQ_VIC0(29)
  29 #define IRQ_GPIOINT             S5P_IRQ_VIC0(30)
  30
  31 /* VIC1: ARM, power, memory, connectivity */
  32 #define IRQ_CORTEX0             S5P_IRQ_VIC1(0)
  33 #define IRQ_CORTEX1             S5P_IRQ_VIC1(1)
  34 #define IRQ_CORTEX2             S5P_IRQ_VIC1(2)
  35 #define IRQ_CORTEX3             S5P_IRQ_VIC1(3)
  36 #define IRQ_CORTEX4             S5P_IRQ_VIC1(4)
  37 #define IRQ_IEMAPC              S5P_IRQ_VIC1(5)
  38 #define IRQ_IEMIEC              S5P_IRQ_VIC1(6)
  39 #define IRQ_ONENAND             S5P_IRQ_VIC1(7)
  40 #define IRQ_NFC                 S5P_IRQ_VIC1(8)
  41 #define IRQ_CFC                 S5P_IRQ_VIC1(9)
  42 #define IRQ_UART0               S5P_IRQ_VIC1(10)
  43 #define IRQ_UART1               S5P_IRQ_VIC1(11)
  44 #define IRQ_UART2               S5P_IRQ_VIC1(12)
  45 #define IRQ_UART3               S5P_IRQ_VIC1(13)
  46 #define IRQ_IIC                 S5P_IRQ_VIC1(14)
  47 #define IRQ_SPI0                S5P_IRQ_VIC1(15)
  48 #define IRQ_SPI1                S5P_IRQ_VIC1(16)
  49 #define IRQ_SPI2                S5P_IRQ_VIC1(17)
  50 #define IRQ_IRDA                S5P_IRQ_VIC1(18)
  51 #define IRQ_CAN0                S5P_IRQ_VIC1(19)
  52 #define IRQ_CAN1                S5P_IRQ_VIC1(20)
  53 #define IRQ_HSIRX               S5P_IRQ_VIC1(21)
  54 #define IRQ_HSITX               S5P_IRQ_VIC1(22)
  55 #define IRQ_UHOST               S5P_IRQ_VIC1(23)
  56 #define IRQ_OTG                 S5P_IRQ_VIC1(24)
  57 #define IRQ_MSM                 S5P_IRQ_VIC1(25)
  58 #define IRQ_HSMMC0              S5P_IRQ_VIC1(26)
  59 #define IRQ_HSMMC1              S5P_IRQ_VIC1(27)
  60 #define IRQ_HSMMC2              S5P_IRQ_VIC1(28)
  61 #define IRQ_MIPICSI             S5P_IRQ_VIC1(29)
  62 #define IRQ_MIPIDSI             S5P_IRQ_VIC1(30)
  63
  64 /* VIC2: multimedia, audio, security */
  65 #define IRQ_LCD0                S5P_IRQ_VIC2(0)
  66 #define IRQ_LCD1                S5P_IRQ_VIC2(1)
  67 #define IRQ_LCD2                S5P_IRQ_VIC2(2)
  68 #define IRQ_LCD3                S5P_IRQ_VIC2(3)
  69 #define IRQ_ROTATOR             S5P_IRQ_VIC2(4)
  70 #define IRQ_FIMC0               S5P_IRQ_VIC2(5)
  71 #define IRQ_FIMC1               S5P_IRQ_VIC2(6)
  72 #define IRQ_FIMC2               S5P_IRQ_VIC2(7)
  73 #define IRQ_JPEG                S5P_IRQ_VIC2(8)
  74 #define IRQ_2D                  S5P_IRQ_VIC2(9)
  75 #define IRQ_3D                  S5P_IRQ_VIC2(10)
  76 #define IRQ_MIXER               S5P_IRQ_VIC2(11)
  77 #define IRQ_HDMI                S5P_IRQ_VIC2(12)
  78 #define IRQ_IIC1                S5P_IRQ_VIC2(13)
  79 #define IRQ_MFC                 S5P_IRQ_VIC2(14)
  80 #define IRQ_TVENC               S5P_IRQ_VIC2(15)
  81 #define IRQ_I2S0                S5P_IRQ_VIC2(16)
  82 #define IRQ_I2S1                S5P_IRQ_VIC2(17)
  83 #define IRQ_I2S2                S5P_IRQ_VIC2(18)
  84 #define IRQ_AC97                S5P_IRQ_VIC2(19)
  85 #define IRQ_PCM0                S5P_IRQ_VIC2(20)
  86 #define IRQ_PCM1                S5P_IRQ_VIC2(21)
  87 #define IRQ_SPDIF               S5P_IRQ_VIC2(22)
  88 #define IRQ_ADC                 S5P_IRQ_VIC2(23)
  89 #define IRQ_PENDN               S5P_IRQ_VIC2(24)
  90 #define IRQ_TC                  IRQ_PENDN
  91 #define IRQ_KEYPAD              S5P_IRQ_VIC2(25)
  92 #define IRQ_CG                  S5P_IRQ_VIC2(26)
  93 #define IRQ_SEC                 S5P_IRQ_VIC2(27)
  94 #define IRQ_SECRX               S5P_IRQ_VIC2(28)
  95 #define IRQ_SECTX               S5P_IRQ_VIC2(29)
  96 #define IRQ_SDMIRQ              S5P_IRQ_VIC2(30)
  97 #define IRQ_SDMFIQ              S5P_IRQ_VIC2(31)
  98 #define IRQ_VIC_END             S5P_IRQ_VIC2(31)
  99
 100 #define S5P_EINT_BASE1          (S5P_IRQ_VIC0(0))
 101 #define S5P_EINT_BASE2          (IRQ_VIC_END + 1)
 102
 103 #define S3C_IRQ_GPIO_BASE       (IRQ_EINT(31) + 1)
 104 #define S3C_IRQ_GPIO(x)         (S3C_IRQ_GPIO_BASE + (x))
 105
 106 /* Until MP04 Groups -> 40 (exactly 39) Groups * 8 ~= 320 GPIOs */
 107 #define NR_IRQS         (S3C_IRQ_GPIO(320) + 1)
 108
 109 /* Compatibility */
 110 #define IRQ_LCD_FIFO            IRQ_LCD0
 111 #define IRQ_LCD_VSYNC           IRQ_LCD1
 112 #define IRQ_LCD_SYSTEM          IRQ_LCD2
 113
 114 #endif /* __ASM_ARCH_IRQS_H */