arch/arm/mach-s5pc100/dev-spi.c

   1 /* linux/arch/arm/mach-s5pc100/dev-spi.c
   2  *
   3  * Copyright (C) 2010 Samsung Electronics Co. Ltd.
   4  *      Jaswinder Singh <jassi.brar@samsung.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/platform_device.h>
  12 #include <linux/dma-mapping.h>
  13 #include <linux/gpio.h>
  14
  15 #include <mach/dma.h>
  16 #include <mach/map.h>
  17 #include <mach/spi-clocks.h>
  18 #include <mach/irqs.h>
  19
  20 #include <plat/s3c64xx-spi.h>
  21 #include <plat/gpio-cfg.h>
  22 #include <plat/irqs.h>
  23
  24 static char *spi_src_clks[] = {
  25         [S5PC100_SPI_SRCCLK_PCLK] = "pclk",
  26         [S5PC100_SPI_SRCCLK_48M] = "spi_48m",
  27         [S5PC100_SPI_SRCCLK_SPIBUS] = "spi_bus",
  28 };
  29
  30 /* SPI Controller platform_devices */
  31
  32 /* Since we emulate multi-cs capability, we do not touch the CS.
  33  * The emulated CS is toggled by board specific mechanism, as it can
  34  * be either some immediate GPIO or some signal out of some other
  35  * chip in between ... or some yet another way.
  36  * We simply do not assume anything about CS.
  37  */
  38 static int s5pc100_spi_cfg_gpio(struct platform_device *pdev)
  39 {
  40         switch (pdev->id) {
  41         case 0:
  42                 s3c_gpio_cfgall_range(S5PC100_GPB(0), 3,
  43                                       S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
  44                 break;
  45
  46         case 1:
  47                 s3c_gpio_cfgall_range(S5PC100_GPB(4), 3,
  48                                       S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
  49                 break;
  50
  51         case 2:
  52                 s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(3));
  53                 s3c_gpio_setpull(S5PC100_GPG3(0), S3C_GPIO_PULL_UP);
  54                 s3c_gpio_cfgall_range(S5PC100_GPB(2), 2,
  55                                       S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
  56                 break;
  57
  58         default:
  59                 dev_err(&pdev->dev, "Invalid SPI Controller number!");
  60                 return -EINVAL;
  61         }
  62
  63         return 0;
  64 }
  65
  66 static struct resource s5pc100_spi0_resource[] = {
  67         [0] = {
  68                 .start = S5PC100_PA_SPI0,
  69                 .end   = S5PC100_PA_SPI0 + 0x100 - 1,
  70                 .flags = IORESOURCE_MEM,
  71         },
  72         [1] = {
  73                 .start = DMACH_SPI0_TX,
  74                 .end   = DMACH_SPI0_TX,
  75                 .flags = IORESOURCE_DMA,
  76         },
  77         [2] = {
  78                 .start = DMACH_SPI0_RX,
  79                 .end   = DMACH_SPI0_RX,
  80                 .flags = IORESOURCE_DMA,
  81         },
  82         [3] = {
  83                 .start = IRQ_SPI0,
  84                 .end   = IRQ_SPI0,
  85                 .flags = IORESOURCE_IRQ,
  86         },
  87 };
  88
  89 static struct s3c64xx_spi_info s5pc100_spi0_pdata = {
  90         .cfg_gpio = s5pc100_spi_cfg_gpio,
  91         .fifo_lvl_mask = 0x7f,
  92         .rx_lvl_offset = 13,
  93         .high_speed = 1,
  94         .tx_st_done = 21,
  95 };
  96
  97 static u64 spi_dmamask = DMA_BIT_MASK(32);
  98
  99 struct platform_device s5pc100_device_spi0 = {
 100         .name             = "s3c64xx-spi",
 101         .id               = 0,
 102         .num_resources    = ARRAY_SIZE(s5pc100_spi0_resource),
 103         .resource         = s5pc100_spi0_resource,
 104         .dev = {
 105                 .dma_mask               = &spi_dmamask,
 106                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 107                 .platform_data = &s5pc100_spi0_pdata,
 108         },
 109 };
 110
 111 static struct resource s5pc100_spi1_resource[] = {
 112         [0] = {
 113                 .start = S5PC100_PA_SPI1,
 114                 .end   = S5PC100_PA_SPI1 + 0x100 - 1,
 115                 .flags = IORESOURCE_MEM,
 116         },
 117         [1] = {
 118                 .start = DMACH_SPI1_TX,
 119                 .end   = DMACH_SPI1_TX,
 120                 .flags = IORESOURCE_DMA,
 121         },
 122         [2] = {
 123                 .start = DMACH_SPI1_RX,
 124                 .end   = DMACH_SPI1_RX,
 125                 .flags = IORESOURCE_DMA,
 126         },
 127         [3] = {
 128                 .start = IRQ_SPI1,
 129                 .end   = IRQ_SPI1,
 130                 .flags = IORESOURCE_IRQ,
 131         },
 132 };
 133
 134 static struct s3c64xx_spi_info s5pc100_spi1_pdata = {
 135         .cfg_gpio = s5pc100_spi_cfg_gpio,
 136         .fifo_lvl_mask = 0x7f,
 137         .rx_lvl_offset = 13,
 138         .high_speed = 1,
 139         .tx_st_done = 21,
 140 };
 141
 142 struct platform_device s5pc100_device_spi1 = {
 143         .name             = "s3c64xx-spi",
 144         .id               = 1,
 145         .num_resources    = ARRAY_SIZE(s5pc100_spi1_resource),
 146         .resource         = s5pc100_spi1_resource,
 147         .dev = {
 148                 .dma_mask               = &spi_dmamask,
 149                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 150                 .platform_data = &s5pc100_spi1_pdata,
 151         },
 152 };
 153
 154 static struct resource s5pc100_spi2_resource[] = {
 155         [0] = {
 156                 .start = S5PC100_PA_SPI2,
 157                 .end   = S5PC100_PA_SPI2 + 0x100 - 1,
 158                 .flags = IORESOURCE_MEM,
 159         },
 160         [1] = {
 161                 .start = DMACH_SPI2_TX,
 162                 .end   = DMACH_SPI2_TX,
 163                 .flags = IORESOURCE_DMA,
 164         },
 165         [2] = {
 166                 .start = DMACH_SPI2_RX,
 167                 .end   = DMACH_SPI2_RX,
 168                 .flags = IORESOURCE_DMA,
 169         },
 170         [3] = {
 171                 .start = IRQ_SPI2,
 172                 .end   = IRQ_SPI2,
 173                 .flags = IORESOURCE_IRQ,
 174         },
 175 };
 176
 177 static struct s3c64xx_spi_info s5pc100_spi2_pdata = {
 178         .cfg_gpio = s5pc100_spi_cfg_gpio,
 179         .fifo_lvl_mask = 0x7f,
 180         .rx_lvl_offset = 13,
 181         .high_speed = 1,
 182         .tx_st_done = 21,
 183 };
 184
 185 struct platform_device s5pc100_device_spi2 = {
 186         .name             = "s3c64xx-spi",
 187         .id               = 2,
 188         .num_resources    = ARRAY_SIZE(s5pc100_spi2_resource),
 189         .resource         = s5pc100_spi2_resource,
 190         .dev = {
 191                 .dma_mask               = &spi_dmamask,
 192                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 193                 .platform_data = &s5pc100_spi2_pdata,
 194         },
 195 };
 196
 197 void __init s5pc100_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
 198 {
 199         struct s3c64xx_spi_info *pd;
 200
 201         /* Reject invalid configuration */
 202         if (!num_cs || src_clk_nr < 0
 203                         || src_clk_nr > S5PC100_SPI_SRCCLK_SPIBUS) {
 204                 printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
 205                 return;
 206         }
 207
 208         switch (cntrlr) {
 209         case 0:
 210                 pd = &s5pc100_spi0_pdata;
 211                 break;
 212         case 1:
 213                 pd = &s5pc100_spi1_pdata;
 214                 break;
 215         case 2:
 216                 pd = &s5pc100_spi2_pdata;
 217                 break;
 218         default:
 219                 printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
 220                                                         __func__, cntrlr);
 221                 return;
 222         }
 223
 224         pd->num_cs = num_cs;
 225         pd->src_clk_nr = src_clk_nr;
 226         pd->src_clk_name = spi_src_clks[src_clk_nr];
 227 }