arch/arm/mach-s5pc100/dev-spi.c

   1 /* linux/arch/arm/mach-s5pc100/dev-spi.c
   2  *
   3  * Copyright (C) 2010 Samsung Electronics Co. Ltd.
   4  *      Jaswinder Singh <jassi.brar@samsung.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/platform_device.h>
  12 #include <linux/dma-mapping.h>
  13 #include <linux/gpio.h>
  14
  15 #include <mach/dma.h>
  16 #include <mach/map.h>
  17 #include <mach/spi-clocks.h>
  18
  19 #include <plat/s3c64xx-spi.h>
  20 #include <plat/gpio-cfg.h>
  21 #include <plat/irqs.h>
  22
  23 static char *spi_src_clks[] = {
  24         [S5PC100_SPI_SRCCLK_PCLK] = "pclk",
  25         [S5PC100_SPI_SRCCLK_48M] = "spi_48m",
  26         [S5PC100_SPI_SRCCLK_SPIBUS] = "spi_bus",
  27 };
  28
  29 /* SPI Controller platform_devices */
  30
  31 /* Since we emulate multi-cs capability, we do not touch the CS.
  32  * The emulated CS is toggled by board specific mechanism, as it can
  33  * be either some immediate GPIO or some signal out of some other
  34  * chip in between ... or some yet another way.
  35  * We simply do not assume anything about CS.
  36  */
  37 static int s5pc100_spi_cfg_gpio(struct platform_device *pdev)
  38 {
  39         switch (pdev->id) {
  40         case 0:
  41                 s3c_gpio_cfgall_range(S5PC100_GPB(0), 3,
  42                                       S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
  43                 break;
  44
  45         case 1:
  46                 s3c_gpio_cfgall_range(S5PC100_GPB(4), 3,
  47                                       S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
  48                 break;
  49
  50         case 2:
  51                 s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(3));
  52                 s3c_gpio_setpull(S5PC100_GPG3(0), S3C_GPIO_PULL_UP);
  53                 s3c_gpio_cfgall_range(S5PC100_GPB(2), 2,
  54                                       S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
  55                 break;
  56
  57         default:
  58                 dev_err(&pdev->dev, "Invalid SPI Controller number!");
  59                 return -EINVAL;
  60         }
  61
  62         return 0;
  63 }
  64
  65 static struct resource s5pc100_spi0_resource[] = {
  66         [0] = {
  67                 .start = S5PC100_PA_SPI0,
  68                 .end   = S5PC100_PA_SPI0 + 0x100 - 1,
  69                 .flags = IORESOURCE_MEM,
  70         },
  71         [1] = {
  72                 .start = DMACH_SPI0_TX,
  73                 .end   = DMACH_SPI0_TX,
  74                 .flags = IORESOURCE_DMA,
  75         },
  76         [2] = {
  77                 .start = DMACH_SPI0_RX,
  78                 .end   = DMACH_SPI0_RX,
  79                 .flags = IORESOURCE_DMA,
  80         },
  81         [3] = {
  82                 .start = IRQ_SPI0,
  83                 .end   = IRQ_SPI0,
  84                 .flags = IORESOURCE_IRQ,
  85         },
  86 };
  87
  88 static struct s3c64xx_spi_info s5pc100_spi0_pdata = {
  89         .cfg_gpio = s5pc100_spi_cfg_gpio,
  90         .fifo_lvl_mask = 0x7f,
  91         .rx_lvl_offset = 13,
  92         .high_speed = 1,
  93         .tx_st_done = 21,
  94 };
  95
  96 static u64 spi_dmamask = DMA_BIT_MASK(32);
  97
  98 struct platform_device s5pc100_device_spi0 = {
  99         .name             = "s3c64xx-spi",
 100         .id               = 0,
 101         .num_resources    = ARRAY_SIZE(s5pc100_spi0_resource),
 102         .resource         = s5pc100_spi0_resource,
 103         .dev = {
 104                 .dma_mask               = &spi_dmamask,
 105                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 106                 .platform_data = &s5pc100_spi0_pdata,
 107         },
 108 };
 109
 110 static struct resource s5pc100_spi1_resource[] = {
 111         [0] = {
 112                 .start = S5PC100_PA_SPI1,
 113                 .end   = S5PC100_PA_SPI1 + 0x100 - 1,
 114                 .flags = IORESOURCE_MEM,
 115         },
 116         [1] = {
 117                 .start = DMACH_SPI1_TX,
 118                 .end   = DMACH_SPI1_TX,
 119                 .flags = IORESOURCE_DMA,
 120         },
 121         [2] = {
 122                 .start = DMACH_SPI1_RX,
 123                 .end   = DMACH_SPI1_RX,
 124                 .flags = IORESOURCE_DMA,
 125         },
 126         [3] = {
 127                 .start = IRQ_SPI1,
 128                 .end   = IRQ_SPI1,
 129                 .flags = IORESOURCE_IRQ,
 130         },
 131 };
 132
 133 static struct s3c64xx_spi_info s5pc100_spi1_pdata = {
 134         .cfg_gpio = s5pc100_spi_cfg_gpio,
 135         .fifo_lvl_mask = 0x7f,
 136         .rx_lvl_offset = 13,
 137         .high_speed = 1,
 138         .tx_st_done = 21,
 139 };
 140
 141 struct platform_device s5pc100_device_spi1 = {
 142         .name             = "s3c64xx-spi",
 143         .id               = 1,
 144         .num_resources    = ARRAY_SIZE(s5pc100_spi1_resource),
 145         .resource         = s5pc100_spi1_resource,
 146         .dev = {
 147                 .dma_mask               = &spi_dmamask,
 148                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 149                 .platform_data = &s5pc100_spi1_pdata,
 150         },
 151 };
 152
 153 static struct resource s5pc100_spi2_resource[] = {
 154         [0] = {
 155                 .start = S5PC100_PA_SPI2,
 156                 .end   = S5PC100_PA_SPI2 + 0x100 - 1,
 157                 .flags = IORESOURCE_MEM,
 158         },
 159         [1] = {
 160                 .start = DMACH_SPI2_TX,
 161                 .end   = DMACH_SPI2_TX,
 162                 .flags = IORESOURCE_DMA,
 163         },
 164         [2] = {
 165                 .start = DMACH_SPI2_RX,
 166                 .end   = DMACH_SPI2_RX,
 167                 .flags = IORESOURCE_DMA,
 168         },
 169         [3] = {
 170                 .start = IRQ_SPI2,
 171                 .end   = IRQ_SPI2,
 172                 .flags = IORESOURCE_IRQ,
 173         },
 174 };
 175
 176 static struct s3c64xx_spi_info s5pc100_spi2_pdata = {
 177         .cfg_gpio = s5pc100_spi_cfg_gpio,
 178         .fifo_lvl_mask = 0x7f,
 179         .rx_lvl_offset = 13,
 180         .high_speed = 1,
 181         .tx_st_done = 21,
 182 };
 183
 184 struct platform_device s5pc100_device_spi2 = {
 185         .name             = "s3c64xx-spi",
 186         .id               = 2,
 187         .num_resources    = ARRAY_SIZE(s5pc100_spi2_resource),
 188         .resource         = s5pc100_spi2_resource,
 189         .dev = {
 190                 .dma_mask               = &spi_dmamask,
 191                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 192                 .platform_data = &s5pc100_spi2_pdata,
 193         },
 194 };
 195
 196 void __init s5pc100_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
 197 {
 198         struct s3c64xx_spi_info *pd;
 199
 200         /* Reject invalid configuration */
 201         if (!num_cs || src_clk_nr < 0
 202                         || src_clk_nr > S5PC100_SPI_SRCCLK_SPIBUS) {
 203                 printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
 204                 return;
 205         }
 206
 207         switch (cntrlr) {
 208         case 0:
 209                 pd = &s5pc100_spi0_pdata;
 210                 break;
 211         case 1:
 212                 pd = &s5pc100_spi1_pdata;
 213                 break;
 214         case 2:
 215                 pd = &s5pc100_spi2_pdata;
 216                 break;
 217         default:
 218                 printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
 219                                                         __func__, cntrlr);
 220                 return;
 221         }
 222
 223         pd->num_cs = num_cs;
 224         pd->src_clk_nr = src_clk_nr;
 225         pd->src_clk_name = spi_src_clks[src_clk_nr];
 226 }