arch/arm/mach-s5p64x0/irq-eint.c

   1 /* arch/arm/mach-s5p64x0/irq-eint.c
   2  *
   3  * Copyright (c) 2011 Samsung Electronics Co., Ltd
   4  *              http://www.samsung.com/
   5  *
   6  * Based on linux/arch/arm/mach-s3c64xx/irq-eint.c
   7  *
   8  * S5P64X0 - Interrupt handling for External Interrupts.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/gpio.h>
  17 #include <linux/irq.h>
  18 #include <linux/io.h>
  19
  20 #include <plat/cpu.h>
  21 #include <plat/regs-irqtype.h>
  22 #include <plat/gpio-cfg.h>
  23
  24 #include <mach/regs-gpio.h>
  25 #include <mach/regs-clock.h>
  26
  27 #define eint_offset(irq)        ((irq) - IRQ_EINT(0))
  28
  29 static int s5p64x0_irq_eint_set_type(struct irq_data *data, unsigned int type)
  30 {
  31         int offs = eint_offset(data->irq);
  32         int shift;
  33         u32 ctrl, mask;
  34         u32 newvalue = 0;
  35
  36         if (offs > 15)
  37                 return -EINVAL;
  38
  39         switch (type) {
  40         case IRQ_TYPE_NONE:
  41                 printk(KERN_WARNING "No edge setting!\n");
  42                 break;
  43         case IRQ_TYPE_EDGE_RISING:
  44                 newvalue = S3C2410_EXTINT_RISEEDGE;
  45                 break;
  46         case IRQ_TYPE_EDGE_FALLING:
  47                 newvalue = S3C2410_EXTINT_FALLEDGE;
  48                 break;
  49         case IRQ_TYPE_EDGE_BOTH:
  50                 newvalue = S3C2410_EXTINT_BOTHEDGE;
  51                 break;
  52         case IRQ_TYPE_LEVEL_LOW:
  53                 newvalue = S3C2410_EXTINT_LOWLEV;
  54                 break;
  55         case IRQ_TYPE_LEVEL_HIGH:
  56                 newvalue = S3C2410_EXTINT_HILEV;
  57                 break;
  58         default:
  59                 printk(KERN_ERR "No such irq type %d", type);
  60                 return -EINVAL;
  61         }
  62
  63         shift = (offs / 2) * 4;
  64         mask = 0x7 << shift;
  65
  66         ctrl = __raw_readl(S5P64X0_EINT0CON0) & ~mask;
  67         ctrl |= newvalue << shift;
  68         __raw_writel(ctrl, S5P64X0_EINT0CON0);
  69
  70         /* Configure the GPIO pin for 6450 or 6440 based on CPU ID */
  71         if (soc_is_s5p6450())
  72                 s3c_gpio_cfgpin(S5P6450_GPN(offs), S3C_GPIO_SFN(2));
  73         else
  74                 s3c_gpio_cfgpin(S5P6440_GPN(offs), S3C_GPIO_SFN(2));
  75
  76         return 0;
  77 }
  78
  79 /*
  80  * s5p64x0_irq_demux_eint
  81  *
  82  * This function demuxes the IRQ from the group0 external interrupts,
  83  * from IRQ_EINT(0) to IRQ_EINT(15). It is designed to be inlined into
  84  * the specific handlers s5p64x0_irq_demux_eintX_Y.
  85  */
  86 static inline void s5p64x0_irq_demux_eint(unsigned int start, unsigned int end)
  87 {
  88         u32 status = __raw_readl(S5P64X0_EINT0PEND);
  89         u32 mask = __raw_readl(S5P64X0_EINT0MASK);
  90         unsigned int irq;
  91
  92         status &= ~mask;
  93         status >>= start;
  94         status &= (1 << (end - start + 1)) - 1;
  95
  96         for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
  97                 if (status & 1)
  98                         generic_handle_irq(irq);
  99                 status >>= 1;
 100         }
 101 }
 102
 103 static void s5p64x0_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
 104 {
 105         s5p64x0_irq_demux_eint(0, 3);
 106 }
 107
 108 static void s5p64x0_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
 109 {
 110         s5p64x0_irq_demux_eint(4, 11);
 111 }
 112
 113 static void s5p64x0_irq_demux_eint12_15(unsigned int irq,
 114                                         struct irq_desc *desc)
 115 {
 116         s5p64x0_irq_demux_eint(12, 15);
 117 }
 118
 119 static int s5p64x0_alloc_gc(void)
 120 {
 121         struct irq_chip_generic *gc;
 122         struct irq_chip_type *ct;
 123
 124         gc = irq_alloc_generic_chip("s5p64x0-eint", 1, S5P_IRQ_EINT_BASE,
 125                                     S5P_VA_GPIO, handle_level_irq);
 126         if (!gc) {
 127                 printk(KERN_ERR "%s: irq_alloc_generic_chip for group 0"
 128                         "external interrupts failed\n", __func__);
 129                 return -EINVAL;
 130         }
 131
 132         ct = gc->chip_types;
 133         ct->chip.irq_ack = irq_gc_ack_set_bit;
 134         ct->chip.irq_mask = irq_gc_mask_set_bit;
 135         ct->chip.irq_unmask = irq_gc_mask_clr_bit;
 136         ct->chip.irq_set_type = s5p64x0_irq_eint_set_type;
 137         ct->regs.ack = EINT0PEND_OFFSET;
 138         ct->regs.mask = EINT0MASK_OFFSET;
 139         irq_setup_generic_chip(gc, IRQ_MSK(16), IRQ_GC_INIT_MASK_CACHE,
 140                                IRQ_NOREQUEST | IRQ_NOPROBE, 0);
 141         return 0;
 142 }
 143
 144 static int __init s5p64x0_init_irq_eint(void)
 145 {
 146         int ret = s5p64x0_alloc_gc();
 147         irq_set_chained_handler(IRQ_EINT0_3, s5p64x0_irq_demux_eint0_3);
 148         irq_set_chained_handler(IRQ_EINT4_11, s5p64x0_irq_demux_eint4_11);
 149         irq_set_chained_handler(IRQ_EINT12_15, s5p64x0_irq_demux_eint12_15);
 150
 151         return ret;
 152 }
 153 arch_initcall(s5p64x0_init_irq_eint);