arch/arm/mach-s5p64x0/dev-spi.c

   1 /* linux/arch/arm/mach-s5p64x0/dev-spi.c
   2  *
   3  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * Copyright (C) 2010 Samsung Electronics Co. Ltd.
   7  *      Jaswinder Singh <jassi.brar@samsung.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12 */
  13
  14 #include <linux/platform_device.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/gpio.h>
  17
  18 #include <mach/dma.h>
  19 #include <mach/map.h>
  20 #include <mach/irqs.h>
  21 #include <mach/regs-clock.h>
  22 #include <mach/spi-clocks.h>
  23
  24 #include <plat/s3c64xx-spi.h>
  25 #include <plat/gpio-cfg.h>
  26
  27 static char *s5p64x0_spi_src_clks[] = {
  28         [S5P64X0_SPI_SRCCLK_PCLK] = "pclk",
  29         [S5P64X0_SPI_SRCCLK_SCLK] = "sclk_spi",
  30 };
  31
  32 /* SPI Controller platform_devices */
  33
  34 /* Since we emulate multi-cs capability, we do not touch the CS.
  35  * The emulated CS is toggled by board specific mechanism, as it can
  36  * be either some immediate GPIO or some signal out of some other
  37  * chip in between ... or some yet another way.
  38  * We simply do not assume anything about CS.
  39  */
  40 static int s5p6440_spi_cfg_gpio(struct platform_device *pdev)
  41 {
  42         unsigned int base;
  43
  44         switch (pdev->id) {
  45         case 0:
  46                 base = S5P6440_GPC(0);
  47                 break;
  48
  49         case 1:
  50                 base = S5P6440_GPC(4);
  51                 break;
  52
  53         default:
  54                 dev_err(&pdev->dev, "Invalid SPI Controller number!");
  55                 return -EINVAL;
  56         }
  57
  58         s3c_gpio_cfgall_range(base, 3,
  59                               S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
  60
  61         return 0;
  62 }
  63
  64 static int s5p6450_spi_cfg_gpio(struct platform_device *pdev)
  65 {
  66         unsigned int base;
  67
  68         switch (pdev->id) {
  69         case 0:
  70                 base = S5P6450_GPC(0);
  71                 break;
  72
  73         case 1:
  74                 base = S5P6450_GPC(4);
  75                 break;
  76
  77         default:
  78                 dev_err(&pdev->dev, "Invalid SPI Controller number!");
  79                 return -EINVAL;
  80         }
  81
  82         s3c_gpio_cfgall_range(base, 3,
  83                               S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
  84
  85         return 0;
  86 }
  87
  88 static struct resource s5p64x0_spi0_resource[] = {
  89         [0] = {
  90                 .start  = S5P64X0_PA_SPI0,
  91                 .end    = S5P64X0_PA_SPI0 + 0x100 - 1,
  92                 .flags  = IORESOURCE_MEM,
  93         },
  94         [1] = {
  95                 .start  = DMACH_SPI0_TX,
  96                 .end    = DMACH_SPI0_TX,
  97                 .flags  = IORESOURCE_DMA,
  98         },
  99         [2] = {
 100                 .start  = DMACH_SPI0_RX,
 101                 .end    = DMACH_SPI0_RX,
 102                 .flags  = IORESOURCE_DMA,
 103         },
 104         [3] = {
 105                 .start  = IRQ_SPI0,
 106                 .end    = IRQ_SPI0,
 107                 .flags  = IORESOURCE_IRQ,
 108         },
 109 };
 110
 111 static struct s3c64xx_spi_info s5p6440_spi0_pdata = {
 112         .cfg_gpio       = s5p6440_spi_cfg_gpio,
 113         .fifo_lvl_mask  = 0x1ff,
 114         .rx_lvl_offset  = 15,
 115         .tx_st_done     = 25,
 116 };
 117
 118 static struct s3c64xx_spi_info s5p6450_spi0_pdata = {
 119         .cfg_gpio       = s5p6450_spi_cfg_gpio,
 120         .fifo_lvl_mask  = 0x1ff,
 121         .rx_lvl_offset  = 15,
 122         .tx_st_done     = 25,
 123 };
 124
 125 static u64 spi_dmamask = DMA_BIT_MASK(32);
 126
 127 struct platform_device s5p64x0_device_spi0 = {
 128         .name           = "s3c64xx-spi",
 129         .id             = 0,
 130         .num_resources  = ARRAY_SIZE(s5p64x0_spi0_resource),
 131         .resource       = s5p64x0_spi0_resource,
 132         .dev = {
 133                 .dma_mask               = &spi_dmamask,
 134                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 135         },
 136 };
 137
 138 static struct resource s5p64x0_spi1_resource[] = {
 139         [0] = {
 140                 .start  = S5P64X0_PA_SPI1,
 141                 .end    = S5P64X0_PA_SPI1 + 0x100 - 1,
 142                 .flags  = IORESOURCE_MEM,
 143         },
 144         [1] = {
 145                 .start  = DMACH_SPI1_TX,
 146                 .end    = DMACH_SPI1_TX,
 147                 .flags  = IORESOURCE_DMA,
 148         },
 149         [2] = {
 150                 .start  = DMACH_SPI1_RX,
 151                 .end    = DMACH_SPI1_RX,
 152                 .flags  = IORESOURCE_DMA,
 153         },
 154         [3] = {
 155                 .start  = IRQ_SPI1,
 156                 .end    = IRQ_SPI1,
 157                 .flags  = IORESOURCE_IRQ,
 158         },
 159 };
 160
 161 static struct s3c64xx_spi_info s5p6440_spi1_pdata = {
 162         .cfg_gpio       = s5p6440_spi_cfg_gpio,
 163         .fifo_lvl_mask  = 0x7f,
 164         .rx_lvl_offset  = 15,
 165         .tx_st_done     = 25,
 166 };
 167
 168 static struct s3c64xx_spi_info s5p6450_spi1_pdata = {
 169         .cfg_gpio       = s5p6450_spi_cfg_gpio,
 170         .fifo_lvl_mask  = 0x7f,
 171         .rx_lvl_offset  = 15,
 172         .tx_st_done     = 25,
 173 };
 174
 175 struct platform_device s5p64x0_device_spi1 = {
 176         .name           = "s3c64xx-spi",
 177         .id             = 1,
 178         .num_resources  = ARRAY_SIZE(s5p64x0_spi1_resource),
 179         .resource       = s5p64x0_spi1_resource,
 180         .dev = {
 181                 .dma_mask               = &spi_dmamask,
 182                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 183         },
 184 };
 185
 186 void __init s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
 187 {
 188         unsigned int id;
 189         struct s3c64xx_spi_info *pd;
 190
 191         id = __raw_readl(S5P64X0_SYS_ID) & 0xFF000;
 192
 193         /* Reject invalid configuration */
 194         if (!num_cs || src_clk_nr < 0
 195                         || src_clk_nr > S5P64X0_SPI_SRCCLK_SCLK) {
 196                 printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
 197                 return;
 198         }
 199
 200         switch (cntrlr) {
 201         case 0:
 202                 if (id == 0x50000)
 203                         pd = &s5p6450_spi0_pdata;
 204                 else
 205                         pd = &s5p6440_spi0_pdata;
 206
 207                 s5p64x0_device_spi0.dev.platform_data = pd;
 208                 break;
 209         case 1:
 210                 if (id == 0x50000)
 211                         pd = &s5p6450_spi1_pdata;
 212                 else
 213                         pd = &s5p6440_spi1_pdata;
 214
 215                 s5p64x0_device_spi1.dev.platform_data = pd;
 216                 break;
 217         default:
 218                 printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
 219                                                         __func__, cntrlr);
 220                 return;
 221         }
 222
 223         pd->num_cs = num_cs;
 224         pd->src_clk_nr = src_clk_nr;
 225         pd->src_clk_name = s5p64x0_spi_src_clks[src_clk_nr];
 226 }