arch/arm/mach-s5p64x0/clock-s5p6450.c

   1 /* linux/arch/arm/mach-s5p64x0/clock-s5p6450.c
   2  *
   3  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * S5P6450 - Clock support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #include <linux/init.h>
  14 #include <linux/module.h>
  15 #include <linux/kernel.h>
  16 #include <linux/list.h>
  17 #include <linux/errno.h>
  18 #include <linux/err.h>
  19 #include <linux/clk.h>
  20 #include <linux/sysdev.h>
  21 #include <linux/io.h>
  22
  23 #include <mach/hardware.h>
  24 #include <mach/map.h>
  25 #include <mach/regs-clock.h>
  26 #include <mach/s5p64x0-clock.h>
  27
  28 #include <plat/cpu-freq.h>
  29 #include <plat/clock.h>
  30 #include <plat/cpu.h>
  31 #include <plat/pll.h>
  32 #include <plat/s5p-clock.h>
  33 #include <plat/clock-clksrc.h>
  34 #include <plat/s5p6450.h>
  35
  36 static struct clksrc_clk clk_mout_dpll = {
  37         .clk    = {
  38                 .name           = "mout_dpll",
  39                 .id             = -1,
  40         },
  41         .sources        = &clk_src_dpll,
  42         .reg_src        = { .reg = S5P64X0_CLK_SRC0, .shift = 5, .size = 1 },
  43 };
  44
  45 static u32 epll_div[][5] = {
  46         { 133000000,    27307,  55, 2, 2 },
  47         { 100000000,    43691,  41, 2, 2 },
  48         { 480000000,    0,      80, 2, 0 },
  49 };
  50
  51 static int s5p6450_epll_set_rate(struct clk *clk, unsigned long rate)
  52 {
  53         unsigned int epll_con, epll_con_k;
  54         unsigned int i;
  55
  56         if (clk->rate == rate)  /* Return if nothing changed */
  57                 return 0;
  58
  59         epll_con = __raw_readl(S5P64X0_EPLL_CON);
  60         epll_con_k = __raw_readl(S5P64X0_EPLL_CON_K);
  61
  62         epll_con_k &= ~(PLL90XX_KDIV_MASK);
  63         epll_con &= ~(PLL90XX_MDIV_MASK | PLL90XX_PDIV_MASK | PLL90XX_SDIV_MASK);
  64
  65         for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
  66                  if (epll_div[i][0] == rate) {
  67                         epll_con_k |= (epll_div[i][1] << PLL90XX_KDIV_SHIFT);
  68                         epll_con |= (epll_div[i][2] << PLL90XX_MDIV_SHIFT) |
  69                                     (epll_div[i][3] << PLL90XX_PDIV_SHIFT) |
  70                                     (epll_div[i][4] << PLL90XX_SDIV_SHIFT);
  71                         break;
  72                 }
  73         }
  74
  75         if (i == ARRAY_SIZE(epll_div)) {
  76                 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
  77                 return -EINVAL;
  78         }
  79
  80         __raw_writel(epll_con, S5P64X0_EPLL_CON);
  81         __raw_writel(epll_con_k, S5P64X0_EPLL_CON_K);
  82
  83         printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
  84                         clk->rate, rate);
  85
  86         clk->rate = rate;
  87
  88         return 0;
  89 }
  90
  91 static struct clk_ops s5p6450_epll_ops = {
  92         .get_rate = s5p_epll_get_rate,
  93         .set_rate = s5p6450_epll_set_rate,
  94 };
  95
  96 static struct clksrc_clk clk_dout_epll = {
  97         .clk    = {
  98                 .name           = "dout_epll",
  99                 .id             = -1,
 100                 .parent         = &clk_mout_epll.clk,
 101         },
 102         .reg_div        = { .reg = S5P64X0_CLK_DIV1, .shift = 24, .size = 4 },
 103 };
 104
 105 static struct clksrc_clk clk_mout_hclk_sel = {
 106         .clk    = {
 107                 .name           = "mout_hclk_sel",
 108                 .id             = -1,
 109         },
 110         .sources        = &clkset_hclk_low,
 111         .reg_src        = { .reg = S5P64X0_OTHERS, .shift = 15, .size = 1 },
 112 };
 113
 114 static struct clk *clkset_hclk_list[] = {
 115         &clk_mout_hclk_sel.clk,
 116         &clk_armclk.clk,
 117 };
 118
 119 static struct clksrc_sources clkset_hclk = {
 120         .sources        = clkset_hclk_list,
 121         .nr_sources     = ARRAY_SIZE(clkset_hclk_list),
 122 };
 123
 124 static struct clksrc_clk clk_hclk = {
 125         .clk    = {
 126                 .name           = "clk_hclk",
 127                 .id             = -1,
 128         },
 129         .sources        = &clkset_hclk,
 130         .reg_src        = { .reg = S5P64X0_OTHERS, .shift = 14, .size = 1 },
 131         .reg_div        = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 },
 132 };
 133
 134 static struct clksrc_clk clk_pclk = {
 135         .clk    = {
 136                 .name           = "clk_pclk",
 137                 .id             = -1,
 138                 .parent         = &clk_hclk.clk,
 139         },
 140         .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 },
 141 };
 142 static struct clksrc_clk clk_dout_pwm_ratio0 = {
 143         .clk    = {
 144                 .name           = "clk_dout_pwm_ratio0",
 145                 .id             = -1,
 146                 .parent         = &clk_mout_hclk_sel.clk,
 147         },
 148         .reg_div        = { .reg = S5P64X0_CLK_DIV3, .shift = 16, .size = 4 },
 149 };
 150
 151 static struct clksrc_clk clk_pclk_to_wdt_pwm = {
 152         .clk    = {
 153                 .name           = "clk_pclk_to_wdt_pwm",
 154                 .id             = -1,
 155                 .parent         = &clk_dout_pwm_ratio0.clk,
 156         },
 157         .reg_div        = { .reg = S5P64X0_CLK_DIV3, .shift = 20, .size = 4 },
 158 };
 159
 160 static struct clksrc_clk clk_hclk_low = {
 161         .clk    = {
 162                 .name           = "clk_hclk_low",
 163                 .id             = -1,
 164         },
 165         .sources        = &clkset_hclk_low,
 166         .reg_src        = { .reg = S5P64X0_OTHERS, .shift = 6, .size = 1 },
 167         .reg_div        = { .reg = S5P64X0_CLK_DIV3, .shift = 8, .size = 4 },
 168 };
 169
 170 static struct clksrc_clk clk_pclk_low = {
 171         .clk    = {
 172                 .name           = "clk_pclk_low",
 173                 .id             = -1,
 174                 .parent         = &clk_hclk_low.clk,
 175         },
 176         .reg_div        = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 },
 177 };
 178
 179 /*
 180  * The following clocks will be disabled during clock initialization. It is
 181  * recommended to keep the following clocks disabled until the driver requests
 182  * for enabling the clock.
 183  */
 184 static struct clk init_clocks_disable[] = {
 185         {
 186                 .name           = "usbhost",
 187                 .id             = -1,
 188                 .parent         = &clk_hclk_low.clk,
 189                 .enable         = s5p64x0_hclk0_ctrl,
 190                 .ctrlbit        = (1 << 3),
 191         }, {
 192                 .name           = "pdma",
 193                 .id             = -1,
 194                 .parent         = &clk_hclk_low.clk,
 195                 .enable         = s5p64x0_hclk0_ctrl,
 196                 .ctrlbit        = (1 << 12),
 197         }, {
 198                 .name           = "hsmmc",
 199                 .id             = 0,
 200                 .parent         = &clk_hclk_low.clk,
 201                 .enable         = s5p64x0_hclk0_ctrl,
 202                 .ctrlbit        = (1 << 17),
 203         }, {
 204                 .name           = "hsmmc",
 205                 .id             = 1,
 206                 .parent         = &clk_hclk_low.clk,
 207                 .enable         = s5p64x0_hclk0_ctrl,
 208                 .ctrlbit        = (1 << 18),
 209         }, {
 210                 .name           = "hsmmc",
 211                 .id             = 2,
 212                 .parent         = &clk_hclk_low.clk,
 213                 .enable         = s5p64x0_hclk0_ctrl,
 214                 .ctrlbit        = (1 << 19),
 215         }, {
 216                 .name           = "usbotg",
 217                 .id             = -1,
 218                 .parent         = &clk_hclk_low.clk,
 219                 .enable         = s5p64x0_hclk0_ctrl,
 220                 .ctrlbit        = (1 << 20),
 221         }, {
 222                 .name           = "lcd",
 223                 .id             = -1,
 224                 .parent         = &clk_h,
 225                 .enable         = s5p64x0_hclk1_ctrl,
 226                 .ctrlbit        = (1 << 1),
 227         }, {
 228                 .name           = "watchdog",
 229                 .id             = -1,
 230                 .parent         = &clk_pclk_low.clk,
 231                 .enable         = s5p64x0_pclk_ctrl,
 232                 .ctrlbit        = (1 << 5),
 233         }, {
 234                 .name           = "adc",
 235                 .id             = -1,
 236                 .parent         = &clk_pclk_low.clk,
 237                 .enable         = s5p64x0_pclk_ctrl,
 238                 .ctrlbit        = (1 << 12),
 239         }, {
 240                 .name           = "i2c",
 241                 .id             = 0,
 242                 .parent         = &clk_pclk_low.clk,
 243                 .enable         = s5p64x0_pclk_ctrl,
 244                 .ctrlbit        = (1 << 17),
 245         }, {
 246                 .name           = "spi",
 247                 .id             = 0,
 248                 .parent         = &clk_pclk_low.clk,
 249                 .enable         = s5p64x0_pclk_ctrl,
 250                 .ctrlbit        = (1 << 21),
 251         }, {
 252                 .name           = "spi",
 253                 .id             = 1,
 254                 .parent         = &clk_pclk_low.clk,
 255                 .enable         = s5p64x0_pclk_ctrl,
 256                 .ctrlbit        = (1 << 22),
 257         }, {
 258                 .name           = "iis",
 259                 .id             = -1,
 260                 .parent         = &clk_pclk_low.clk,
 261                 .enable         = s5p64x0_pclk_ctrl,
 262                 .ctrlbit        = (1 << 26),
 263         }, {
 264                 .name           = "i2c",
 265                 .id             = 1,
 266                 .parent         = &clk_pclk_low.clk,
 267                 .enable         = s5p64x0_pclk_ctrl,
 268                 .ctrlbit        = (1 << 27),
 269         }, {
 270                 .name           = "dmc0",
 271                 .id             = -1,
 272                 .parent         = &clk_pclk.clk,
 273                 .enable         = s5p64x0_pclk_ctrl,
 274                 .ctrlbit        = (1 << 30),
 275         }
 276 };
 277
 278 /*
 279  * The following clocks will be enabled during clock initialization.
 280  */
 281 static struct clk init_clocks[] = {
 282         {
 283                 .name           = "intc",
 284                 .id             = -1,
 285                 .parent         = &clk_hclk.clk,
 286                 .enable         = s5p64x0_hclk0_ctrl,
 287                 .ctrlbit        = (1 << 1),
 288         }, {
 289                 .name           = "mem",
 290                 .id             = -1,
 291                 .parent         = &clk_hclk.clk,
 292                 .enable         = s5p64x0_hclk0_ctrl,
 293                 .ctrlbit        = (1 << 21),
 294         }, {
 295                 .name           = "uart",
 296                 .id             = 0,
 297                 .parent         = &clk_pclk_low.clk,
 298                 .enable         = s5p64x0_pclk_ctrl,
 299                 .ctrlbit        = (1 << 1),
 300         }, {
 301                 .name           = "uart",
 302                 .id             = 1,
 303                 .parent         = &clk_pclk_low.clk,
 304                 .enable         = s5p64x0_pclk_ctrl,
 305                 .ctrlbit        = (1 << 2),
 306         }, {
 307                 .name           = "uart",
 308                 .id             = 2,
 309                 .parent         = &clk_pclk_low.clk,
 310                 .enable         = s5p64x0_pclk_ctrl,
 311                 .ctrlbit        = (1 << 3),
 312         }, {
 313                 .name           = "uart",
 314                 .id             = 3,
 315                 .parent         = &clk_pclk_low.clk,
 316                 .enable         = s5p64x0_pclk_ctrl,
 317                 .ctrlbit        = (1 << 4),
 318         }, {
 319                 .name           = "timers",
 320                 .id             = -1,
 321                 .parent         = &clk_pclk_to_wdt_pwm.clk,
 322                 .enable         = s5p64x0_pclk_ctrl,
 323                 .ctrlbit        = (1 << 7),
 324         }, {
 325                 .name           = "gpio",
 326                 .id             = -1,
 327                 .parent         = &clk_pclk_low.clk,
 328                 .enable         = s5p64x0_pclk_ctrl,
 329                 .ctrlbit        = (1 << 18),
 330         },
 331 };
 332
 333 static struct clk *clkset_uart_list[] = {
 334         &clk_dout_epll.clk,
 335         &clk_dout_mpll.clk,
 336 };
 337
 338 static struct clksrc_sources clkset_uart = {
 339         .sources        = clkset_uart_list,
 340         .nr_sources     = ARRAY_SIZE(clkset_uart_list),
 341 };
 342
 343 static struct clk *clkset_mali_list[] = {
 344         &clk_mout_epll.clk,
 345         &clk_mout_apll.clk,
 346         &clk_mout_mpll.clk,
 347 };
 348
 349 static struct clksrc_sources clkset_mali = {
 350         .sources        = clkset_mali_list,
 351         .nr_sources     = ARRAY_SIZE(clkset_mali_list),
 352 };
 353
 354 static struct clk *clkset_group2_list[] = {
 355         &clk_dout_epll.clk,
 356         &clk_dout_mpll.clk,
 357         &clk_ext_xtal_mux,
 358 };
 359
 360 static struct clksrc_sources clkset_group2 = {
 361         .sources        = clkset_group2_list,
 362         .nr_sources     = ARRAY_SIZE(clkset_group2_list),
 363 };
 364
 365 static struct clk *clkset_dispcon_list[] = {
 366         &clk_dout_epll.clk,
 367         &clk_dout_mpll.clk,
 368         &clk_ext_xtal_mux,
 369         &clk_mout_dpll.clk,
 370 };
 371
 372 static struct clksrc_sources clkset_dispcon = {
 373         .sources        = clkset_dispcon_list,
 374         .nr_sources     = ARRAY_SIZE(clkset_dispcon_list),
 375 };
 376
 377 static struct clk *clkset_hsmmc44_list[] = {
 378         &clk_dout_epll.clk,
 379         &clk_dout_mpll.clk,
 380         &clk_ext_xtal_mux,
 381         &s5p_clk_27m,
 382         &clk_48m,
 383 };
 384
 385 static struct clksrc_sources clkset_hsmmc44 = {
 386         .sources        = clkset_hsmmc44_list,
 387         .nr_sources     = ARRAY_SIZE(clkset_hsmmc44_list),
 388 };
 389
 390 static struct clk *clkset_sclk_audio0_list[] = {
 391         [0] = &clk_dout_epll.clk,
 392         [1] = &clk_dout_mpll.clk,
 393         [2] = &clk_ext_xtal_mux,
 394         [3] = NULL,
 395         [4] = NULL,
 396 };
 397
 398 static struct clksrc_sources clkset_sclk_audio0 = {
 399         .sources        = clkset_sclk_audio0_list,
 400         .nr_sources     = ARRAY_SIZE(clkset_sclk_audio0_list),
 401 };
 402
 403 static struct clksrc_clk clk_sclk_audio0 = {
 404         .clk            = {
 405                 .name           = "audio-bus",
 406                 .id             = -1,
 407                 .enable         = s5p64x0_sclk_ctrl,
 408                 .ctrlbit        = (1 << 8),
 409                 .parent         = &clk_dout_epll.clk,
 410         },
 411         .sources        = &clkset_sclk_audio0,
 412         .reg_src        = { .reg = S5P64X0_CLK_SRC1, .shift = 10, .size = 3 },
 413         .reg_div        = { .reg = S5P64X0_CLK_DIV2, .shift = 8, .size = 4 },
 414 };
 415
 416 static struct clksrc_clk clksrcs[] = {
 417         {
 418                 .clk    = {
 419                         .name           = "sclk_mmc",
 420                         .id             = 0,
 421                         .ctrlbit        = (1 << 24),
 422                         .enable         = s5p64x0_sclk_ctrl,
 423                 },
 424                 .sources = &clkset_group2,
 425                 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
 426                 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
 427         }, {
 428                 .clk    = {
 429                         .name           = "sclk_mmc",
 430                         .id             = 1,
 431                         .ctrlbit        = (1 << 25),
 432                         .enable         = s5p64x0_sclk_ctrl,
 433                 },
 434                 .sources = &clkset_group2,
 435                 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
 436                 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
 437         }, {
 438                 .clk    = {
 439                         .name           = "sclk_mmc",
 440                         .id             = 2,
 441                         .ctrlbit        = (1 << 26),
 442                         .enable         = s5p64x0_sclk_ctrl,
 443                 },
 444                 .sources = &clkset_group2,
 445                 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
 446                 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
 447         }, {
 448                 .clk    = {
 449                         .name           = "uclk1",
 450                         .id             = -1,
 451                         .ctrlbit        = (1 << 5),
 452                         .enable         = s5p64x0_sclk_ctrl,
 453                 },
 454                 .sources = &clkset_uart,
 455                 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
 456                 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
 457         }, {
 458                 .clk    = {
 459                         .name           = "sclk_spi",
 460                         .id             = 0,
 461                         .ctrlbit        = (1 << 20),
 462                         .enable         = s5p64x0_sclk_ctrl,
 463                 },
 464                 .sources = &clkset_group2,
 465                 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
 466                 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
 467         }, {
 468                 .clk    = {
 469                         .name           = "sclk_spi",
 470                         .id             = 1,
 471                         .ctrlbit        = (1 << 21),
 472                         .enable         = s5p64x0_sclk_ctrl,
 473                 },
 474                 .sources = &clkset_group2,
 475                 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
 476                 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
 477         }, {
 478                 .clk    = {
 479                         .name           = "sclk_fimc",
 480                         .id             = -1,
 481                         .ctrlbit        = (1 << 10),
 482                         .enable         = s5p64x0_sclk_ctrl,
 483                 },
 484                 .sources = &clkset_group2,
 485                 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 26, .size = 2 },
 486                 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 12, .size = 4 },
 487         }, {
 488                 .clk    = {
 489                         .name           = "aclk_mali",
 490                         .id             = -1,
 491                         .ctrlbit        = (1 << 2),
 492                         .enable         = s5p64x0_sclk1_ctrl,
 493                 },
 494                 .sources = &clkset_mali,
 495                 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 8, .size = 2 },
 496                 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 4, .size = 4 },
 497         }, {
 498                 .clk    = {
 499                         .name           = "sclk_2d",
 500                         .id             = -1,
 501                         .ctrlbit        = (1 << 12),
 502                         .enable         = s5p64x0_sclk_ctrl,
 503                 },
 504                 .sources = &clkset_mali,
 505                 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 30, .size = 2 },
 506                 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 20, .size = 4 },
 507         }, {
 508                 .clk    = {
 509                         .name           = "sclk_usi",
 510                         .id             = -1,
 511                         .ctrlbit        = (1 << 7),
 512                         .enable         = s5p64x0_sclk_ctrl,
 513                 },
 514                 .sources = &clkset_group2,
 515                 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 10, .size = 2 },
 516                 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 16, .size = 4 },
 517         }, {
 518                 .clk    = {
 519                         .name           = "sclk_camif",
 520                         .id             = -1,
 521                         .ctrlbit        = (1 << 6),
 522                         .enable         = s5p64x0_sclk_ctrl,
 523                 },
 524                 .sources = &clkset_group2,
 525                 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 28, .size = 2 },
 526                 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 20, .size = 4 },
 527         }, {
 528                 .clk    = {
 529                         .name           = "sclk_dispcon",
 530                         .id             = -1,
 531                         .ctrlbit        = (1 << 1),
 532                         .enable         = s5p64x0_sclk1_ctrl,
 533                 },
 534                 .sources = &clkset_dispcon,
 535                 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 4, .size = 2 },
 536                 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 0, .size = 4 },
 537         }, {
 538                 .clk    = {
 539                         .name           = "sclk_hsmmc44",
 540                         .id             = -1,
 541                         .ctrlbit        = (1 << 30),
 542                         .enable         = s5p64x0_sclk_ctrl,
 543                 },
 544                 .sources = &clkset_hsmmc44,
 545                 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 6, .size = 3 },
 546                 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 28, .size = 4 },
 547         },
 548 };
 549
 550 /* Clock initialization code */
 551 static struct clksrc_clk *sysclks[] = {
 552         &clk_mout_apll,
 553         &clk_mout_epll,
 554         &clk_dout_epll,
 555         &clk_mout_mpll,
 556         &clk_dout_mpll,
 557         &clk_armclk,
 558         &clk_mout_hclk_sel,
 559         &clk_dout_pwm_ratio0,
 560         &clk_pclk_to_wdt_pwm,
 561         &clk_hclk,
 562         &clk_pclk,
 563         &clk_hclk_low,
 564         &clk_pclk_low,
 565         &clk_sclk_audio0,
 566 };
 567
 568 void __init_or_cpufreq s5p6450_setup_clocks(void)
 569 {
 570         struct clk *xtal_clk;
 571
 572         unsigned long xtal;
 573         unsigned long fclk;
 574         unsigned long hclk;
 575         unsigned long hclk_low;
 576         unsigned long pclk;
 577         unsigned long pclk_low;
 578
 579         unsigned long apll;
 580         unsigned long mpll;
 581         unsigned long epll;
 582         unsigned long dpll;
 583         unsigned int ptr;
 584
 585         /* Set S5P6450 functions for clk_fout_epll */
 586
 587         clk_fout_epll.enable = s5p_epll_enable;
 588         clk_fout_epll.ops = &s5p6450_epll_ops;
 589
 590         clk_48m.enable = s5p64x0_clk48m_ctrl;
 591
 592         xtal_clk = clk_get(NULL, "ext_xtal");
 593         BUG_ON(IS_ERR(xtal_clk));
 594
 595         xtal = clk_get_rate(xtal_clk);
 596         clk_put(xtal_clk);
 597
 598         apll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_APLL_CON), pll_4502);
 599         mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_MPLL_CON), pll_4502);
 600         epll = s5p_get_pll90xx(xtal, __raw_readl(S5P64X0_EPLL_CON),
 601                                 __raw_readl(S5P64X0_EPLL_CON_K));
 602         dpll = s5p_get_pll46xx(xtal, __raw_readl(S5P6450_DPLL_CON),
 603                                 __raw_readl(S5P6450_DPLL_CON_K), pll_4650c);
 604
 605         clk_fout_apll.rate = apll;
 606         clk_fout_mpll.rate = mpll;
 607         clk_fout_epll.rate = epll;
 608         clk_fout_dpll.rate = dpll;
 609
 610         printk(KERN_INFO "S5P6450: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
 611                         " E=%ld.%ldMHz, D=%ld.%ldMHz\n",
 612                         print_mhz(apll), print_mhz(mpll), print_mhz(epll),
 613                         print_mhz(dpll));
 614
 615         fclk = clk_get_rate(&clk_armclk.clk);
 616         hclk = clk_get_rate(&clk_hclk.clk);
 617         pclk = clk_get_rate(&clk_pclk.clk);
 618         hclk_low = clk_get_rate(&clk_hclk_low.clk);
 619         pclk_low = clk_get_rate(&clk_pclk_low.clk);
 620
 621         printk(KERN_INFO "S5P6450: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
 622                         " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
 623                         print_mhz(hclk), print_mhz(hclk_low),
 624                         print_mhz(pclk), print_mhz(pclk_low));
 625
 626         clk_f.rate = fclk;
 627         clk_h.rate = hclk;
 628         clk_p.rate = pclk;
 629
 630         for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
 631                 s3c_set_clksrc(&clksrcs[ptr], true);
 632 }
 633
 634 void __init s5p6450_register_clocks(void)
 635 {
 636         struct clk *clkp;
 637         int ret;
 638         int ptr;
 639
 640         for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
 641                 s3c_register_clksrc(sysclks[ptr], 1);
 642
 643         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
 644         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
 645
 646         clkp = init_clocks_disable;
 647         for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
 648
 649                 ret = s3c24xx_register_clock(clkp);
 650                 if (ret < 0) {
 651                         printk(KERN_ERR "Failed to register clock %s (%d)\n",
 652                                clkp->name, ret);
 653                 }
 654                 (clkp->enable)(clkp, 0);
 655         }
 656
 657         s3c_pwmclk_init();
 658 }