arch/arm/mach-s5p64x0/clock-s5p6440.c

   1 /* linux/arch/arm/mach-s5p64x0/clock-s5p6440.c
   2  *
   3  * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * S5P6440 - Clock support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #include <linux/init.h>
  14 #include <linux/module.h>
  15 #include <linux/kernel.h>
  16 #include <linux/list.h>
  17 #include <linux/errno.h>
  18 #include <linux/err.h>
  19 #include <linux/clk.h>
  20 #include <linux/sysdev.h>
  21 #include <linux/io.h>
  22
  23 #include <mach/hardware.h>
  24 #include <mach/map.h>
  25 #include <mach/regs-clock.h>
  26 #include <mach/s5p64x0-clock.h>
  27
  28 #include <plat/cpu-freq.h>
  29 #include <plat/clock.h>
  30 #include <plat/cpu.h>
  31 #include <plat/pll.h>
  32 #include <plat/s5p-clock.h>
  33 #include <plat/clock-clksrc.h>
  34 #include <plat/s5p6440.h>
  35
  36 static u32 epll_div[][5] = {
  37         { 36000000,     0,      48, 1, 4 },
  38         { 48000000,     0,      32, 1, 3 },
  39         { 60000000,     0,      40, 1, 3 },
  40         { 72000000,     0,      48, 1, 3 },
  41         { 84000000,     0,      28, 1, 2 },
  42         { 96000000,     0,      32, 1, 2 },
  43         { 32768000,     45264,  43, 1, 4 },
  44         { 45158000,     6903,   30, 1, 3 },
  45         { 49152000,     50332,  32, 1, 3 },
  46         { 67738000,     10398,  45, 1, 3 },
  47         { 73728000,     9961,   49, 1, 3 }
  48 };
  49
  50 static int s5p6440_epll_set_rate(struct clk *clk, unsigned long rate)
  51 {
  52         unsigned int epll_con, epll_con_k;
  53         unsigned int i;
  54
  55         if (clk->rate == rate)  /* Return if nothing changed */
  56                 return 0;
  57
  58         epll_con = __raw_readl(S5P64X0_EPLL_CON);
  59         epll_con_k = __raw_readl(S5P64X0_EPLL_CON_K);
  60
  61         epll_con_k &= ~(PLL90XX_KDIV_MASK);
  62         epll_con &= ~(PLL90XX_MDIV_MASK | PLL90XX_PDIV_MASK | PLL90XX_SDIV_MASK);
  63
  64         for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
  65                  if (epll_div[i][0] == rate) {
  66                         epll_con_k |= (epll_div[i][1] << PLL90XX_KDIV_SHIFT);
  67                         epll_con |= (epll_div[i][2] << PLL90XX_MDIV_SHIFT) |
  68                                     (epll_div[i][3] << PLL90XX_PDIV_SHIFT) |
  69                                     (epll_div[i][4] << PLL90XX_SDIV_SHIFT);
  70                         break;
  71                 }
  72         }
  73
  74         if (i == ARRAY_SIZE(epll_div)) {
  75                 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
  76                 return -EINVAL;
  77         }
  78
  79         __raw_writel(epll_con, S5P64X0_EPLL_CON);
  80         __raw_writel(epll_con_k, S5P64X0_EPLL_CON_K);
  81
  82         clk->rate = rate;
  83
  84         return 0;
  85 }
  86
  87 static struct clk_ops s5p6440_epll_ops = {
  88         .get_rate = s5p64x0_epll_get_rate,
  89         .set_rate = s5p6440_epll_set_rate,
  90 };
  91
  92 static struct clksrc_clk clk_hclk = {
  93         .clk    = {
  94                 .name           = "clk_hclk",
  95                 .id             = -1,
  96                 .parent         = &clk_armclk.clk,
  97         },
  98         .reg_div        = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 },
  99 };
 100
 101 static struct clksrc_clk clk_pclk = {
 102         .clk    = {
 103                 .name           = "clk_pclk",
 104                 .id             = -1,
 105                 .parent         = &clk_hclk.clk,
 106         },
 107         .reg_div        = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 },
 108 };
 109 static struct clksrc_clk clk_hclk_low = {
 110         .clk    = {
 111                 .name           = "clk_hclk_low",
 112                 .id             = -1,
 113         },
 114         .sources        = &clkset_hclk_low,
 115         .reg_src        = { .reg = S5P64X0_SYS_OTHERS, .shift = 6, .size = 1 },
 116         .reg_div        = { .reg = S5P64X0_CLK_DIV3, .shift = 8, .size = 4 },
 117 };
 118
 119 static struct clksrc_clk clk_pclk_low = {
 120         .clk    = {
 121                 .name           = "clk_pclk_low",
 122                 .id             = -1,
 123                 .parent         = &clk_hclk_low.clk,
 124         },
 125         .reg_div        = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 },
 126 };
 127
 128 /*
 129  * The following clocks will be disabled during clock initialization. It is
 130  * recommended to keep the following clocks disabled until the driver requests
 131  * for enabling the clock.
 132  */
 133 static struct clk init_clocks_disable[] = {
 134         {
 135                 .name           = "nand",
 136                 .id             = -1,
 137                 .parent         = &clk_hclk.clk,
 138                 .enable         = s5p64x0_mem_ctrl,
 139                 .ctrlbit        = (1 << 2),
 140         }, {
 141                 .name           = "post",
 142                 .id             = -1,
 143                 .parent         = &clk_hclk_low.clk,
 144                 .enable         = s5p64x0_hclk0_ctrl,
 145                 .ctrlbit        = (1 << 5)
 146         }, {
 147                 .name           = "2d",
 148                 .id             = -1,
 149                 .parent         = &clk_hclk.clk,
 150                 .enable         = s5p64x0_hclk0_ctrl,
 151                 .ctrlbit        = (1 << 8),
 152         }, {
 153                 .name           = "hsmmc",
 154                 .id             = 0,
 155                 .parent         = &clk_hclk_low.clk,
 156                 .enable         = s5p64x0_hclk0_ctrl,
 157                 .ctrlbit        = (1 << 17),
 158         }, {
 159                 .name           = "hsmmc",
 160                 .id             = 1,
 161                 .parent         = &clk_hclk_low.clk,
 162                 .enable         = s5p64x0_hclk0_ctrl,
 163                 .ctrlbit        = (1 << 18),
 164         }, {
 165                 .name           = "hsmmc",
 166                 .id             = 2,
 167                 .parent         = &clk_hclk_low.clk,
 168                 .enable         = s5p64x0_hclk0_ctrl,
 169                 .ctrlbit        = (1 << 19),
 170         }, {
 171                 .name           = "otg",
 172                 .id             = -1,
 173                 .parent         = &clk_hclk_low.clk,
 174                 .enable         = s5p64x0_hclk0_ctrl,
 175                 .ctrlbit        = (1 << 20)
 176         }, {
 177                 .name           = "irom",
 178                 .id             = -1,
 179                 .parent         = &clk_hclk.clk,
 180                 .enable         = s5p64x0_hclk0_ctrl,
 181                 .ctrlbit        = (1 << 25),
 182         }, {
 183                 .name           = "lcd",
 184                 .id             = -1,
 185                 .parent         = &clk_hclk_low.clk,
 186                 .enable         = s5p64x0_hclk1_ctrl,
 187                 .ctrlbit        = (1 << 1),
 188         }, {
 189                 .name           = "hclk_fimgvg",
 190                 .id             = -1,
 191                 .parent         = &clk_hclk.clk,
 192                 .enable         = s5p64x0_hclk1_ctrl,
 193                 .ctrlbit        = (1 << 2),
 194         }, {
 195                 .name           = "tsi",
 196                 .id             = -1,
 197                 .parent         = &clk_hclk_low.clk,
 198                 .enable         = s5p64x0_hclk1_ctrl,
 199                 .ctrlbit        = (1 << 0),
 200         }, {
 201                 .name           = "watchdog",
 202                 .id             = -1,
 203                 .parent         = &clk_pclk_low.clk,
 204                 .enable         = s5p64x0_pclk_ctrl,
 205                 .ctrlbit        = (1 << 5),
 206         }, {
 207                 .name           = "rtc",
 208                 .id             = -1,
 209                 .parent         = &clk_pclk_low.clk,
 210                 .enable         = s5p64x0_pclk_ctrl,
 211                 .ctrlbit        = (1 << 6),
 212         }, {
 213                 .name           = "timers",
 214                 .id             = -1,
 215                 .parent         = &clk_pclk_low.clk,
 216                 .enable         = s5p64x0_pclk_ctrl,
 217                 .ctrlbit        = (1 << 7),
 218         }, {
 219                 .name           = "pcm",
 220                 .id             = -1,
 221                 .parent         = &clk_pclk_low.clk,
 222                 .enable         = s5p64x0_pclk_ctrl,
 223                 .ctrlbit        = (1 << 8),
 224         }, {
 225                 .name           = "adc",
 226                 .id             = -1,
 227                 .parent         = &clk_pclk_low.clk,
 228                 .enable         = s5p64x0_pclk_ctrl,
 229                 .ctrlbit        = (1 << 12),
 230         }, {
 231                 .name           = "i2c",
 232                 .id             = -1,
 233                 .parent         = &clk_pclk_low.clk,
 234                 .enable         = s5p64x0_pclk_ctrl,
 235                 .ctrlbit        = (1 << 17),
 236         }, {
 237                 .name           = "spi",
 238                 .id             = 0,
 239                 .parent         = &clk_pclk_low.clk,
 240                 .enable         = s5p64x0_pclk_ctrl,
 241                 .ctrlbit        = (1 << 21),
 242         }, {
 243                 .name           = "spi",
 244                 .id             = 1,
 245                 .parent         = &clk_pclk_low.clk,
 246                 .enable         = s5p64x0_pclk_ctrl,
 247                 .ctrlbit        = (1 << 22),
 248         }, {
 249                 .name           = "gps",
 250                 .id             = -1,
 251                 .parent         = &clk_pclk_low.clk,
 252                 .enable         = s5p64x0_pclk_ctrl,
 253                 .ctrlbit        = (1 << 25),
 254         }, {
 255                 .name           = "i2s_v40",
 256                 .id             = 0,
 257                 .parent         = &clk_pclk_low.clk,
 258                 .enable         = s5p64x0_pclk_ctrl,
 259                 .ctrlbit        = (1 << 26),
 260         }, {
 261                 .name           = "dsim",
 262                 .id             = -1,
 263                 .parent         = &clk_pclk_low.clk,
 264                 .enable         = s5p64x0_pclk_ctrl,
 265                 .ctrlbit        = (1 << 28),
 266         }, {
 267                 .name           = "etm",
 268                 .id             = -1,
 269                 .parent         = &clk_pclk.clk,
 270                 .enable         = s5p64x0_pclk_ctrl,
 271                 .ctrlbit        = (1 << 29),
 272         }, {
 273                 .name           = "dmc0",
 274                 .id             = -1,
 275                 .parent         = &clk_pclk.clk,
 276                 .enable         = s5p64x0_pclk_ctrl,
 277                 .ctrlbit        = (1 << 30),
 278         }, {
 279                 .name           = "pclk_fimgvg",
 280                 .id             = -1,
 281                 .parent         = &clk_pclk.clk,
 282                 .enable         = s5p64x0_pclk_ctrl,
 283                 .ctrlbit        = (1 << 31),
 284         }, {
 285                 .name           = "sclk_spi_48",
 286                 .id             = 0,
 287                 .parent         = &clk_48m,
 288                 .enable         = s5p64x0_sclk_ctrl,
 289                 .ctrlbit        = (1 << 22),
 290         }, {
 291                 .name           = "sclk_spi_48",
 292                 .id             = 1,
 293                 .parent         = &clk_48m,
 294                 .enable         = s5p64x0_sclk_ctrl,
 295                 .ctrlbit        = (1 << 23),
 296         }, {
 297                 .name           = "mmc_48m",
 298                 .id             = 0,
 299                 .parent         = &clk_48m,
 300                 .enable         = s5p64x0_sclk_ctrl,
 301                 .ctrlbit        = (1 << 27),
 302         }, {
 303                 .name           = "mmc_48m",
 304                 .id             = 1,
 305                 .parent         = &clk_48m,
 306                 .enable         = s5p64x0_sclk_ctrl,
 307                 .ctrlbit        = (1 << 28),
 308         }, {
 309                 .name           = "mmc_48m",
 310                 .id             = 2,
 311                 .parent         = &clk_48m,
 312                 .enable         = s5p64x0_sclk_ctrl,
 313                 .ctrlbit        = (1 << 29),
 314         },
 315 };
 316
 317 /*
 318  * The following clocks will be enabled during clock initialization.
 319  */
 320 static struct clk init_clocks[] = {
 321         {
 322                 .name           = "intc",
 323                 .id             = -1,
 324                 .parent         = &clk_hclk.clk,
 325                 .enable         = s5p64x0_hclk0_ctrl,
 326                 .ctrlbit        = (1 << 1),
 327         }, {
 328                 .name           = "mem",
 329                 .id             = -1,
 330                 .parent         = &clk_hclk.clk,
 331                 .enable         = s5p64x0_hclk0_ctrl,
 332                 .ctrlbit        = (1 << 21),
 333         }, {
 334                 .name           = "dma",
 335                 .id             = -1,
 336                 .parent         = &clk_hclk_low.clk,
 337                 .enable         = s5p64x0_hclk0_ctrl,
 338                 .ctrlbit        = (1 << 12),
 339         }, {
 340                 .name           = "uart",
 341                 .id             = 0,
 342                 .parent         = &clk_pclk_low.clk,
 343                 .enable         = s5p64x0_pclk_ctrl,
 344                 .ctrlbit        = (1 << 1),
 345         }, {
 346                 .name           = "uart",
 347                 .id             = 1,
 348                 .parent         = &clk_pclk_low.clk,
 349                 .enable         = s5p64x0_pclk_ctrl,
 350                 .ctrlbit        = (1 << 2),
 351         }, {
 352                 .name           = "uart",
 353                 .id             = 2,
 354                 .parent         = &clk_pclk_low.clk,
 355                 .enable         = s5p64x0_pclk_ctrl,
 356                 .ctrlbit        = (1 << 3),
 357         }, {
 358                 .name           = "uart",
 359                 .id             = 3,
 360                 .parent         = &clk_pclk_low.clk,
 361                 .enable         = s5p64x0_pclk_ctrl,
 362                 .ctrlbit        = (1 << 4),
 363         }, {
 364                 .name           = "gpio",
 365                 .id             = -1,
 366                 .parent         = &clk_pclk_low.clk,
 367                 .enable         = s5p64x0_pclk_ctrl,
 368                 .ctrlbit        = (1 << 18),
 369         },
 370 };
 371
 372 static struct clk clk_iis_cd_v40 = {
 373         .name           = "iis_cdclk_v40",
 374         .id             = -1,
 375 };
 376
 377 static struct clk clk_pcm_cd = {
 378         .name           = "pcm_cdclk",
 379         .id             = -1,
 380 };
 381
 382 static struct clk *clkset_group1_list[] = {
 383         &clk_mout_epll.clk,
 384         &clk_dout_mpll.clk,
 385         &clk_fin_epll,
 386 };
 387
 388 static struct clksrc_sources clkset_group1 = {
 389         .sources        = clkset_group1_list,
 390         .nr_sources     = ARRAY_SIZE(clkset_group1_list),
 391 };
 392
 393 static struct clk *clkset_uart_list[] = {
 394         &clk_mout_epll.clk,
 395         &clk_dout_mpll.clk,
 396 };
 397
 398 static struct clksrc_sources clkset_uart = {
 399         .sources        = clkset_uart_list,
 400         .nr_sources     = ARRAY_SIZE(clkset_uart_list),
 401 };
 402
 403 static struct clk *clkset_audio_list[] = {
 404         &clk_mout_epll.clk,
 405         &clk_dout_mpll.clk,
 406         &clk_fin_epll,
 407         &clk_iis_cd_v40,
 408         &clk_pcm_cd,
 409 };
 410
 411 static struct clksrc_sources clkset_audio = {
 412         .sources        = clkset_audio_list,
 413         .nr_sources     = ARRAY_SIZE(clkset_audio_list),
 414 };
 415
 416 static struct clksrc_clk clksrcs[] = {
 417         {
 418                 .clk    = {
 419                         .name           = "mmc_bus",
 420                         .id             = 0,
 421                         .ctrlbit        = (1 << 24),
 422                         .enable         = s5p64x0_sclk_ctrl,
 423                 },
 424                 .sources = &clkset_group1,
 425                 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
 426                 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
 427         }, {
 428                 .clk    = {
 429                         .name           = "mmc_bus",
 430                         .id             = 1,
 431                         .ctrlbit        = (1 << 25),
 432                         .enable         = s5p64x0_sclk_ctrl,
 433                 },
 434                 .sources = &clkset_group1,
 435                 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
 436                 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
 437         }, {
 438                 .clk    = {
 439                         .name           = "mmc_bus",
 440                         .id             = 2,
 441                         .ctrlbit        = (1 << 26),
 442                         .enable         = s5p64x0_sclk_ctrl,
 443                 },
 444                 .sources = &clkset_group1,
 445                 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
 446                 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
 447         }, {
 448                 .clk    = {
 449                         .name           = "uclk1",
 450                         .id             = -1,
 451                         .ctrlbit        = (1 << 5),
 452                         .enable         = s5p64x0_sclk_ctrl,
 453                 },
 454                 .sources = &clkset_uart,
 455                 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
 456                 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
 457         }, {
 458                 .clk    = {
 459                         .name           = "sclk_spi",
 460                         .id             = 0,
 461                         .ctrlbit        = (1 << 20),
 462                         .enable         = s5p64x0_sclk_ctrl,
 463                 },
 464                 .sources = &clkset_group1,
 465                 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
 466                 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
 467         }, {
 468                 .clk    = {
 469                         .name           = "sclk_spi",
 470                         .id             = 1,
 471                         .ctrlbit        = (1 << 21),
 472                         .enable         = s5p64x0_sclk_ctrl,
 473                 },
 474                 .sources = &clkset_group1,
 475                 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
 476                 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
 477         }, {
 478                 .clk    = {
 479                         .name           = "sclk_post",
 480                         .id             = -1,
 481                         .ctrlbit        = (1 << 10),
 482                         .enable         = s5p64x0_sclk_ctrl,
 483                 },
 484                 .sources = &clkset_group1,
 485                 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 26, .size = 2 },
 486                 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 12, .size = 4 },
 487         }, {
 488                 .clk    = {
 489                         .name           = "sclk_dispcon",
 490                         .id             = -1,
 491                         .ctrlbit        = (1 << 1),
 492                         .enable         = s5p64x0_sclk1_ctrl,
 493                 },
 494                 .sources = &clkset_group1,
 495                 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 4, .size = 2 },
 496                 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 0, .size = 4 },
 497         }, {
 498                 .clk    = {
 499                         .name           = "sclk_fimgvg",
 500                         .id             = -1,
 501                         .ctrlbit        = (1 << 2),
 502                         .enable         = s5p64x0_sclk1_ctrl,
 503                 },
 504                 .sources = &clkset_group1,
 505                 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 8, .size = 2 },
 506                 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 4, .size = 4 },
 507         }, {
 508                 .clk    = {
 509                         .name           = "sclk_audio2",
 510                         .id             = -1,
 511                         .ctrlbit        = (1 << 11),
 512                         .enable         = s5p64x0_sclk_ctrl,
 513                 },
 514                 .sources = &clkset_audio,
 515                 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 0, .size = 3 },
 516                 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 24, .size = 4 },
 517         },
 518 };
 519
 520 /* Clock initialization code */
 521 static struct clksrc_clk *sysclks[] = {
 522         &clk_mout_apll,
 523         &clk_mout_epll,
 524         &clk_mout_mpll,
 525         &clk_dout_mpll,
 526         &clk_armclk,
 527         &clk_hclk,
 528         &clk_pclk,
 529         &clk_hclk_low,
 530         &clk_pclk_low,
 531 };
 532
 533 void __init_or_cpufreq s5p6440_setup_clocks(void)
 534 {
 535         struct clk *xtal_clk;
 536
 537         unsigned long xtal;
 538         unsigned long fclk;
 539         unsigned long hclk;
 540         unsigned long hclk_low;
 541         unsigned long pclk;
 542         unsigned long pclk_low;
 543
 544         unsigned long apll;
 545         unsigned long mpll;
 546         unsigned long epll;
 547         unsigned int ptr;
 548
 549         /* Set S5P6440 functions for clk_fout_epll */
 550
 551         clk_fout_epll.enable = s5p64x0_epll_enable;
 552         clk_fout_epll.ops = &s5p6440_epll_ops;
 553
 554         clk_48m.enable = s5p64x0_clk48m_ctrl;
 555
 556         xtal_clk = clk_get(NULL, "ext_xtal");
 557         BUG_ON(IS_ERR(xtal_clk));
 558
 559         xtal = clk_get_rate(xtal_clk);
 560         clk_put(xtal_clk);
 561
 562         apll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_APLL_CON), pll_4502);
 563         mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_MPLL_CON), pll_4502);
 564         epll = s5p_get_pll90xx(xtal, __raw_readl(S5P64X0_EPLL_CON),
 565                                 __raw_readl(S5P64X0_EPLL_CON_K));
 566
 567         clk_fout_apll.rate = apll;
 568         clk_fout_mpll.rate = mpll;
 569         clk_fout_epll.rate = epll;
 570
 571         printk(KERN_INFO "S5P6440: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
 572                         " E=%ld.%ldMHz\n",
 573                         print_mhz(apll), print_mhz(mpll), print_mhz(epll));
 574
 575         fclk = clk_get_rate(&clk_armclk.clk);
 576         hclk = clk_get_rate(&clk_hclk.clk);
 577         pclk = clk_get_rate(&clk_pclk.clk);
 578         hclk_low = clk_get_rate(&clk_hclk_low.clk);
 579         pclk_low = clk_get_rate(&clk_pclk_low.clk);
 580
 581         printk(KERN_INFO "S5P6440: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
 582                         " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
 583                         print_mhz(hclk), print_mhz(hclk_low),
 584                         print_mhz(pclk), print_mhz(pclk_low));
 585
 586         clk_f.rate = fclk;
 587         clk_h.rate = hclk;
 588         clk_p.rate = pclk;
 589
 590         for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
 591                 s3c_set_clksrc(&clksrcs[ptr], true);
 592 }
 593
 594 static struct clk *clks[] __initdata = {
 595         &clk_ext,
 596         &clk_iis_cd_v40,
 597         &clk_pcm_cd,
 598 };
 599
 600 void __init s5p6440_register_clocks(void)
 601 {
 602         struct clk *clkp;
 603         int ret;
 604         int ptr;
 605
 606         s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
 607
 608         for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
 609                 s3c_register_clksrc(sysclks[ptr], 1);
 610
 611         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
 612         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
 613
 614         clkp = init_clocks_disable;
 615         for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
 616
 617                 ret = s3c24xx_register_clock(clkp);
 618                 if (ret < 0) {
 619                         printk(KERN_ERR "Failed to register clock %s (%d)\n",
 620                                clkp->name, ret);
 621                 }
 622                 (clkp->enable)(clkp, 0);
 623         }
 624
 625         s3c_pwmclk_init();
 626 }