arch/arm/mach-s5p64x0/clock-s5p6440.c

   1 /* linux/arch/arm/mach-s5p64x0/clock-s5p6440.c
   2  *
   3  * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * S5P6440 - Clock support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #include <linux/init.h>
  14 #include <linux/module.h>
  15 #include <linux/kernel.h>
  16 #include <linux/list.h>
  17 #include <linux/errno.h>
  18 #include <linux/err.h>
  19 #include <linux/clk.h>
  20 #include <linux/sysdev.h>
  21 #include <linux/io.h>
  22
  23 #include <mach/hardware.h>
  24 #include <mach/map.h>
  25 #include <mach/regs-clock.h>
  26 #include <mach/s5p64x0-clock.h>
  27
  28 #include <plat/cpu-freq.h>
  29 #include <plat/clock.h>
  30 #include <plat/cpu.h>
  31 #include <plat/pll.h>
  32 #include <plat/s5p-clock.h>
  33 #include <plat/clock-clksrc.h>
  34 #include <plat/s5p6440.h>
  35
  36 static u32 epll_div[][5] = {
  37         { 36000000,     0,      48, 1, 4 },
  38         { 48000000,     0,      32, 1, 3 },
  39         { 60000000,     0,      40, 1, 3 },
  40         { 72000000,     0,      48, 1, 3 },
  41         { 84000000,     0,      28, 1, 2 },
  42         { 96000000,     0,      32, 1, 2 },
  43         { 32768000,     45264,  43, 1, 4 },
  44         { 45158000,     6903,   30, 1, 3 },
  45         { 49152000,     50332,  32, 1, 3 },
  46         { 67738000,     10398,  45, 1, 3 },
  47         { 73728000,     9961,   49, 1, 3 }
  48 };
  49
  50 static int s5p6440_epll_set_rate(struct clk *clk, unsigned long rate)
  51 {
  52         unsigned int epll_con, epll_con_k;
  53         unsigned int i;
  54
  55         if (clk->rate == rate)  /* Return if nothing changed */
  56                 return 0;
  57
  58         epll_con = __raw_readl(S5P64X0_EPLL_CON);
  59         epll_con_k = __raw_readl(S5P64X0_EPLL_CON_K);
  60
  61         epll_con_k &= ~(PLL90XX_KDIV_MASK);
  62         epll_con &= ~(PLL90XX_MDIV_MASK | PLL90XX_PDIV_MASK | PLL90XX_SDIV_MASK);
  63
  64         for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
  65                  if (epll_div[i][0] == rate) {
  66                         epll_con_k |= (epll_div[i][1] << PLL90XX_KDIV_SHIFT);
  67                         epll_con |= (epll_div[i][2] << PLL90XX_MDIV_SHIFT) |
  68                                     (epll_div[i][3] << PLL90XX_PDIV_SHIFT) |
  69                                     (epll_div[i][4] << PLL90XX_SDIV_SHIFT);
  70                         break;
  71                 }
  72         }
  73
  74         if (i == ARRAY_SIZE(epll_div)) {
  75                 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
  76                 return -EINVAL;
  77         }
  78
  79         __raw_writel(epll_con, S5P64X0_EPLL_CON);
  80         __raw_writel(epll_con_k, S5P64X0_EPLL_CON_K);
  81
  82         printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
  83                         clk->rate, rate);
  84
  85         clk->rate = rate;
  86
  87         return 0;
  88 }
  89
  90 static struct clk_ops s5p6440_epll_ops = {
  91         .get_rate = s5p_epll_get_rate,
  92         .set_rate = s5p6440_epll_set_rate,
  93 };
  94
  95 static struct clksrc_clk clk_hclk = {
  96         .clk    = {
  97                 .name           = "clk_hclk",
  98                 .id             = -1,
  99                 .parent         = &clk_armclk.clk,
 100         },
 101         .reg_div        = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 },
 102 };
 103
 104 static struct clksrc_clk clk_pclk = {
 105         .clk    = {
 106                 .name           = "clk_pclk",
 107                 .id             = -1,
 108                 .parent         = &clk_hclk.clk,
 109         },
 110         .reg_div        = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 },
 111 };
 112 static struct clksrc_clk clk_hclk_low = {
 113         .clk    = {
 114                 .name           = "clk_hclk_low",
 115                 .id             = -1,
 116         },
 117         .sources        = &clkset_hclk_low,
 118         .reg_src        = { .reg = S5P64X0_SYS_OTHERS, .shift = 6, .size = 1 },
 119         .reg_div        = { .reg = S5P64X0_CLK_DIV3, .shift = 8, .size = 4 },
 120 };
 121
 122 static struct clksrc_clk clk_pclk_low = {
 123         .clk    = {
 124                 .name           = "clk_pclk_low",
 125                 .id             = -1,
 126                 .parent         = &clk_hclk_low.clk,
 127         },
 128         .reg_div        = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 },
 129 };
 130
 131 /*
 132  * The following clocks will be disabled during clock initialization. It is
 133  * recommended to keep the following clocks disabled until the driver requests
 134  * for enabling the clock.
 135  */
 136 static struct clk init_clocks_off[] = {
 137         {
 138                 .name           = "nand",
 139                 .id             = -1,
 140                 .parent         = &clk_hclk.clk,
 141                 .enable         = s5p64x0_mem_ctrl,
 142                 .ctrlbit        = (1 << 2),
 143         }, {
 144                 .name           = "post",
 145                 .id             = -1,
 146                 .parent         = &clk_hclk_low.clk,
 147                 .enable         = s5p64x0_hclk0_ctrl,
 148                 .ctrlbit        = (1 << 5)
 149         }, {
 150                 .name           = "2d",
 151                 .id             = -1,
 152                 .parent         = &clk_hclk.clk,
 153                 .enable         = s5p64x0_hclk0_ctrl,
 154                 .ctrlbit        = (1 << 8),
 155         }, {
 156                 .name           = "pdma",
 157                 .id             = -1,
 158                 .parent         = &clk_hclk_low.clk,
 159                 .enable         = s5p64x0_hclk0_ctrl,
 160                 .ctrlbit        = (1 << 12),
 161         }, {
 162                 .name           = "hsmmc",
 163                 .id             = 0,
 164                 .parent         = &clk_hclk_low.clk,
 165                 .enable         = s5p64x0_hclk0_ctrl,
 166                 .ctrlbit        = (1 << 17),
 167         }, {
 168                 .name           = "hsmmc",
 169                 .id             = 1,
 170                 .parent         = &clk_hclk_low.clk,
 171                 .enable         = s5p64x0_hclk0_ctrl,
 172                 .ctrlbit        = (1 << 18),
 173         }, {
 174                 .name           = "hsmmc",
 175                 .id             = 2,
 176                 .parent         = &clk_hclk_low.clk,
 177                 .enable         = s5p64x0_hclk0_ctrl,
 178                 .ctrlbit        = (1 << 19),
 179         }, {
 180                 .name           = "otg",
 181                 .id             = -1,
 182                 .parent         = &clk_hclk_low.clk,
 183                 .enable         = s5p64x0_hclk0_ctrl,
 184                 .ctrlbit        = (1 << 20)
 185         }, {
 186                 .name           = "irom",
 187                 .id             = -1,
 188                 .parent         = &clk_hclk.clk,
 189                 .enable         = s5p64x0_hclk0_ctrl,
 190                 .ctrlbit        = (1 << 25),
 191         }, {
 192                 .name           = "lcd",
 193                 .id             = -1,
 194                 .parent         = &clk_hclk_low.clk,
 195                 .enable         = s5p64x0_hclk1_ctrl,
 196                 .ctrlbit        = (1 << 1),
 197         }, {
 198                 .name           = "hclk_fimgvg",
 199                 .id             = -1,
 200                 .parent         = &clk_hclk.clk,
 201                 .enable         = s5p64x0_hclk1_ctrl,
 202                 .ctrlbit        = (1 << 2),
 203         }, {
 204                 .name           = "tsi",
 205                 .id             = -1,
 206                 .parent         = &clk_hclk_low.clk,
 207                 .enable         = s5p64x0_hclk1_ctrl,
 208                 .ctrlbit        = (1 << 0),
 209         }, {
 210                 .name           = "watchdog",
 211                 .id             = -1,
 212                 .parent         = &clk_pclk_low.clk,
 213                 .enable         = s5p64x0_pclk_ctrl,
 214                 .ctrlbit        = (1 << 5),
 215         }, {
 216                 .name           = "rtc",
 217                 .id             = -1,
 218                 .parent         = &clk_pclk_low.clk,
 219                 .enable         = s5p64x0_pclk_ctrl,
 220                 .ctrlbit        = (1 << 6),
 221         }, {
 222                 .name           = "timers",
 223                 .id             = -1,
 224                 .parent         = &clk_pclk_low.clk,
 225                 .enable         = s5p64x0_pclk_ctrl,
 226                 .ctrlbit        = (1 << 7),
 227         }, {
 228                 .name           = "pcm",
 229                 .id             = -1,
 230                 .parent         = &clk_pclk_low.clk,
 231                 .enable         = s5p64x0_pclk_ctrl,
 232                 .ctrlbit        = (1 << 8),
 233         }, {
 234                 .name           = "adc",
 235                 .id             = -1,
 236                 .parent         = &clk_pclk_low.clk,
 237                 .enable         = s5p64x0_pclk_ctrl,
 238                 .ctrlbit        = (1 << 12),
 239         }, {
 240                 .name           = "i2c",
 241                 .id             = -1,
 242                 .parent         = &clk_pclk_low.clk,
 243                 .enable         = s5p64x0_pclk_ctrl,
 244                 .ctrlbit        = (1 << 17),
 245         }, {
 246                 .name           = "spi",
 247                 .id             = 0,
 248                 .parent         = &clk_pclk_low.clk,
 249                 .enable         = s5p64x0_pclk_ctrl,
 250                 .ctrlbit        = (1 << 21),
 251         }, {
 252                 .name           = "spi",
 253                 .id             = 1,
 254                 .parent         = &clk_pclk_low.clk,
 255                 .enable         = s5p64x0_pclk_ctrl,
 256                 .ctrlbit        = (1 << 22),
 257         }, {
 258                 .name           = "gps",
 259                 .id             = -1,
 260                 .parent         = &clk_pclk_low.clk,
 261                 .enable         = s5p64x0_pclk_ctrl,
 262                 .ctrlbit        = (1 << 25),
 263         }, {
 264                 .name           = "iis",
 265                 .id             = 0,
 266                 .parent         = &clk_pclk_low.clk,
 267                 .enable         = s5p64x0_pclk_ctrl,
 268                 .ctrlbit        = (1 << 26),
 269         }, {
 270                 .name           = "dsim",
 271                 .id             = -1,
 272                 .parent         = &clk_pclk_low.clk,
 273                 .enable         = s5p64x0_pclk_ctrl,
 274                 .ctrlbit        = (1 << 28),
 275         }, {
 276                 .name           = "etm",
 277                 .id             = -1,
 278                 .parent         = &clk_pclk.clk,
 279                 .enable         = s5p64x0_pclk_ctrl,
 280                 .ctrlbit        = (1 << 29),
 281         }, {
 282                 .name           = "dmc0",
 283                 .id             = -1,
 284                 .parent         = &clk_pclk.clk,
 285                 .enable         = s5p64x0_pclk_ctrl,
 286                 .ctrlbit        = (1 << 30),
 287         }, {
 288                 .name           = "pclk_fimgvg",
 289                 .id             = -1,
 290                 .parent         = &clk_pclk.clk,
 291                 .enable         = s5p64x0_pclk_ctrl,
 292                 .ctrlbit        = (1 << 31),
 293         }, {
 294                 .name           = "sclk_spi_48",
 295                 .id             = 0,
 296                 .parent         = &clk_48m,
 297                 .enable         = s5p64x0_sclk_ctrl,
 298                 .ctrlbit        = (1 << 22),
 299         }, {
 300                 .name           = "sclk_spi_48",
 301                 .id             = 1,
 302                 .parent         = &clk_48m,
 303                 .enable         = s5p64x0_sclk_ctrl,
 304                 .ctrlbit        = (1 << 23),
 305         }, {
 306                 .name           = "mmc_48m",
 307                 .id             = 0,
 308                 .parent         = &clk_48m,
 309                 .enable         = s5p64x0_sclk_ctrl,
 310                 .ctrlbit        = (1 << 27),
 311         }, {
 312                 .name           = "mmc_48m",
 313                 .id             = 1,
 314                 .parent         = &clk_48m,
 315                 .enable         = s5p64x0_sclk_ctrl,
 316                 .ctrlbit        = (1 << 28),
 317         }, {
 318                 .name           = "mmc_48m",
 319                 .id             = 2,
 320                 .parent         = &clk_48m,
 321                 .enable         = s5p64x0_sclk_ctrl,
 322                 .ctrlbit        = (1 << 29),
 323         },
 324 };
 325
 326 /*
 327  * The following clocks will be enabled during clock initialization.
 328  */
 329 static struct clk init_clocks[] = {
 330         {
 331                 .name           = "intc",
 332                 .id             = -1,
 333                 .parent         = &clk_hclk.clk,
 334                 .enable         = s5p64x0_hclk0_ctrl,
 335                 .ctrlbit        = (1 << 1),
 336         }, {
 337                 .name           = "mem",
 338                 .id             = -1,
 339                 .parent         = &clk_hclk.clk,
 340                 .enable         = s5p64x0_hclk0_ctrl,
 341                 .ctrlbit        = (1 << 21),
 342         }, {
 343                 .name           = "uart",
 344                 .id             = 0,
 345                 .parent         = &clk_pclk_low.clk,
 346                 .enable         = s5p64x0_pclk_ctrl,
 347                 .ctrlbit        = (1 << 1),
 348         }, {
 349                 .name           = "uart",
 350                 .id             = 1,
 351                 .parent         = &clk_pclk_low.clk,
 352                 .enable         = s5p64x0_pclk_ctrl,
 353                 .ctrlbit        = (1 << 2),
 354         }, {
 355                 .name           = "uart",
 356                 .id             = 2,
 357                 .parent         = &clk_pclk_low.clk,
 358                 .enable         = s5p64x0_pclk_ctrl,
 359                 .ctrlbit        = (1 << 3),
 360         }, {
 361                 .name           = "uart",
 362                 .id             = 3,
 363                 .parent         = &clk_pclk_low.clk,
 364                 .enable         = s5p64x0_pclk_ctrl,
 365                 .ctrlbit        = (1 << 4),
 366         }, {
 367                 .name           = "gpio",
 368                 .id             = -1,
 369                 .parent         = &clk_pclk_low.clk,
 370                 .enable         = s5p64x0_pclk_ctrl,
 371                 .ctrlbit        = (1 << 18),
 372         },
 373 };
 374
 375 static struct clk clk_iis_cd_v40 = {
 376         .name           = "iis_cdclk_v40",
 377         .id             = -1,
 378 };
 379
 380 static struct clk clk_pcm_cd = {
 381         .name           = "pcm_cdclk",
 382         .id             = -1,
 383 };
 384
 385 static struct clk *clkset_group1_list[] = {
 386         &clk_mout_epll.clk,
 387         &clk_dout_mpll.clk,
 388         &clk_fin_epll,
 389 };
 390
 391 static struct clksrc_sources clkset_group1 = {
 392         .sources        = clkset_group1_list,
 393         .nr_sources     = ARRAY_SIZE(clkset_group1_list),
 394 };
 395
 396 static struct clk *clkset_uart_list[] = {
 397         &clk_mout_epll.clk,
 398         &clk_dout_mpll.clk,
 399 };
 400
 401 static struct clksrc_sources clkset_uart = {
 402         .sources        = clkset_uart_list,
 403         .nr_sources     = ARRAY_SIZE(clkset_uart_list),
 404 };
 405
 406 static struct clk *clkset_audio_list[] = {
 407         &clk_mout_epll.clk,
 408         &clk_dout_mpll.clk,
 409         &clk_fin_epll,
 410         &clk_iis_cd_v40,
 411         &clk_pcm_cd,
 412 };
 413
 414 static struct clksrc_sources clkset_audio = {
 415         .sources        = clkset_audio_list,
 416         .nr_sources     = ARRAY_SIZE(clkset_audio_list),
 417 };
 418
 419 static struct clksrc_clk clksrcs[] = {
 420         {
 421                 .clk    = {
 422                         .name           = "sclk_mmc",
 423                         .id             = 0,
 424                         .ctrlbit        = (1 << 24),
 425                         .enable         = s5p64x0_sclk_ctrl,
 426                 },
 427                 .sources = &clkset_group1,
 428                 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
 429                 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
 430         }, {
 431                 .clk    = {
 432                         .name           = "sclk_mmc",
 433                         .id             = 1,
 434                         .ctrlbit        = (1 << 25),
 435                         .enable         = s5p64x0_sclk_ctrl,
 436                 },
 437                 .sources = &clkset_group1,
 438                 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
 439                 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
 440         }, {
 441                 .clk    = {
 442                         .name           = "sclk_mmc",
 443                         .id             = 2,
 444                         .ctrlbit        = (1 << 26),
 445                         .enable         = s5p64x0_sclk_ctrl,
 446                 },
 447                 .sources = &clkset_group1,
 448                 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
 449                 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
 450         }, {
 451                 .clk    = {
 452                         .name           = "uclk1",
 453                         .id             = -1,
 454                         .ctrlbit        = (1 << 5),
 455                         .enable         = s5p64x0_sclk_ctrl,
 456                 },
 457                 .sources = &clkset_uart,
 458                 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
 459                 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
 460         }, {
 461                 .clk    = {
 462                         .name           = "sclk_spi",
 463                         .id             = 0,
 464                         .ctrlbit        = (1 << 20),
 465                         .enable         = s5p64x0_sclk_ctrl,
 466                 },
 467                 .sources = &clkset_group1,
 468                 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
 469                 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
 470         }, {
 471                 .clk    = {
 472                         .name           = "sclk_spi",
 473                         .id             = 1,
 474                         .ctrlbit        = (1 << 21),
 475                         .enable         = s5p64x0_sclk_ctrl,
 476                 },
 477                 .sources = &clkset_group1,
 478                 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
 479                 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
 480         }, {
 481                 .clk    = {
 482                         .name           = "sclk_post",
 483                         .id             = -1,
 484                         .ctrlbit        = (1 << 10),
 485                         .enable         = s5p64x0_sclk_ctrl,
 486                 },
 487                 .sources = &clkset_group1,
 488                 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 26, .size = 2 },
 489                 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 12, .size = 4 },
 490         }, {
 491                 .clk    = {
 492                         .name           = "sclk_dispcon",
 493                         .id             = -1,
 494                         .ctrlbit        = (1 << 1),
 495                         .enable         = s5p64x0_sclk1_ctrl,
 496                 },
 497                 .sources = &clkset_group1,
 498                 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 4, .size = 2 },
 499                 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 0, .size = 4 },
 500         }, {
 501                 .clk    = {
 502                         .name           = "sclk_fimgvg",
 503                         .id             = -1,
 504                         .ctrlbit        = (1 << 2),
 505                         .enable         = s5p64x0_sclk1_ctrl,
 506                 },
 507                 .sources = &clkset_group1,
 508                 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 8, .size = 2 },
 509                 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 4, .size = 4 },
 510         }, {
 511                 .clk    = {
 512                         .name           = "sclk_audio2",
 513                         .id             = -1,
 514                         .ctrlbit        = (1 << 11),
 515                         .enable         = s5p64x0_sclk_ctrl,
 516                 },
 517                 .sources = &clkset_audio,
 518                 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 0, .size = 3 },
 519                 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 24, .size = 4 },
 520         },
 521 };
 522
 523 /* Clock initialization code */
 524 static struct clksrc_clk *sysclks[] = {
 525         &clk_mout_apll,
 526         &clk_mout_epll,
 527         &clk_mout_mpll,
 528         &clk_dout_mpll,
 529         &clk_armclk,
 530         &clk_hclk,
 531         &clk_pclk,
 532         &clk_hclk_low,
 533         &clk_pclk_low,
 534 };
 535
 536 void __init_or_cpufreq s5p6440_setup_clocks(void)
 537 {
 538         struct clk *xtal_clk;
 539
 540         unsigned long xtal;
 541         unsigned long fclk;
 542         unsigned long hclk;
 543         unsigned long hclk_low;
 544         unsigned long pclk;
 545         unsigned long pclk_low;
 546
 547         unsigned long apll;
 548         unsigned long mpll;
 549         unsigned long epll;
 550         unsigned int ptr;
 551
 552         /* Set S5P6440 functions for clk_fout_epll */
 553
 554         clk_fout_epll.enable = s5p_epll_enable;
 555         clk_fout_epll.ops = &s5p6440_epll_ops;
 556
 557         clk_48m.enable = s5p64x0_clk48m_ctrl;
 558
 559         xtal_clk = clk_get(NULL, "ext_xtal");
 560         BUG_ON(IS_ERR(xtal_clk));
 561
 562         xtal = clk_get_rate(xtal_clk);
 563         clk_put(xtal_clk);
 564
 565         apll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_APLL_CON), pll_4502);
 566         mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_MPLL_CON), pll_4502);
 567         epll = s5p_get_pll90xx(xtal, __raw_readl(S5P64X0_EPLL_CON),
 568                                 __raw_readl(S5P64X0_EPLL_CON_K));
 569
 570         clk_fout_apll.rate = apll;
 571         clk_fout_mpll.rate = mpll;
 572         clk_fout_epll.rate = epll;
 573
 574         printk(KERN_INFO "S5P6440: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
 575                         " E=%ld.%ldMHz\n",
 576                         print_mhz(apll), print_mhz(mpll), print_mhz(epll));
 577
 578         fclk = clk_get_rate(&clk_armclk.clk);
 579         hclk = clk_get_rate(&clk_hclk.clk);
 580         pclk = clk_get_rate(&clk_pclk.clk);
 581         hclk_low = clk_get_rate(&clk_hclk_low.clk);
 582         pclk_low = clk_get_rate(&clk_pclk_low.clk);
 583
 584         printk(KERN_INFO "S5P6440: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
 585                         " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
 586                         print_mhz(hclk), print_mhz(hclk_low),
 587                         print_mhz(pclk), print_mhz(pclk_low));
 588
 589         clk_f.rate = fclk;
 590         clk_h.rate = hclk;
 591         clk_p.rate = pclk;
 592
 593         for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
 594                 s3c_set_clksrc(&clksrcs[ptr], true);
 595 }
 596
 597 static struct clk *clks[] __initdata = {
 598         &clk_ext,
 599         &clk_iis_cd_v40,
 600         &clk_pcm_cd,
 601 };
 602
 603 void __init s5p6440_register_clocks(void)
 604 {
 605         int ptr;
 606
 607         s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
 608
 609         for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
 610                 s3c_register_clksrc(sysclks[ptr], 1);
 611
 612         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
 613         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
 614
 615         s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
 616         s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
 617
 618         s3c_pwmclk_init();
 619 }