arch/arm/mach-s5p64x0/clock-s5p6440.c

   1 /* linux/arch/arm/mach-s5p64x0/clock-s5p6440.c
   2  *
   3  * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * S5P6440 - Clock support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #include <linux/init.h>
  14 #include <linux/module.h>
  15 #include <linux/kernel.h>
  16 #include <linux/list.h>
  17 #include <linux/errno.h>
  18 #include <linux/err.h>
  19 #include <linux/clk.h>
  20 #include <linux/sysdev.h>
  21 #include <linux/io.h>
  22
  23 #include <mach/hardware.h>
  24 #include <mach/map.h>
  25 #include <mach/regs-clock.h>
  26 #include <mach/s5p64x0-clock.h>
  27
  28 #include <plat/cpu-freq.h>
  29 #include <plat/clock.h>
  30 #include <plat/cpu.h>
  31 #include <plat/pll.h>
  32 #include <plat/s5p-clock.h>
  33 #include <plat/clock-clksrc.h>
  34 #include <plat/s5p6440.h>
  35
  36 static u32 epll_div[][5] = {
  37         { 36000000,     0,      48, 1, 4 },
  38         { 48000000,     0,      32, 1, 3 },
  39         { 60000000,     0,      40, 1, 3 },
  40         { 72000000,     0,      48, 1, 3 },
  41         { 84000000,     0,      28, 1, 2 },
  42         { 96000000,     0,      32, 1, 2 },
  43         { 32768000,     45264,  43, 1, 4 },
  44         { 45158000,     6903,   30, 1, 3 },
  45         { 49152000,     50332,  32, 1, 3 },
  46         { 67738000,     10398,  45, 1, 3 },
  47         { 73728000,     9961,   49, 1, 3 }
  48 };
  49
  50 static int s5p6440_epll_set_rate(struct clk *clk, unsigned long rate)
  51 {
  52         unsigned int epll_con, epll_con_k;
  53         unsigned int i;
  54
  55         if (clk->rate == rate)  /* Return if nothing changed */
  56                 return 0;
  57
  58         epll_con = __raw_readl(S5P64X0_EPLL_CON);
  59         epll_con_k = __raw_readl(S5P64X0_EPLL_CON_K);
  60
  61         epll_con_k &= ~(PLL90XX_KDIV_MASK);
  62         epll_con &= ~(PLL90XX_MDIV_MASK | PLL90XX_PDIV_MASK | PLL90XX_SDIV_MASK);
  63
  64         for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
  65                  if (epll_div[i][0] == rate) {
  66                         epll_con_k |= (epll_div[i][1] << PLL90XX_KDIV_SHIFT);
  67                         epll_con |= (epll_div[i][2] << PLL90XX_MDIV_SHIFT) |
  68                                     (epll_div[i][3] << PLL90XX_PDIV_SHIFT) |
  69                                     (epll_div[i][4] << PLL90XX_SDIV_SHIFT);
  70                         break;
  71                 }
  72         }
  73
  74         if (i == ARRAY_SIZE(epll_div)) {
  75                 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
  76                 return -EINVAL;
  77         }
  78
  79         __raw_writel(epll_con, S5P64X0_EPLL_CON);
  80         __raw_writel(epll_con_k, S5P64X0_EPLL_CON_K);
  81
  82         printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
  83                         clk->rate, rate);
  84
  85         clk->rate = rate;
  86
  87         return 0;
  88 }
  89
  90 static struct clk_ops s5p6440_epll_ops = {
  91         .get_rate = s5p_epll_get_rate,
  92         .set_rate = s5p6440_epll_set_rate,
  93 };
  94
  95 static struct clksrc_clk clk_hclk = {
  96         .clk    = {
  97                 .name           = "clk_hclk",
  98                 .parent         = &clk_armclk.clk,
  99         },
 100         .reg_div        = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 },
 101 };
 102
 103 static struct clksrc_clk clk_pclk = {
 104         .clk    = {
 105                 .name           = "clk_pclk",
 106                 .parent         = &clk_hclk.clk,
 107         },
 108         .reg_div        = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 },
 109 };
 110 static struct clksrc_clk clk_hclk_low = {
 111         .clk    = {
 112                 .name           = "clk_hclk_low",
 113         },
 114         .sources        = &clkset_hclk_low,
 115         .reg_src        = { .reg = S5P64X0_SYS_OTHERS, .shift = 6, .size = 1 },
 116         .reg_div        = { .reg = S5P64X0_CLK_DIV3, .shift = 8, .size = 4 },
 117 };
 118
 119 static struct clksrc_clk clk_pclk_low = {
 120         .clk    = {
 121                 .name           = "clk_pclk_low",
 122                 .parent         = &clk_hclk_low.clk,
 123         },
 124         .reg_div        = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 },
 125 };
 126
 127 /*
 128  * The following clocks will be disabled during clock initialization. It is
 129  * recommended to keep the following clocks disabled until the driver requests
 130  * for enabling the clock.
 131  */
 132 static struct clk init_clocks_off[] = {
 133         {
 134                 .name           = "nand",
 135                 .parent         = &clk_hclk.clk,
 136                 .enable         = s5p64x0_mem_ctrl,
 137                 .ctrlbit        = (1 << 2),
 138         }, {
 139                 .name           = "post",
 140                 .parent         = &clk_hclk_low.clk,
 141                 .enable         = s5p64x0_hclk0_ctrl,
 142                 .ctrlbit        = (1 << 5)
 143         }, {
 144                 .name           = "2d",
 145                 .parent         = &clk_hclk.clk,
 146                 .enable         = s5p64x0_hclk0_ctrl,
 147                 .ctrlbit        = (1 << 8),
 148         }, {
 149                 .name           = "pdma",
 150                 .parent         = &clk_hclk_low.clk,
 151                 .enable         = s5p64x0_hclk0_ctrl,
 152                 .ctrlbit        = (1 << 12),
 153         }, {
 154                 .name           = "hsmmc",
 155                 .devname        = "s3c-sdhci.0",
 156                 .parent         = &clk_hclk_low.clk,
 157                 .enable         = s5p64x0_hclk0_ctrl,
 158                 .ctrlbit        = (1 << 17),
 159         }, {
 160                 .name           = "hsmmc",
 161                 .devname        = "s3c-sdhci.1",
 162                 .parent         = &clk_hclk_low.clk,
 163                 .enable         = s5p64x0_hclk0_ctrl,
 164                 .ctrlbit        = (1 << 18),
 165         }, {
 166                 .name           = "hsmmc",
 167                 .devname        = "s3c-sdhci.2",
 168                 .parent         = &clk_hclk_low.clk,
 169                 .enable         = s5p64x0_hclk0_ctrl,
 170                 .ctrlbit        = (1 << 19),
 171         }, {
 172                 .name           = "otg",
 173                 .parent         = &clk_hclk_low.clk,
 174                 .enable         = s5p64x0_hclk0_ctrl,
 175                 .ctrlbit        = (1 << 20)
 176         }, {
 177                 .name           = "irom",
 178                 .parent         = &clk_hclk.clk,
 179                 .enable         = s5p64x0_hclk0_ctrl,
 180                 .ctrlbit        = (1 << 25),
 181         }, {
 182                 .name           = "lcd",
 183                 .parent         = &clk_hclk_low.clk,
 184                 .enable         = s5p64x0_hclk1_ctrl,
 185                 .ctrlbit        = (1 << 1),
 186         }, {
 187                 .name           = "hclk_fimgvg",
 188                 .parent         = &clk_hclk.clk,
 189                 .enable         = s5p64x0_hclk1_ctrl,
 190                 .ctrlbit        = (1 << 2),
 191         }, {
 192                 .name           = "tsi",
 193                 .parent         = &clk_hclk_low.clk,
 194                 .enable         = s5p64x0_hclk1_ctrl,
 195                 .ctrlbit        = (1 << 0),
 196         }, {
 197                 .name           = "watchdog",
 198                 .parent         = &clk_pclk_low.clk,
 199                 .enable         = s5p64x0_pclk_ctrl,
 200                 .ctrlbit        = (1 << 5),
 201         }, {
 202                 .name           = "rtc",
 203                 .parent         = &clk_pclk_low.clk,
 204                 .enable         = s5p64x0_pclk_ctrl,
 205                 .ctrlbit        = (1 << 6),
 206         }, {
 207                 .name           = "timers",
 208                 .parent         = &clk_pclk_low.clk,
 209                 .enable         = s5p64x0_pclk_ctrl,
 210                 .ctrlbit        = (1 << 7),
 211         }, {
 212                 .name           = "pcm",
 213                 .parent         = &clk_pclk_low.clk,
 214                 .enable         = s5p64x0_pclk_ctrl,
 215                 .ctrlbit        = (1 << 8),
 216         }, {
 217                 .name           = "adc",
 218                 .parent         = &clk_pclk_low.clk,
 219                 .enable         = s5p64x0_pclk_ctrl,
 220                 .ctrlbit        = (1 << 12),
 221         }, {
 222                 .name           = "i2c",
 223                 .parent         = &clk_pclk_low.clk,
 224                 .enable         = s5p64x0_pclk_ctrl,
 225                 .ctrlbit        = (1 << 17),
 226         }, {
 227                 .name           = "spi",
 228                 .devname        = "s3c64xx-spi.0",
 229                 .parent         = &clk_pclk_low.clk,
 230                 .enable         = s5p64x0_pclk_ctrl,
 231                 .ctrlbit        = (1 << 21),
 232         }, {
 233                 .name           = "spi",
 234                 .devname        = "s3c64xx-spi.1",
 235                 .parent         = &clk_pclk_low.clk,
 236                 .enable         = s5p64x0_pclk_ctrl,
 237                 .ctrlbit        = (1 << 22),
 238         }, {
 239                 .name           = "gps",
 240                 .parent         = &clk_pclk_low.clk,
 241                 .enable         = s5p64x0_pclk_ctrl,
 242                 .ctrlbit        = (1 << 25),
 243         }, {
 244                 .name           = "iis",
 245                 .devname        = "samsung-i2s.0",
 246                 .parent         = &clk_pclk_low.clk,
 247                 .enable         = s5p64x0_pclk_ctrl,
 248                 .ctrlbit        = (1 << 26),
 249         }, {
 250                 .name           = "dsim",
 251                 .parent         = &clk_pclk_low.clk,
 252                 .enable         = s5p64x0_pclk_ctrl,
 253                 .ctrlbit        = (1 << 28),
 254         }, {
 255                 .name           = "etm",
 256                 .parent         = &clk_pclk.clk,
 257                 .enable         = s5p64x0_pclk_ctrl,
 258                 .ctrlbit        = (1 << 29),
 259         }, {
 260                 .name           = "dmc0",
 261                 .parent         = &clk_pclk.clk,
 262                 .enable         = s5p64x0_pclk_ctrl,
 263                 .ctrlbit        = (1 << 30),
 264         }, {
 265                 .name           = "pclk_fimgvg",
 266                 .parent         = &clk_pclk.clk,
 267                 .enable         = s5p64x0_pclk_ctrl,
 268                 .ctrlbit        = (1 << 31),
 269         }, {
 270                 .name           = "sclk_spi_48",
 271                 .devname        = "s3c64xx-spi.0",
 272                 .parent         = &clk_48m,
 273                 .enable         = s5p64x0_sclk_ctrl,
 274                 .ctrlbit        = (1 << 22),
 275         }, {
 276                 .name           = "sclk_spi_48",
 277                 .devname        = "s3c64xx-spi.1",
 278                 .parent         = &clk_48m,
 279                 .enable         = s5p64x0_sclk_ctrl,
 280                 .ctrlbit        = (1 << 23),
 281         }, {
 282                 .name           = "mmc_48m",
 283                 .devname        = "s3c-sdhci.0",
 284                 .parent         = &clk_48m,
 285                 .enable         = s5p64x0_sclk_ctrl,
 286                 .ctrlbit        = (1 << 27),
 287         }, {
 288                 .name           = "mmc_48m",
 289                 .devname        = "s3c-sdhci.1",
 290                 .parent         = &clk_48m,
 291                 .enable         = s5p64x0_sclk_ctrl,
 292                 .ctrlbit        = (1 << 28),
 293         }, {
 294                 .name           = "mmc_48m",
 295                 .devname        = "s3c-sdhci.2",
 296                 .parent         = &clk_48m,
 297                 .enable         = s5p64x0_sclk_ctrl,
 298                 .ctrlbit        = (1 << 29),
 299         },
 300 };
 301
 302 /*
 303  * The following clocks will be enabled during clock initialization.
 304  */
 305 static struct clk init_clocks[] = {
 306         {
 307                 .name           = "intc",
 308                 .parent         = &clk_hclk.clk,
 309                 .enable         = s5p64x0_hclk0_ctrl,
 310                 .ctrlbit        = (1 << 1),
 311         }, {
 312                 .name           = "mem",
 313                 .parent         = &clk_hclk.clk,
 314                 .enable         = s5p64x0_hclk0_ctrl,
 315                 .ctrlbit        = (1 << 21),
 316         }, {
 317                 .name           = "uart",
 318                 .devname        = "s3c6400-uart.0",
 319                 .parent         = &clk_pclk_low.clk,
 320                 .enable         = s5p64x0_pclk_ctrl,
 321                 .ctrlbit        = (1 << 1),
 322         }, {
 323                 .name           = "uart",
 324                 .devname        = "s3c6400-uart.1",
 325                 .parent         = &clk_pclk_low.clk,
 326                 .enable         = s5p64x0_pclk_ctrl,
 327                 .ctrlbit        = (1 << 2),
 328         }, {
 329                 .name           = "uart",
 330                 .devname        = "s3c6400-uart.2",
 331                 .parent         = &clk_pclk_low.clk,
 332                 .enable         = s5p64x0_pclk_ctrl,
 333                 .ctrlbit        = (1 << 3),
 334         }, {
 335                 .name           = "uart",
 336                 .devname        = "s3c6400-uart.3",
 337                 .parent         = &clk_pclk_low.clk,
 338                 .enable         = s5p64x0_pclk_ctrl,
 339                 .ctrlbit        = (1 << 4),
 340         }, {
 341                 .name           = "gpio",
 342                 .parent         = &clk_pclk_low.clk,
 343                 .enable         = s5p64x0_pclk_ctrl,
 344                 .ctrlbit        = (1 << 18),
 345         },
 346 };
 347
 348 static struct clk clk_iis_cd_v40 = {
 349         .name           = "iis_cdclk_v40",
 350 };
 351
 352 static struct clk clk_pcm_cd = {
 353         .name           = "pcm_cdclk",
 354 };
 355
 356 static struct clk *clkset_group1_list[] = {
 357         &clk_mout_epll.clk,
 358         &clk_dout_mpll.clk,
 359         &clk_fin_epll,
 360 };
 361
 362 static struct clksrc_sources clkset_group1 = {
 363         .sources        = clkset_group1_list,
 364         .nr_sources     = ARRAY_SIZE(clkset_group1_list),
 365 };
 366
 367 static struct clk *clkset_uart_list[] = {
 368         &clk_mout_epll.clk,
 369         &clk_dout_mpll.clk,
 370 };
 371
 372 static struct clksrc_sources clkset_uart = {
 373         .sources        = clkset_uart_list,
 374         .nr_sources     = ARRAY_SIZE(clkset_uart_list),
 375 };
 376
 377 static struct clk *clkset_audio_list[] = {
 378         &clk_mout_epll.clk,
 379         &clk_dout_mpll.clk,
 380         &clk_fin_epll,
 381         &clk_iis_cd_v40,
 382         &clk_pcm_cd,
 383 };
 384
 385 static struct clksrc_sources clkset_audio = {
 386         .sources        = clkset_audio_list,
 387         .nr_sources     = ARRAY_SIZE(clkset_audio_list),
 388 };
 389
 390 static struct clksrc_clk clksrcs[] = {
 391         {
 392                 .clk    = {
 393                         .name           = "sclk_mmc",
 394                         .devname        = "s3c-sdhci.0",
 395                         .ctrlbit        = (1 << 24),
 396                         .enable         = s5p64x0_sclk_ctrl,
 397                 },
 398                 .sources = &clkset_group1,
 399                 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
 400                 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
 401         }, {
 402                 .clk    = {
 403                         .name           = "sclk_mmc",
 404                         .devname        = "s3c-sdhci.1",
 405                         .ctrlbit        = (1 << 25),
 406                         .enable         = s5p64x0_sclk_ctrl,
 407                 },
 408                 .sources = &clkset_group1,
 409                 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
 410                 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
 411         }, {
 412                 .clk    = {
 413                         .name           = "sclk_mmc",
 414                         .devname        = "s3c-sdhci.2",
 415                         .ctrlbit        = (1 << 26),
 416                         .enable         = s5p64x0_sclk_ctrl,
 417                 },
 418                 .sources = &clkset_group1,
 419                 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
 420                 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
 421         }, {
 422                 .clk    = {
 423                         .name           = "uclk1",
 424                         .ctrlbit        = (1 << 5),
 425                         .enable         = s5p64x0_sclk_ctrl,
 426                 },
 427                 .sources = &clkset_uart,
 428                 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
 429                 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
 430         }, {
 431                 .clk    = {
 432                         .name           = "sclk_spi",
 433                         .devname        = "s3c64xx-spi.0",
 434                         .ctrlbit        = (1 << 20),
 435                         .enable         = s5p64x0_sclk_ctrl,
 436                 },
 437                 .sources = &clkset_group1,
 438                 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
 439                 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
 440         }, {
 441                 .clk    = {
 442                         .name           = "sclk_spi",
 443                         .devname        = "s3c64xx-spi.1",
 444                         .ctrlbit        = (1 << 21),
 445                         .enable         = s5p64x0_sclk_ctrl,
 446                 },
 447                 .sources = &clkset_group1,
 448                 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
 449                 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
 450         }, {
 451                 .clk    = {
 452                         .name           = "sclk_post",
 453                         .ctrlbit        = (1 << 10),
 454                         .enable         = s5p64x0_sclk_ctrl,
 455                 },
 456                 .sources = &clkset_group1,
 457                 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 26, .size = 2 },
 458                 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 12, .size = 4 },
 459         }, {
 460                 .clk    = {
 461                         .name           = "sclk_dispcon",
 462                         .ctrlbit        = (1 << 1),
 463                         .enable         = s5p64x0_sclk1_ctrl,
 464                 },
 465                 .sources = &clkset_group1,
 466                 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 4, .size = 2 },
 467                 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 0, .size = 4 },
 468         }, {
 469                 .clk    = {
 470                         .name           = "sclk_fimgvg",
 471                         .ctrlbit        = (1 << 2),
 472                         .enable         = s5p64x0_sclk1_ctrl,
 473                 },
 474                 .sources = &clkset_group1,
 475                 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 8, .size = 2 },
 476                 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 4, .size = 4 },
 477         }, {
 478                 .clk    = {
 479                         .name           = "sclk_audio2",
 480                         .ctrlbit        = (1 << 11),
 481                         .enable         = s5p64x0_sclk_ctrl,
 482                 },
 483                 .sources = &clkset_audio,
 484                 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 0, .size = 3 },
 485                 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 24, .size = 4 },
 486         },
 487 };
 488
 489 /* Clock initialization code */
 490 static struct clksrc_clk *sysclks[] = {
 491         &clk_mout_apll,
 492         &clk_mout_epll,
 493         &clk_mout_mpll,
 494         &clk_dout_mpll,
 495         &clk_armclk,
 496         &clk_hclk,
 497         &clk_pclk,
 498         &clk_hclk_low,
 499         &clk_pclk_low,
 500 };
 501
 502 void __init_or_cpufreq s5p6440_setup_clocks(void)
 503 {
 504         struct clk *xtal_clk;
 505
 506         unsigned long xtal;
 507         unsigned long fclk;
 508         unsigned long hclk;
 509         unsigned long hclk_low;
 510         unsigned long pclk;
 511         unsigned long pclk_low;
 512
 513         unsigned long apll;
 514         unsigned long mpll;
 515         unsigned long epll;
 516         unsigned int ptr;
 517
 518         /* Set S5P6440 functions for clk_fout_epll */
 519
 520         clk_fout_epll.enable = s5p_epll_enable;
 521         clk_fout_epll.ops = &s5p6440_epll_ops;
 522
 523         clk_48m.enable = s5p64x0_clk48m_ctrl;
 524
 525         xtal_clk = clk_get(NULL, "ext_xtal");
 526         BUG_ON(IS_ERR(xtal_clk));
 527
 528         xtal = clk_get_rate(xtal_clk);
 529         clk_put(xtal_clk);
 530
 531         apll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_APLL_CON), pll_4502);
 532         mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_MPLL_CON), pll_4502);
 533         epll = s5p_get_pll90xx(xtal, __raw_readl(S5P64X0_EPLL_CON),
 534                                 __raw_readl(S5P64X0_EPLL_CON_K));
 535
 536         clk_fout_apll.rate = apll;
 537         clk_fout_mpll.rate = mpll;
 538         clk_fout_epll.rate = epll;
 539
 540         printk(KERN_INFO "S5P6440: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
 541                         " E=%ld.%ldMHz\n",
 542                         print_mhz(apll), print_mhz(mpll), print_mhz(epll));
 543
 544         fclk = clk_get_rate(&clk_armclk.clk);
 545         hclk = clk_get_rate(&clk_hclk.clk);
 546         pclk = clk_get_rate(&clk_pclk.clk);
 547         hclk_low = clk_get_rate(&clk_hclk_low.clk);
 548         pclk_low = clk_get_rate(&clk_pclk_low.clk);
 549
 550         printk(KERN_INFO "S5P6440: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
 551                         " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
 552                         print_mhz(hclk), print_mhz(hclk_low),
 553                         print_mhz(pclk), print_mhz(pclk_low));
 554
 555         clk_f.rate = fclk;
 556         clk_h.rate = hclk;
 557         clk_p.rate = pclk;
 558
 559         for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
 560                 s3c_set_clksrc(&clksrcs[ptr], true);
 561 }
 562
 563 static struct clk *clks[] __initdata = {
 564         &clk_ext,
 565         &clk_iis_cd_v40,
 566         &clk_pcm_cd,
 567 };
 568
 569 void __init s5p6440_register_clocks(void)
 570 {
 571         int ptr;
 572
 573         s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
 574
 575         for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
 576                 s3c_register_clksrc(sysclks[ptr], 1);
 577
 578         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
 579         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
 580
 581         s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
 582         s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
 583
 584         s3c_pwmclk_init();
 585 }