arch/arm/mach-s3c2440/mach-osiris.c

   1 /* linux/arch/arm/mach-s3c2440/mach-osiris.c
   2  *
   3  * Copyright (c) 2005 Simtec Electronics
   4  *      http://armlinux.simtec.co.uk/
   5  *      Ben Dooks <ben@simtec.co.uk>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/types.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/list.h>
  16 #include <linux/timer.h>
  17 #include <linux/init.h>
  18 #include <linux/device.h>
  19 #include <linux/serial_core.h>
  20
  21 #include <asm/mach/arch.h>
  22 #include <asm/mach/map.h>
  23 #include <asm/mach/irq.h>
  24
  25 #include <asm/arch/osiris-map.h>
  26 #include <asm/arch/osiris-cpld.h>
  27
  28 #include <asm/hardware.h>
  29 #include <asm/io.h>
  30 #include <asm/irq.h>
  31 #include <asm/mach-types.h>
  32
  33 #include <asm/arch/regs-serial.h>
  34 #include <asm/arch/regs-gpio.h>
  35 #include <asm/arch/regs-mem.h>
  36 #include <asm/arch/regs-lcd.h>
  37 #include <asm/arch/nand.h>
  38
  39 #include <linux/mtd/mtd.h>
  40 #include <linux/mtd/nand.h>
  41 #include <linux/mtd/nand_ecc.h>
  42 #include <linux/mtd/partitions.h>
  43
  44 #include <asm/plat-s3c24xx/clock.h>
  45 #include <asm/plat-s3c24xx/devs.h>
  46 #include <asm/plat-s3c24xx/cpu.h>
  47
  48 /* onboard perihpheral map */
  49
  50 static struct map_desc osiris_iodesc[] __initdata = {
  51   /* ISA IO areas (may be over-written later) */
  52
  53   {
  54           .virtual      = (u32)S3C24XX_VA_ISA_BYTE,
  55           .pfn          = __phys_to_pfn(S3C2410_CS5),
  56           .length       = SZ_16M,
  57           .type         = MT_DEVICE,
  58   }, {
  59           .virtual      = (u32)S3C24XX_VA_ISA_WORD,
  60           .pfn          = __phys_to_pfn(S3C2410_CS5),
  61           .length       = SZ_16M,
  62           .type         = MT_DEVICE,
  63   },
  64
  65   /* CPLD control registers */
  66
  67   {
  68           .virtual      = (u32)OSIRIS_VA_CTRL1,
  69           .pfn          = __phys_to_pfn(OSIRIS_PA_CTRL1),
  70           .length       = SZ_16K,
  71           .type         = MT_DEVICE,
  72   }, {
  73           .virtual      = (u32)OSIRIS_VA_CTRL2,
  74           .pfn          = __phys_to_pfn(OSIRIS_PA_CTRL2),
  75           .length       = SZ_16K,
  76           .type         = MT_DEVICE,
  77   },
  78 };
  79
  80 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
  81 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
  82 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
  83
  84 static struct s3c24xx_uart_clksrc osiris_serial_clocks[] = {
  85         [0] = {
  86                 .name           = "uclk",
  87                 .divisor        = 1,
  88                 .min_baud       = 0,
  89                 .max_baud       = 0,
  90         },
  91         [1] = {
  92                 .name           = "pclk",
  93                 .divisor        = 1,
  94                 .min_baud       = 0,
  95                 .max_baud       = 0,
  96         }
  97 };
  98
  99 static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
 100         [0] = {
 101                 .hwport      = 0,
 102                 .flags       = 0,
 103                 .ucon        = UCON,
 104                 .ulcon       = ULCON,
 105                 .ufcon       = UFCON,
 106                 .clocks      = osiris_serial_clocks,
 107                 .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
 108         },
 109         [1] = {
 110                 .hwport      = 1,
 111                 .flags       = 0,
 112                 .ucon        = UCON,
 113                 .ulcon       = ULCON,
 114                 .ufcon       = UFCON,
 115                 .clocks      = osiris_serial_clocks,
 116                 .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
 117         },
 118         [2] = {
 119                 .hwport      = 2,
 120                 .flags       = 0,
 121                 .ucon        = UCON,
 122                 .ulcon       = ULCON,
 123                 .ufcon       = UFCON,
 124                 .clocks      = osiris_serial_clocks,
 125                 .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
 126         }
 127 };
 128
 129 /* NAND Flash on Osiris board */
 130
 131 static int external_map[]   = { 2 };
 132 static int chip0_map[]      = { 0 };
 133 static int chip1_map[]      = { 1 };
 134
 135 static struct mtd_partition osiris_default_nand_part[] = {
 136         [0] = {
 137                 .name   = "Boot Agent",
 138                 .size   = SZ_16K,
 139                 .offset = 0,
 140         },
 141         [1] = {
 142                 .name   = "/boot",
 143                 .size   = SZ_4M - SZ_16K,
 144                 .offset = SZ_16K,
 145         },
 146         [2] = {
 147                 .name   = "user1",
 148                 .offset = SZ_4M,
 149                 .size   = SZ_32M - SZ_4M,
 150         },
 151         [3] = {
 152                 .name   = "user2",
 153                 .offset = SZ_32M,
 154                 .size   = MTDPART_SIZ_FULL,
 155         }
 156 };
 157
 158 /* the Osiris has 3 selectable slots for nand-flash, the two
 159  * on-board chip areas, as well as the external slot.
 160  *
 161  * Note, there is no current hot-plug support for the External
 162  * socket.
 163 */
 164
 165 static struct s3c2410_nand_set osiris_nand_sets[] = {
 166         [1] = {
 167                 .name           = "External",
 168                 .nr_chips       = 1,
 169                 .nr_map         = external_map,
 170                 .nr_partitions  = ARRAY_SIZE(osiris_default_nand_part),
 171                 .partitions     = osiris_default_nand_part,
 172         },
 173         [0] = {
 174                 .name           = "chip0",
 175                 .nr_chips       = 1,
 176                 .nr_map         = chip0_map,
 177                 .nr_partitions  = ARRAY_SIZE(osiris_default_nand_part),
 178                 .partitions     = osiris_default_nand_part,
 179         },
 180         [2] = {
 181                 .name           = "chip1",
 182                 .nr_chips       = 1,
 183                 .nr_map         = chip1_map,
 184                 .nr_partitions  = ARRAY_SIZE(osiris_default_nand_part),
 185                 .partitions     = osiris_default_nand_part,
 186         },
 187 };
 188
 189 static void osiris_nand_select(struct s3c2410_nand_set *set, int slot)
 190 {
 191         unsigned int tmp;
 192
 193         slot = set->nr_map[slot] & 3;
 194
 195         pr_debug("osiris_nand: selecting slot %d (set %p,%p)\n",
 196                  slot, set, set->nr_map);
 197
 198         tmp = __raw_readb(OSIRIS_VA_CTRL1);
 199         tmp &= ~OSIRIS_CTRL1_NANDSEL;
 200         tmp |= slot;
 201
 202         pr_debug("osiris_nand: ctrl1 now %02x\n", tmp);
 203
 204         __raw_writeb(tmp, OSIRIS_VA_CTRL1);
 205 }
 206
 207 static struct s3c2410_platform_nand osiris_nand_info = {
 208         .tacls          = 25,
 209         .twrph0         = 60,
 210         .twrph1         = 60,
 211         .nr_sets        = ARRAY_SIZE(osiris_nand_sets),
 212         .sets           = osiris_nand_sets,
 213         .select_chip    = osiris_nand_select,
 214 };
 215
 216 /* PCMCIA control and configuration */
 217
 218 static struct resource osiris_pcmcia_resource[] = {
 219         [0] = {
 220                 .start  = 0x0f000000,
 221                 .end    = 0x0f100000,
 222                 .flags  = IORESOURCE_MEM,
 223         },
 224         [1] = {
 225                 .start  = 0x0c000000,
 226                 .end    = 0x0c100000,
 227                 .flags  = IORESOURCE_MEM,
 228         }
 229 };
 230
 231 static struct platform_device osiris_pcmcia = {
 232         .name           = "osiris-pcmcia",
 233         .id             = -1,
 234         .num_resources  = ARRAY_SIZE(osiris_pcmcia_resource),
 235         .resource       = osiris_pcmcia_resource,
 236 };
 237
 238 /* Standard Osiris devices */
 239
 240 static struct platform_device *osiris_devices[] __initdata = {
 241         &s3c_device_i2c,
 242         &s3c_device_nand,
 243         &osiris_pcmcia,
 244 };
 245
 246 static struct clk *osiris_clocks[] = {
 247         &s3c24xx_dclk0,
 248         &s3c24xx_dclk1,
 249         &s3c24xx_clkout0,
 250         &s3c24xx_clkout1,
 251         &s3c24xx_uclk,
 252 };
 253
 254 static struct s3c24xx_board osiris_board __initdata = {
 255         .devices       = osiris_devices,
 256         .devices_count = ARRAY_SIZE(osiris_devices),
 257         .clocks        = osiris_clocks,
 258         .clocks_count  = ARRAY_SIZE(osiris_clocks),
 259 };
 260
 261 static void __init osiris_map_io(void)
 262 {
 263         unsigned long flags;
 264
 265         /* initialise the clocks */
 266
 267         s3c24xx_dclk0.parent = NULL;
 268         s3c24xx_dclk0.rate   = 12*1000*1000;
 269
 270         s3c24xx_dclk1.parent = NULL;
 271         s3c24xx_dclk1.rate   = 24*1000*1000;
 272
 273         s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
 274         s3c24xx_clkout1.parent  = &s3c24xx_dclk1;
 275
 276         s3c24xx_uclk.parent  = &s3c24xx_clkout1;
 277
 278         s3c_device_nand.dev.platform_data = &osiris_nand_info;
 279
 280         s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc));
 281         s3c24xx_init_clocks(0);
 282         s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs));
 283         s3c24xx_set_board(&osiris_board);
 284
 285         /* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */
 286
 287         local_irq_save(flags);
 288         __raw_writel(__raw_readl(S3C2410_BWSCON) | S3C2410_BWSCON_ST1 | S3C2410_BWSCON_ST2 | S3C2410_BWSCON_ST3 | S3C2410_BWSCON_ST4 | S3C2410_BWSCON_ST5, S3C2410_BWSCON);
 289         local_irq_restore(flags);
 290
 291         /* write-protect line to the NAND */
 292         s3c2410_gpio_setpin(S3C2410_GPA0, 1);
 293 }
 294
 295 MACHINE_START(OSIRIS, "Simtec-OSIRIS")
 296         /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
 297         .phys_io        = S3C2410_PA_UART,
 298         .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
 299         .boot_params    = S3C2410_SDRAM_PA + 0x100,
 300         .map_io         = osiris_map_io,
 301         .init_irq       = s3c24xx_init_irq,
 302         .timer          = &s3c24xx_timer,
 303 MACHINE_END