arch/arm/mach-s3c2416/clock.c

   1 /* linux/arch/arm/mach-s3c2416/clock.c
   2  *
   3  * Copyright (c) 2010 Simtec Electronics
   4  * Copyright (c) 2010 Ben Dooks <ben-linux@fluff.org>
   5  *
   6  * S3C2416 Clock control support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/init.h>
  15 #include <linux/clk.h>
  16
  17 #include <plat/s3c2416.h>
  18 #include <plat/s3c2443.h>
  19 #include <plat/clock.h>
  20 #include <plat/clock-clksrc.h>
  21 #include <plat/cpu.h>
  22
  23 #include <plat/cpu-freq.h>
  24 #include <plat/pll.h>
  25
  26 #include <asm/mach/map.h>
  27
  28 #include <mach/regs-clock.h>
  29 #include <mach/regs-s3c2443-clock.h>
  30
  31 /* armdiv
  32  *
  33  * this clock is sourced from msysclk and can have a number of
  34  * divider values applied to it to then be fed into armclk.
  35  * The real clock definition is done in s3c2443-clock.c,
  36  * only the armdiv divisor table must be defined here.
  37 */
  38
  39 static unsigned int armdiv[8] = {
  40         [0] = 1,
  41         [1] = 2,
  42         [2] = 3,
  43         [3] = 4,
  44         [5] = 6,
  45         [7] = 8,
  46 };
  47
  48 static struct clksrc_clk hsspi_eplldiv = {
  49         .clk = {
  50                 .name   = "hsspi-eplldiv",
  51                 .parent = &clk_esysclk.clk,
  52                 .ctrlbit = (1 << 14),
  53                 .enable = s3c2443_clkcon_enable_s,
  54         },
  55         .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 24 },
  56 };
  57
  58 static struct clk *hsspi_sources[] = {
  59         [0] = &hsspi_eplldiv.clk,
  60         [1] = NULL, /* to fix */
  61 };
  62
  63 static struct clksrc_clk hsspi_mux = {
  64         .clk    = {
  65                 .name   = "hsspi-if",
  66         },
  67         .sources = &(struct clksrc_sources) {
  68                 .sources = hsspi_sources,
  69                 .nr_sources = ARRAY_SIZE(hsspi_sources),
  70         },
  71         .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 18 },
  72 };
  73
  74 static struct clksrc_clk hsmmc_div[] = {
  75         [0] = {
  76                 .clk = {
  77                         .name   = "hsmmc-div",
  78                         .devname        = "s3c-sdhci.0",
  79                         .parent = &clk_esysclk.clk,
  80                 },
  81                 .reg_div = { .reg = S3C2416_CLKDIV2, .size = 2, .shift = 6 },
  82         },
  83         [1] = {
  84                 .clk = {
  85                         .name   = "hsmmc-div",
  86                         .devname        = "s3c-sdhci.1",
  87                         .parent = &clk_esysclk.clk,
  88                 },
  89                 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
  90         },
  91 };
  92
  93 static struct clksrc_clk hsmmc_mux[] = {
  94         [0] = {
  95                 .clk    = {
  96                         .name   = "hsmmc-if",
  97                         .devname        = "s3c-sdhci.0",
  98                         .ctrlbit = (1 << 6),
  99                         .enable = s3c2443_clkcon_enable_s,
 100                 },
 101                 .sources = &(struct clksrc_sources) {
 102                         .nr_sources = 2,
 103                         .sources = (struct clk *[]) {
 104                                 [0] = &hsmmc_div[0].clk,
 105                                 [1] = NULL, /* to fix */
 106                         },
 107                 },
 108                 .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 16 },
 109         },
 110         [1] = {
 111                 .clk    = {
 112                         .name   = "hsmmc-if",
 113                         .devname        = "s3c-sdhci.1",
 114                         .ctrlbit = (1 << 12),
 115                         .enable = s3c2443_clkcon_enable_s,
 116                 },
 117                 .sources = &(struct clksrc_sources) {
 118                         .nr_sources = 2,
 119                         .sources = (struct clk *[]) {
 120                                 [0] = &hsmmc_div[1].clk,
 121                                 [1] = NULL, /* to fix */
 122                         },
 123                 },
 124                 .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 17 },
 125         },
 126 };
 127
 128 static struct clk hsmmc0_clk = {
 129         .name           = "hsmmc",
 130         .devname        = "s3c-sdhci.0",
 131         .parent         = &clk_h,
 132         .enable         = s3c2443_clkcon_enable_h,
 133         .ctrlbit        = S3C2416_HCLKCON_HSMMC0,
 134 };
 135
 136 void __init_or_cpufreq s3c2416_setup_clocks(void)
 137 {
 138         s3c2443_common_setup_clocks(s3c2416_get_pll);
 139 }
 140
 141
 142 static struct clksrc_clk *clksrcs[] __initdata = {
 143         &hsspi_eplldiv,
 144         &hsspi_mux,
 145         &hsmmc_div[0],
 146         &hsmmc_div[1],
 147         &hsmmc_mux[0],
 148         &hsmmc_mux[1],
 149 };
 150
 151 void __init s3c2416_init_clocks(int xtal)
 152 {
 153         u32 epllcon = __raw_readl(S3C2443_EPLLCON);
 154         u32 epllcon1 = __raw_readl(S3C2443_EPLLCON+4);
 155         int ptr;
 156
 157         /* s3c2416 EPLL compatible with s3c64xx */
 158         clk_epll.rate = s3c_get_pll6553x(xtal, epllcon, epllcon1);
 159
 160         clk_epll.parent = &clk_epllref.clk;
 161
 162         s3c2443_common_init_clocks(xtal, s3c2416_get_pll,
 163                                    armdiv, ARRAY_SIZE(armdiv),
 164                                    S3C2416_CLKDIV0_ARMDIV_MASK);
 165
 166         for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
 167                 s3c_register_clksrc(clksrcs[ptr], 1);
 168
 169         s3c24xx_register_clock(&hsmmc0_clk);
 170
 171         s3c_pwmclk_init();
 172
 173 }