arch/arm/mach-s3c2410/mach-qt2410.c

   1 /* linux/arch/arm/mach-s3c2410/mach-qt2410.c
   2  *
   3  * Copyright (C) 2006 by OpenMoko, Inc.
   4  * Author: Harald Welte <laforge@openmoko.org>
   5  * All rights reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  *
  22  */
  23
  24 #include <linux/kernel.h>
  25 #include <linux/types.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/list.h>
  28 #include <linux/timer.h>
  29 #include <linux/init.h>
  30 #include <linux/gpio.h>
  31 #include <linux/sysdev.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/serial_core.h>
  34 #include <linux/spi/spi.h>
  35 #include <linux/spi/spi_bitbang.h>
  36 #include <linux/io.h>
  37 #include <linux/mtd/mtd.h>
  38 #include <linux/mtd/nand.h>
  39 #include <linux/mtd/nand_ecc.h>
  40 #include <linux/mtd/partitions.h>
  41
  42 #include <asm/mach/arch.h>
  43 #include <asm/mach/map.h>
  44 #include <asm/mach/irq.h>
  45
  46 #include <mach/hardware.h>
  47 #include <asm/irq.h>
  48 #include <asm/mach-types.h>
  49
  50 #include <mach/regs-gpio.h>
  51 #include <mach/leds-gpio.h>
  52 #include <plat/regs-serial.h>
  53 #include <mach/fb.h>
  54 #include <plat/nand.h>
  55 #include <plat/udc.h>
  56 #include <mach/spi.h>
  57 #include <mach/spi-gpio.h>
  58 #include <plat/iic.h>
  59
  60 #include <plat/common-smdk.h>
  61 #include <plat/gpio-cfg.h>
  62 #include <plat/devs.h>
  63 #include <plat/cpu.h>
  64 #include <plat/pm.h>
  65
  66 static struct map_desc qt2410_iodesc[] __initdata = {
  67         { 0xe0000000, __phys_to_pfn(S3C2410_CS3+0x01000000), SZ_1M, MT_DEVICE }
  68 };
  69
  70 #define UCON S3C2410_UCON_DEFAULT
  71 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
  72 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
  73
  74 static struct s3c2410_uartcfg smdk2410_uartcfgs[] = {
  75         [0] = {
  76                 .hwport      = 0,
  77                 .flags       = 0,
  78                 .ucon        = UCON,
  79                 .ulcon       = ULCON,
  80                 .ufcon       = UFCON,
  81         },
  82         [1] = {
  83                 .hwport      = 1,
  84                 .flags       = 0,
  85                 .ucon        = UCON,
  86                 .ulcon       = ULCON,
  87                 .ufcon       = UFCON,
  88         },
  89         [2] = {
  90                 .hwport      = 2,
  91                 .flags       = 0,
  92                 .ucon        = UCON,
  93                 .ulcon       = ULCON,
  94                 .ufcon       = UFCON,
  95         }
  96 };
  97
  98 /* LCD driver info */
  99
 100 static struct s3c2410fb_display qt2410_lcd_cfg[] __initdata = {
 101         {
 102                 /* Configuration for 640x480 SHARP LQ080V3DG01 */
 103                 .lcdcon5 = S3C2410_LCDCON5_FRM565 |
 104                            S3C2410_LCDCON5_INVVLINE |
 105                            S3C2410_LCDCON5_INVVFRAME |
 106                            S3C2410_LCDCON5_PWREN |
 107                            S3C2410_LCDCON5_HWSWP,
 108
 109                 .type           = S3C2410_LCDCON1_TFT,
 110                 .width          = 640,
 111                 .height         = 480,
 112
 113                 .pixclock       = 40000, /* HCLK/4 */
 114                 .xres           = 640,
 115                 .yres           = 480,
 116                 .bpp            = 16,
 117                 .left_margin    = 44,
 118                 .right_margin   = 116,
 119                 .hsync_len      = 96,
 120                 .upper_margin   = 19,
 121                 .lower_margin   = 11,
 122                 .vsync_len      = 15,
 123         },
 124         {
 125                 /* Configuration for 480x640 toppoly TD028TTEC1 */
 126                 .lcdcon5 = S3C2410_LCDCON5_FRM565 |
 127                            S3C2410_LCDCON5_INVVLINE |
 128                            S3C2410_LCDCON5_INVVFRAME |
 129                            S3C2410_LCDCON5_PWREN |
 130                            S3C2410_LCDCON5_HWSWP,
 131
 132                 .type           = S3C2410_LCDCON1_TFT,
 133                 .width          = 480,
 134                 .height         = 640,
 135                 .pixclock       = 40000, /* HCLK/4 */
 136                 .xres           = 480,
 137                 .yres           = 640,
 138                 .bpp            = 16,
 139                 .left_margin    = 8,
 140                 .right_margin   = 24,
 141                 .hsync_len      = 8,
 142                 .upper_margin   = 2,
 143                 .lower_margin   = 4,
 144                 .vsync_len      = 2,
 145         },
 146         {
 147                 /* Config for 240x320 LCD */
 148                 .lcdcon5 = S3C2410_LCDCON5_FRM565 |
 149                            S3C2410_LCDCON5_INVVLINE |
 150                            S3C2410_LCDCON5_INVVFRAME |
 151                            S3C2410_LCDCON5_PWREN |
 152                            S3C2410_LCDCON5_HWSWP,
 153
 154                 .type           = S3C2410_LCDCON1_TFT,
 155                 .width          = 240,
 156                 .height         = 320,
 157                 .pixclock       = 100000, /* HCLK/10 */
 158                 .xres           = 240,
 159                 .yres           = 320,
 160                 .bpp            = 16,
 161                 .left_margin    = 13,
 162                 .right_margin   = 8,
 163                 .hsync_len      = 4,
 164                 .upper_margin   = 2,
 165                 .lower_margin   = 7,
 166                 .vsync_len      = 4,
 167         },
 168 };
 169
 170
 171 static struct s3c2410fb_mach_info qt2410_fb_info __initdata = {
 172         .displays       = qt2410_lcd_cfg,
 173         .num_displays   = ARRAY_SIZE(qt2410_lcd_cfg),
 174         .default_display = 0,
 175
 176         .lpcsel         = ((0xCE6) & ~7) | 1<<4,
 177 };
 178
 179 /* CS8900 */
 180
 181 static struct resource qt2410_cs89x0_resources[] = {
 182         [0] = {
 183                 .start  = 0x19000000,
 184                 .end    = 0x19000000 + 16,
 185                 .flags  = IORESOURCE_MEM,
 186         },
 187         [1] = {
 188                 .start  = IRQ_EINT9,
 189                 .end    = IRQ_EINT9,
 190                 .flags  = IORESOURCE_IRQ,
 191         },
 192 };
 193
 194 static struct platform_device qt2410_cs89x0 = {
 195         .name           = "cirrus-cs89x0",
 196         .num_resources  = ARRAY_SIZE(qt2410_cs89x0_resources),
 197         .resource       = qt2410_cs89x0_resources,
 198 };
 199
 200 /* LED */
 201
 202 static struct s3c24xx_led_platdata qt2410_pdata_led = {
 203         .gpio           = S3C2410_GPB(0),
 204         .flags          = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
 205         .name           = "led",
 206         .def_trigger    = "timer",
 207 };
 208
 209 static struct platform_device qt2410_led = {
 210         .name           = "s3c24xx_led",
 211         .id             = 0,
 212         .dev            = {
 213                 .platform_data = &qt2410_pdata_led,
 214         },
 215 };
 216
 217 /* SPI */
 218
 219 static void spi_gpio_cs(struct s3c2410_spigpio_info *spi, int cs)
 220 {
 221         switch (cs) {
 222         case BITBANG_CS_ACTIVE:
 223                 gpio_set_value(S3C2410_GPB(5), 0);
 224                 break;
 225         case BITBANG_CS_INACTIVE:
 226                 gpio_set_value(S3C2410_GPB(5), 1);
 227                 break;
 228         }
 229 }
 230
 231 static struct s3c2410_spigpio_info spi_gpio_cfg = {
 232         .pin_clk        = S3C2410_GPG(7),
 233         .pin_mosi       = S3C2410_GPG(6),
 234         .pin_miso       = S3C2410_GPG(5),
 235         .chip_select    = &spi_gpio_cs,
 236 };
 237
 238
 239 static struct platform_device qt2410_spi = {
 240         .name             = "s3c24xx-spi-gpio",
 241         .id               = 1,
 242         .dev = {
 243                 .platform_data = &spi_gpio_cfg,
 244         },
 245 };
 246
 247 /* Board devices */
 248
 249 static struct platform_device *qt2410_devices[] __initdata = {
 250         &s3c_device_ohci,
 251         &s3c_device_lcd,
 252         &s3c_device_wdt,
 253         &s3c_device_i2c0,
 254         &s3c_device_iis,
 255         &s3c_device_sdi,
 256         &s3c_device_usbgadget,
 257         &qt2410_spi,
 258         &qt2410_cs89x0,
 259         &qt2410_led,
 260 };
 261
 262 static struct mtd_partition __initdata qt2410_nand_part[] = {
 263         [0] = {
 264                 .name   = "U-Boot",
 265                 .size   = 0x30000,
 266                 .offset = 0,
 267         },
 268         [1] = {
 269                 .name   = "U-Boot environment",
 270                 .offset = 0x30000,
 271                 .size   = 0x4000,
 272         },
 273         [2] = {
 274                 .name   = "kernel",
 275                 .offset = 0x34000,
 276                 .size   = SZ_2M,
 277         },
 278         [3] = {
 279                 .name   = "initrd",
 280                 .offset = 0x234000,
 281                 .size   = SZ_4M,
 282         },
 283         [4] = {
 284                 .name   = "jffs2",
 285                 .offset = 0x634000,
 286                 .size   = 0x39cc000,
 287         },
 288 };
 289
 290 static struct s3c2410_nand_set __initdata qt2410_nand_sets[] = {
 291         [0] = {
 292                 .name           = "NAND",
 293                 .nr_chips       = 1,
 294                 .nr_partitions  = ARRAY_SIZE(qt2410_nand_part),
 295                 .partitions     = qt2410_nand_part,
 296         },
 297 };
 298
 299 /* choose a set of timings which should suit most 512Mbit
 300  * chips and beyond.
 301  */
 302
 303 static struct s3c2410_platform_nand __initdata qt2410_nand_info = {
 304         .tacls          = 20,
 305         .twrph0         = 60,
 306         .twrph1         = 20,
 307         .nr_sets        = ARRAY_SIZE(qt2410_nand_sets),
 308         .sets           = qt2410_nand_sets,
 309 };
 310
 311 /* UDC */
 312
 313 static struct s3c2410_udc_mach_info qt2410_udc_cfg = {
 314 };
 315
 316 static char tft_type = 's';
 317
 318 static int __init qt2410_tft_setup(char *str)
 319 {
 320         tft_type = str[0];
 321         return 1;
 322 }
 323
 324 __setup("tft=", qt2410_tft_setup);
 325
 326 static void __init qt2410_map_io(void)
 327 {
 328         s3c24xx_init_io(qt2410_iodesc, ARRAY_SIZE(qt2410_iodesc));
 329         s3c24xx_init_clocks(12*1000*1000);
 330         s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs));
 331 }
 332
 333 static void __init qt2410_machine_init(void)
 334 {
 335         s3c_nand_set_platdata(&qt2410_nand_info);
 336
 337         switch (tft_type) {
 338         case 'p': /* production */
 339                 qt2410_fb_info.default_display = 1;
 340                 break;
 341         case 'b': /* big */
 342                 qt2410_fb_info.default_display = 0;
 343                 break;
 344         case 's': /* small */
 345         default:
 346                 qt2410_fb_info.default_display = 2;
 347                 break;
 348         }
 349         s3c24xx_fb_set_platdata(&qt2410_fb_info);
 350
 351         s3c_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPIO_OUTPUT);
 352         s3c2410_gpio_setpin(S3C2410_GPB(0), 1);
 353
 354         s3c24xx_udc_set_platdata(&qt2410_udc_cfg);
 355         s3c_i2c0_set_platdata(NULL);
 356
 357         WARN_ON(gpio_request(S3C2410_GPB(5), "spi cs"));
 358         gpio_direction_output(S3C2410_GPB(5), 1);
 359
 360         platform_add_devices(qt2410_devices, ARRAY_SIZE(qt2410_devices));
 361         s3c_pm_init();
 362 }
 363
 364 MACHINE_START(QT2410, "QT2410")
 365         .phys_io        = S3C2410_PA_UART,
 366         .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
 367         .boot_params    = S3C2410_SDRAM_PA + 0x100,
 368         .map_io         = qt2410_map_io,
 369         .init_irq       = s3c24xx_init_irq,
 370         .init_machine   = qt2410_machine_init,
 371         .timer          = &s3c24xx_timer,
 372 MACHINE_END
 373
 374