arch/arm/mach-s3c2410/mach-osiris.c

   1 /* linux/arch/arm/mach-s3c2410/mach-osiris.c
   2  *
   3  * Copyright (c) 2005 Simtec Electronics
   4  *      http://armlinux.simtec.co.uk/
   5  *      Ben Dooks <ben@simtec.co.uk>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/types.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/list.h>
  16 #include <linux/timer.h>
  17 #include <linux/init.h>
  18 #include <linux/device.h>
  19
  20 #include <asm/mach/arch.h>
  21 #include <asm/mach/map.h>
  22 #include <asm/mach/irq.h>
  23
  24 #include <asm/arch/osiris-map.h>
  25 #include <asm/arch/osiris-cpld.h>
  26
  27 #include <asm/hardware.h>
  28 #include <asm/io.h>
  29 #include <asm/irq.h>
  30 #include <asm/mach-types.h>
  31
  32 #include <asm/arch/regs-serial.h>
  33 #include <asm/arch/regs-gpio.h>
  34 #include <asm/arch/regs-mem.h>
  35 #include <asm/arch/regs-lcd.h>
  36 #include <asm/arch/nand.h>
  37
  38 #include <linux/mtd/mtd.h>
  39 #include <linux/mtd/nand.h>
  40 #include <linux/mtd/nand_ecc.h>
  41 #include <linux/mtd/partitions.h>
  42
  43 #include "clock.h"
  44 #include "devs.h"
  45 #include "cpu.h"
  46
  47 /* onboard perihpheral map */
  48
  49 static struct map_desc osiris_iodesc[] __initdata = {
  50   /* ISA IO areas (may be over-written later) */
  51
  52   {
  53           .virtual      = (u32)S3C24XX_VA_ISA_BYTE,
  54           .pfn          = __phys_to_pfn(S3C2410_CS5),
  55           .length       = SZ_16M,
  56           .type         = MT_DEVICE,
  57   }, {
  58           .virtual      = (u32)S3C24XX_VA_ISA_WORD,
  59           .pfn          = __phys_to_pfn(S3C2410_CS5),
  60           .length       = SZ_16M,
  61           .type         = MT_DEVICE,
  62   },
  63
  64   /* CPLD control registers */
  65
  66   {
  67           .virtual      = (u32)OSIRIS_VA_CTRL1,
  68           .pfn          = __phys_to_pfn(OSIRIS_PA_CTRL1),
  69           .length       = SZ_16K,
  70           .type         = MT_DEVICE,
  71   }, {
  72           .virtual      = (u32)OSIRIS_VA_CTRL2,
  73           .pfn          = __phys_to_pfn(OSIRIS_PA_CTRL2),
  74           .length       = SZ_16K,
  75           .type         = MT_DEVICE,
  76   },
  77 };
  78
  79 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
  80 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
  81 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
  82
  83 static struct s3c24xx_uart_clksrc osiris_serial_clocks[] = {
  84         [0] = {
  85                 .name           = "uclk",
  86                 .divisor        = 1,
  87                 .min_baud       = 0,
  88                 .max_baud       = 0,
  89         },
  90         [1] = {
  91                 .name           = "pclk",
  92                 .divisor        = 1,
  93                 .min_baud       = 0,
  94                 .max_baud       = 0,
  95         }
  96 };
  97
  98 static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
  99         [0] = {
 100                 .hwport      = 0,
 101                 .flags       = 0,
 102                 .ucon        = UCON,
 103                 .ulcon       = ULCON,
 104                 .ufcon       = UFCON,
 105                 .clocks      = osiris_serial_clocks,
 106                 .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
 107         },
 108         [1] = {
 109                 .hwport      = 1,
 110                 .flags       = 0,
 111                 .ucon        = UCON,
 112                 .ulcon       = ULCON,
 113                 .ufcon       = UFCON,
 114                 .clocks      = osiris_serial_clocks,
 115                 .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
 116         },
 117         [2] = {
 118                 .hwport      = 2,
 119                 .flags       = 0,
 120                 .ucon        = UCON,
 121                 .ulcon       = ULCON,
 122                 .ufcon       = UFCON,
 123                 .clocks      = osiris_serial_clocks,
 124                 .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
 125         }
 126 };
 127
 128 /* NAND Flash on Osiris board */
 129
 130 static int external_map[]   = { 2 };
 131 static int chip0_map[]      = { 0 };
 132 static int chip1_map[]      = { 1 };
 133
 134 static struct mtd_partition osiris_default_nand_part[] = {
 135         [0] = {
 136                 .name   = "Boot Agent",
 137                 .size   = SZ_16K,
 138                 .offset = 0,
 139         },
 140         [1] = {
 141                 .name   = "/boot",
 142                 .size   = SZ_4M - SZ_16K,
 143                 .offset = SZ_16K,
 144         },
 145         [2] = {
 146                 .name   = "user1",
 147                 .offset = SZ_4M,
 148                 .size   = SZ_32M - SZ_4M,
 149         },
 150         [3] = {
 151                 .name   = "user2",
 152                 .offset = SZ_32M,
 153                 .size   = MTDPART_SIZ_FULL,
 154         }
 155 };
 156
 157 /* the Osiris has 3 selectable slots for nand-flash, the two
 158  * on-board chip areas, as well as the external slot.
 159  *
 160  * Note, there is no current hot-plug support for the External
 161  * socket.
 162 */
 163
 164 static struct s3c2410_nand_set osiris_nand_sets[] = {
 165         [1] = {
 166                 .name           = "External",
 167                 .nr_chips       = 1,
 168                 .nr_map         = external_map,
 169                 .nr_partitions  = ARRAY_SIZE(osiris_default_nand_part),
 170                 .partitions     = osiris_default_nand_part,
 171         },
 172         [0] = {
 173                 .name           = "chip0",
 174                 .nr_chips       = 1,
 175                 .nr_map         = chip0_map,
 176                 .nr_partitions  = ARRAY_SIZE(osiris_default_nand_part),
 177                 .partitions     = osiris_default_nand_part,
 178         },
 179         [2] = {
 180                 .name           = "chip1",
 181                 .nr_chips       = 1,
 182                 .nr_map         = chip1_map,
 183                 .nr_partitions  = ARRAY_SIZE(osiris_default_nand_part),
 184                 .partitions     = osiris_default_nand_part,
 185         },
 186 };
 187
 188 static void osiris_nand_select(struct s3c2410_nand_set *set, int slot)
 189 {
 190         unsigned int tmp;
 191
 192         slot = set->nr_map[slot] & 3;
 193
 194         pr_debug("osiris_nand: selecting slot %d (set %p,%p)\n",
 195                  slot, set, set->nr_map);
 196
 197         tmp = __raw_readb(OSIRIS_VA_CTRL1);
 198         tmp &= ~OSIRIS_CTRL1_NANDSEL;
 199         tmp |= slot;
 200
 201         pr_debug("osiris_nand: ctrl1 now %02x\n", tmp);
 202
 203         __raw_writeb(tmp, OSIRIS_VA_CTRL1);
 204 }
 205
 206 static struct s3c2410_platform_nand osiris_nand_info = {
 207         .tacls          = 25,
 208         .twrph0         = 60,
 209         .twrph1         = 60,
 210         .nr_sets        = ARRAY_SIZE(osiris_nand_sets),
 211         .sets           = osiris_nand_sets,
 212         .select_chip    = osiris_nand_select,
 213 };
 214
 215 /* PCMCIA control and configuration */
 216
 217 static struct resource osiris_pcmcia_resource[] = {
 218         [0] = {
 219                 .start  = 0x0f000000,
 220                 .end    = 0x0f100000,
 221                 .flags  = IORESOURCE_MEM,
 222         },
 223         [1] = {
 224                 .start  = 0x0c000000,
 225                 .end    = 0x0c100000,
 226                 .flags  = IORESOURCE_MEM,
 227         }
 228 };
 229
 230 static struct platform_device osiris_pcmcia = {
 231         .name           = "osiris-pcmcia",
 232         .id             = -1,
 233         .num_resources  = ARRAY_SIZE(osiris_pcmcia_resource),
 234         .resource       = osiris_pcmcia_resource,
 235 };
 236
 237 /* Standard Osiris devices */
 238
 239 static struct platform_device *osiris_devices[] __initdata = {
 240         &s3c_device_i2c,
 241         &s3c_device_nand,
 242         &osiris_pcmcia,
 243 };
 244
 245 static struct clk *osiris_clocks[] = {
 246         &s3c24xx_dclk0,
 247         &s3c24xx_dclk1,
 248         &s3c24xx_clkout0,
 249         &s3c24xx_clkout1,
 250         &s3c24xx_uclk,
 251 };
 252
 253 static struct s3c24xx_board osiris_board __initdata = {
 254         .devices       = osiris_devices,
 255         .devices_count = ARRAY_SIZE(osiris_devices),
 256         .clocks        = osiris_clocks,
 257         .clocks_count  = ARRAY_SIZE(osiris_clocks),
 258 };
 259
 260 static void __init osiris_map_io(void)
 261 {
 262         unsigned long flags;
 263
 264         /* initialise the clocks */
 265
 266         s3c24xx_dclk0.parent = NULL;
 267         s3c24xx_dclk0.rate   = 12*1000*1000;
 268
 269         s3c24xx_dclk1.parent = NULL;
 270         s3c24xx_dclk1.rate   = 24*1000*1000;
 271
 272         s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
 273         s3c24xx_clkout1.parent  = &s3c24xx_dclk1;
 274
 275         s3c24xx_uclk.parent  = &s3c24xx_clkout1;
 276
 277         s3c_device_nand.dev.platform_data = &osiris_nand_info;
 278
 279         s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc));
 280         s3c24xx_init_clocks(0);
 281         s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs));
 282         s3c24xx_set_board(&osiris_board);
 283
 284         /* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */
 285
 286         local_irq_save(flags);
 287         __raw_writel(__raw_readl(S3C2410_BWSCON) | S3C2410_BWSCON_ST1 | S3C2410_BWSCON_ST2 | S3C2410_BWSCON_ST3 | S3C2410_BWSCON_ST4 | S3C2410_BWSCON_ST5, S3C2410_BWSCON);
 288         local_irq_restore(flags);
 289
 290         /* write-protect line to the NAND */
 291         s3c2410_gpio_setpin(S3C2410_GPA0, 1);
 292 }
 293
 294 MACHINE_START(OSIRIS, "Simtec-OSIRIS")
 295         /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
 296         .phys_io        = S3C2410_PA_UART,
 297         .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
 298         .boot_params    = S3C2410_SDRAM_PA + 0x100,
 299         .map_io         = osiris_map_io,
 300         .init_irq       = s3c24xx_init_irq,
 301         .timer          = &s3c24xx_timer,
 302 MACHINE_END