arch/arm/mach-realview/core.c

   1 /*
   2  *  linux/arch/arm/mach-realview/core.c
   3  *
   4  *  Copyright (C) 1999 - 2003 ARM Limited
   5  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21 #include <linux/init.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/sysdev.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/amba/bus.h>
  27 #include <linux/amba/clcd.h>
  28 #include <linux/clocksource.h>
  29 #include <linux/clockchips.h>
  30 #include <linux/io.h>
  31 #include <linux/smsc911x.h>
  32 #include <linux/ata_platform.h>
  33
  34 #include <asm/clkdev.h>
  35 #include <asm/system.h>
  36 #include <mach/hardware.h>
  37 #include <asm/irq.h>
  38 #include <asm/leds.h>
  39 #include <asm/mach-types.h>
  40 #include <asm/hardware/arm_timer.h>
  41 #include <asm/hardware/icst307.h>
  42
  43 #include <asm/mach/arch.h>
  44 #include <asm/mach/flash.h>
  45 #include <asm/mach/irq.h>
  46 #include <asm/mach/map.h>
  47 #include <asm/mach/mmc.h>
  48
  49 #include <asm/hardware/gic.h>
  50
  51 #include <mach/platform.h>
  52 #include <mach/irqs.h>
  53
  54 #include "core.h"
  55 #include "clock.h"
  56
  57 #define REALVIEW_REFCOUNTER     (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_24MHz_OFFSET)
  58
  59 /* used by entry-macro.S and platsmp.c */
  60 void __iomem *gic_cpu_base_addr;
  61
  62 /*
  63  * This is the RealView sched_clock implementation.  This has
  64  * a resolution of 41.7ns, and a maximum value of about 179s.
  65  */
  66 unsigned long long sched_clock(void)
  67 {
  68         unsigned long long v;
  69
  70         v = (unsigned long long)readl(REALVIEW_REFCOUNTER) * 125;
  71         do_div(v, 3);
  72
  73         return v;
  74 }
  75
  76
  77 #define REALVIEW_FLASHCTRL    (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)
  78
  79 static int realview_flash_init(void)
  80 {
  81         u32 val;
  82
  83         val = __raw_readl(REALVIEW_FLASHCTRL);
  84         val &= ~REALVIEW_FLASHPROG_FLVPPEN;
  85         __raw_writel(val, REALVIEW_FLASHCTRL);
  86
  87         return 0;
  88 }
  89
  90 static void realview_flash_exit(void)
  91 {
  92         u32 val;
  93
  94         val = __raw_readl(REALVIEW_FLASHCTRL);
  95         val &= ~REALVIEW_FLASHPROG_FLVPPEN;
  96         __raw_writel(val, REALVIEW_FLASHCTRL);
  97 }
  98
  99 static void realview_flash_set_vpp(int on)
 100 {
 101         u32 val;
 102
 103         val = __raw_readl(REALVIEW_FLASHCTRL);
 104         if (on)
 105                 val |= REALVIEW_FLASHPROG_FLVPPEN;
 106         else
 107                 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
 108         __raw_writel(val, REALVIEW_FLASHCTRL);
 109 }
 110
 111 static struct flash_platform_data realview_flash_data = {
 112         .map_name               = "cfi_probe",
 113         .width                  = 4,
 114         .init                   = realview_flash_init,
 115         .exit                   = realview_flash_exit,
 116         .set_vpp                = realview_flash_set_vpp,
 117 };
 118
 119 struct platform_device realview_flash_device = {
 120         .name                   = "armflash",
 121         .id                     = 0,
 122         .dev                    = {
 123                 .platform_data  = &realview_flash_data,
 124         },
 125 };
 126
 127 int realview_flash_register(struct resource *res, u32 num)
 128 {
 129         realview_flash_device.resource = res;
 130         realview_flash_device.num_resources = num;
 131         return platform_device_register(&realview_flash_device);
 132 }
 133
 134 static struct smsc911x_platform_config smsc911x_config = {
 135         .flags          = SMSC911X_USE_32BIT,
 136         .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
 137         .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
 138         .phy_interface  = PHY_INTERFACE_MODE_MII,
 139 };
 140
 141 static struct platform_device realview_eth_device = {
 142         .name           = "smsc911x",
 143         .id             = 0,
 144         .num_resources  = 2,
 145 };
 146
 147 int realview_eth_register(const char *name, struct resource *res)
 148 {
 149         if (name)
 150                 realview_eth_device.name = name;
 151         realview_eth_device.resource = res;
 152         if (strcmp(realview_eth_device.name, "smsc911x") == 0)
 153                 realview_eth_device.dev.platform_data = &smsc911x_config;
 154
 155         return platform_device_register(&realview_eth_device);
 156 }
 157
 158 struct platform_device realview_usb_device = {
 159         .name                   = "isp1760",
 160         .num_resources          = 2,
 161 };
 162
 163 int realview_usb_register(struct resource *res)
 164 {
 165         realview_usb_device.resource = res;
 166         return platform_device_register(&realview_usb_device);
 167 }
 168
 169 static struct pata_platform_info pata_platform_data = {
 170         .ioport_shift           = 1,
 171 };
 172
 173 static struct resource pata_resources[] = {
 174         [0] = {
 175                 .start          = REALVIEW_CF_BASE,
 176                 .end            = REALVIEW_CF_BASE + 0xff,
 177                 .flags          = IORESOURCE_MEM,
 178         },
 179         [1] = {
 180                 .start          = REALVIEW_CF_BASE + 0x100,
 181                 .end            = REALVIEW_CF_BASE + SZ_4K - 1,
 182                 .flags          = IORESOURCE_MEM,
 183         },
 184 };
 185
 186 struct platform_device realview_cf_device = {
 187         .name                   = "pata_platform",
 188         .id                     = -1,
 189         .num_resources          = ARRAY_SIZE(pata_resources),
 190         .resource               = pata_resources,
 191         .dev                    = {
 192                 .platform_data  = &pata_platform_data,
 193         },
 194 };
 195
 196 static struct resource realview_i2c_resource = {
 197         .start          = REALVIEW_I2C_BASE,
 198         .end            = REALVIEW_I2C_BASE + SZ_4K - 1,
 199         .flags          = IORESOURCE_MEM,
 200 };
 201
 202 struct platform_device realview_i2c_device = {
 203         .name           = "versatile-i2c",
 204         .id             = 0,
 205         .num_resources  = 1,
 206         .resource       = &realview_i2c_resource,
 207 };
 208
 209 static struct i2c_board_info realview_i2c_board_info[] = {
 210         {
 211                 I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
 212         },
 213 };
 214
 215 static int __init realview_i2c_init(void)
 216 {
 217         return i2c_register_board_info(0, realview_i2c_board_info,
 218                                        ARRAY_SIZE(realview_i2c_board_info));
 219 }
 220 arch_initcall(realview_i2c_init);
 221
 222 #define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)
 223
 224 static unsigned int realview_mmc_status(struct device *dev)
 225 {
 226         struct amba_device *adev = container_of(dev, struct amba_device, dev);
 227         u32 mask;
 228
 229         if (adev->res.start == REALVIEW_MMCI0_BASE)
 230                 mask = 1;
 231         else
 232                 mask = 2;
 233
 234         return readl(REALVIEW_SYSMCI) & mask;
 235 }
 236
 237 struct mmc_platform_data realview_mmc0_plat_data = {
 238         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 239         .status         = realview_mmc_status,
 240 };
 241
 242 struct mmc_platform_data realview_mmc1_plat_data = {
 243         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 244         .status         = realview_mmc_status,
 245 };
 246
 247 /*
 248  * Clock handling
 249  */
 250 static const struct icst307_params realview_oscvco_params = {
 251         .ref            = 24000,
 252         .vco_max        = 200000,
 253         .vd_min         = 4 + 8,
 254         .vd_max         = 511 + 8,
 255         .rd_min         = 1 + 2,
 256         .rd_max         = 127 + 2,
 257 };
 258
 259 static void realview_oscvco_set(struct clk *clk, struct icst307_vco vco)
 260 {
 261         void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET;
 262         void __iomem *sys_osc;
 263         u32 val;
 264
 265         if (machine_is_realview_pb1176())
 266                 sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC0_OFFSET;
 267         else
 268                 sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC4_OFFSET;
 269
 270         val = readl(sys_osc) & ~0x7ffff;
 271         val |= vco.v | (vco.r << 9) | (vco.s << 16);
 272
 273         writel(0xa05f, sys_lock);
 274         writel(val, sys_osc);
 275         writel(0, sys_lock);
 276 }
 277
 278 static struct clk oscvco_clk = {
 279         .params = &realview_oscvco_params,
 280         .setvco = realview_oscvco_set,
 281 };
 282
 283 /*
 284  * These are fixed clocks.
 285  */
 286 static struct clk ref24_clk = {
 287         .rate   = 24000000,
 288 };
 289
 290 static struct clk_lookup lookups[] = {
 291         {       /* UART0 */
 292                 .dev_id         = "dev:f1",
 293                 .clk            = &ref24_clk,
 294         }, {    /* UART1 */
 295                 .dev_id         = "dev:f2",
 296                 .clk            = &ref24_clk,
 297         }, {    /* UART2 */
 298                 .dev_id         = "dev:f3",
 299                 .clk            = &ref24_clk,
 300         }, {    /* UART3 */
 301                 .dev_id         = "fpga:09",
 302                 .clk            = &ref24_clk,
 303         }, {    /* KMI0 */
 304                 .dev_id         = "fpga:06",
 305                 .clk            = &ref24_clk,
 306         }, {    /* KMI1 */
 307                 .dev_id         = "fpga:07",
 308                 .clk            = &ref24_clk,
 309         }, {    /* MMC0 */
 310                 .dev_id         = "fpga:05",
 311                 .clk            = &ref24_clk,
 312         }, {    /* EB:CLCD */
 313                 .dev_id         = "dev:20",
 314                 .clk            = &oscvco_clk,
 315         }, {    /* PB:CLCD */
 316                 .dev_id         = "issp:20",
 317                 .clk            = &oscvco_clk,
 318         }
 319 };
 320
 321 static int __init clk_init(void)
 322 {
 323         int i;
 324
 325         for (i = 0; i < ARRAY_SIZE(lookups); i++)
 326                 clkdev_add(&lookups[i]);
 327         return 0;
 328 }
 329 arch_initcall(clk_init);
 330
 331 /*
 332  * CLCD support.
 333  */
 334 #define SYS_CLCD_NLCDIOON       (1 << 2)
 335 #define SYS_CLCD_VDDPOSSWITCH   (1 << 3)
 336 #define SYS_CLCD_PWR3V5SWITCH   (1 << 4)
 337 #define SYS_CLCD_ID_MASK        (0x1f << 8)
 338 #define SYS_CLCD_ID_SANYO_3_8   (0x00 << 8)
 339 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
 340 #define SYS_CLCD_ID_EPSON_2_2   (0x02 << 8)
 341 #define SYS_CLCD_ID_SANYO_2_5   (0x07 << 8)
 342 #define SYS_CLCD_ID_VGA         (0x1f << 8)
 343
 344 static struct clcd_panel vga = {
 345         .mode           = {
 346                 .name           = "VGA",
 347                 .refresh        = 60,
 348                 .xres           = 640,
 349                 .yres           = 480,
 350                 .pixclock       = 39721,
 351                 .left_margin    = 40,
 352                 .right_margin   = 24,
 353                 .upper_margin   = 32,
 354                 .lower_margin   = 11,
 355                 .hsync_len      = 96,
 356                 .vsync_len      = 2,
 357                 .sync           = 0,
 358                 .vmode          = FB_VMODE_NONINTERLACED,
 359         },
 360         .width          = -1,
 361         .height         = -1,
 362         .tim2           = TIM2_BCD | TIM2_IPC,
 363         .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
 364         .bpp            = 16,
 365 };
 366
 367 static struct clcd_panel xvga = {
 368         .mode           = {
 369                 .name           = "XVGA",
 370                 .refresh        = 60,
 371                 .xres           = 1024,
 372                 .yres           = 768,
 373                 .pixclock       = 15748,
 374                 .left_margin    = 152,
 375                 .right_margin   = 48,
 376                 .upper_margin   = 23,
 377                 .lower_margin   = 3,
 378                 .hsync_len      = 104,
 379                 .vsync_len      = 4,
 380                 .sync           = 0,
 381                 .vmode          = FB_VMODE_NONINTERLACED,
 382         },
 383         .width          = -1,
 384         .height         = -1,
 385         .tim2           = TIM2_BCD | TIM2_IPC,
 386         .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
 387         .bpp            = 16,
 388 };
 389
 390 static struct clcd_panel sanyo_3_8_in = {
 391         .mode           = {
 392                 .name           = "Sanyo QVGA",
 393                 .refresh        = 116,
 394                 .xres           = 320,
 395                 .yres           = 240,
 396                 .pixclock       = 100000,
 397                 .left_margin    = 6,
 398                 .right_margin   = 6,
 399                 .upper_margin   = 5,
 400                 .lower_margin   = 5,
 401                 .hsync_len      = 6,
 402                 .vsync_len      = 6,
 403                 .sync           = 0,
 404                 .vmode          = FB_VMODE_NONINTERLACED,
 405         },
 406         .width          = -1,
 407         .height         = -1,
 408         .tim2           = TIM2_BCD,
 409         .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
 410         .bpp            = 16,
 411 };
 412
 413 static struct clcd_panel sanyo_2_5_in = {
 414         .mode           = {
 415                 .name           = "Sanyo QVGA Portrait",
 416                 .refresh        = 116,
 417                 .xres           = 240,
 418                 .yres           = 320,
 419                 .pixclock       = 100000,
 420                 .left_margin    = 20,
 421                 .right_margin   = 10,
 422                 .upper_margin   = 2,
 423                 .lower_margin   = 2,
 424                 .hsync_len      = 10,
 425                 .vsync_len      = 2,
 426                 .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
 427                 .vmode          = FB_VMODE_NONINTERLACED,
 428         },
 429         .width          = -1,
 430         .height         = -1,
 431         .tim2           = TIM2_IVS | TIM2_IHS | TIM2_IPC,
 432         .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
 433         .bpp            = 16,
 434 };
 435
 436 static struct clcd_panel epson_2_2_in = {
 437         .mode           = {
 438                 .name           = "Epson QCIF",
 439                 .refresh        = 390,
 440                 .xres           = 176,
 441                 .yres           = 220,
 442                 .pixclock       = 62500,
 443                 .left_margin    = 3,
 444                 .right_margin   = 2,
 445                 .upper_margin   = 1,
 446                 .lower_margin   = 0,
 447                 .hsync_len      = 3,
 448                 .vsync_len      = 2,
 449                 .sync           = 0,
 450                 .vmode          = FB_VMODE_NONINTERLACED,
 451         },
 452         .width          = -1,
 453         .height         = -1,
 454         .tim2           = TIM2_BCD | TIM2_IPC,
 455         .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
 456         .bpp            = 16,
 457 };
 458
 459 /*
 460  * Detect which LCD panel is connected, and return the appropriate
 461  * clcd_panel structure.  Note: we do not have any information on
 462  * the required timings for the 8.4in panel, so we presently assume
 463  * VGA timings.
 464  */
 465 static struct clcd_panel *realview_clcd_panel(void)
 466 {
 467         void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
 468         struct clcd_panel *vga_panel;
 469         struct clcd_panel *panel;
 470         u32 val;
 471
 472         if (machine_is_realview_eb())
 473                 vga_panel = &vga;
 474         else
 475                 vga_panel = &xvga;
 476
 477         val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
 478         if (val == SYS_CLCD_ID_SANYO_3_8)
 479                 panel = &sanyo_3_8_in;
 480         else if (val == SYS_CLCD_ID_SANYO_2_5)
 481                 panel = &sanyo_2_5_in;
 482         else if (val == SYS_CLCD_ID_EPSON_2_2)
 483                 panel = &epson_2_2_in;
 484         else if (val == SYS_CLCD_ID_VGA)
 485                 panel = vga_panel;
 486         else {
 487                 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
 488                         val);
 489                 panel = vga_panel;
 490         }
 491
 492         return panel;
 493 }
 494
 495 /*
 496  * Disable all display connectors on the interface module.
 497  */
 498 static void realview_clcd_disable(struct clcd_fb *fb)
 499 {
 500         void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
 501         u32 val;
 502
 503         val = readl(sys_clcd);
 504         val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 505         writel(val, sys_clcd);
 506 }
 507
 508 /*
 509  * Enable the relevant connector on the interface module.
 510  */
 511 static void realview_clcd_enable(struct clcd_fb *fb)
 512 {
 513         void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
 514         u32 val;
 515
 516         /*
 517          * Enable the PSUs
 518          */
 519         val = readl(sys_clcd);
 520         val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 521         writel(val, sys_clcd);
 522 }
 523
 524 static int realview_clcd_setup(struct clcd_fb *fb)
 525 {
 526         unsigned long framesize;
 527         dma_addr_t dma;
 528
 529         if (machine_is_realview_eb())
 530                 /* VGA, 16bpp */
 531                 framesize = 640 * 480 * 2;
 532         else
 533                 /* XVGA, 16bpp */
 534                 framesize = 1024 * 768 * 2;
 535
 536         fb->panel               = realview_clcd_panel();
 537
 538         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
 539                                                     &dma, GFP_KERNEL);
 540         if (!fb->fb.screen_base) {
 541                 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
 542                 return -ENOMEM;
 543         }
 544
 545         fb->fb.fix.smem_start   = dma;
 546         fb->fb.fix.smem_len     = framesize;
 547
 548         return 0;
 549 }
 550
 551 static int realview_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
 552 {
 553         return dma_mmap_writecombine(&fb->dev->dev, vma,
 554                                      fb->fb.screen_base,
 555                                      fb->fb.fix.smem_start,
 556                                      fb->fb.fix.smem_len);
 557 }
 558
 559 static void realview_clcd_remove(struct clcd_fb *fb)
 560 {
 561         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
 562                               fb->fb.screen_base, fb->fb.fix.smem_start);
 563 }
 564
 565 struct clcd_board clcd_plat_data = {
 566         .name           = "RealView",
 567         .check          = clcdfb_check,
 568         .decode         = clcdfb_decode,
 569         .disable        = realview_clcd_disable,
 570         .enable         = realview_clcd_enable,
 571         .setup          = realview_clcd_setup,
 572         .mmap           = realview_clcd_mmap,
 573         .remove         = realview_clcd_remove,
 574 };
 575
 576 #ifdef CONFIG_LEDS
 577 #define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
 578
 579 void realview_leds_event(led_event_t ledevt)
 580 {
 581         unsigned long flags;
 582         u32 val;
 583         u32 led = 1 << smp_processor_id();
 584
 585         local_irq_save(flags);
 586         val = readl(VA_LEDS_BASE);
 587
 588         switch (ledevt) {
 589         case led_idle_start:
 590                 val = val & ~led;
 591                 break;
 592
 593         case led_idle_end:
 594                 val = val | led;
 595                 break;
 596
 597         case led_timer:
 598                 val = val ^ REALVIEW_SYS_LED7;
 599                 break;
 600
 601         case led_halted:
 602                 val = 0;
 603                 break;
 604
 605         default:
 606                 break;
 607         }
 608
 609         writel(val, VA_LEDS_BASE);
 610         local_irq_restore(flags);
 611 }
 612 #endif  /* CONFIG_LEDS */
 613
 614 /*
 615  * Where is the timer (VA)?
 616  */
 617 void __iomem *timer0_va_base;
 618 void __iomem *timer1_va_base;
 619 void __iomem *timer2_va_base;
 620 void __iomem *timer3_va_base;
 621
 622 /*
 623  * How long is the timer interval?
 624  */
 625 #define TIMER_INTERVAL  (TICKS_PER_uSEC * mSEC_10)
 626 #if TIMER_INTERVAL >= 0x100000
 627 #define TIMER_RELOAD    (TIMER_INTERVAL >> 8)
 628 #define TIMER_DIVISOR   (TIMER_CTRL_DIV256)
 629 #define TICKS2USECS(x)  (256 * (x) / TICKS_PER_uSEC)
 630 #elif TIMER_INTERVAL >= 0x10000
 631 #define TIMER_RELOAD    (TIMER_INTERVAL >> 4)           /* Divide by 16 */
 632 #define TIMER_DIVISOR   (TIMER_CTRL_DIV16)
 633 #define TICKS2USECS(x)  (16 * (x) / TICKS_PER_uSEC)
 634 #else
 635 #define TIMER_RELOAD    (TIMER_INTERVAL)
 636 #define TIMER_DIVISOR   (TIMER_CTRL_DIV1)
 637 #define TICKS2USECS(x)  ((x) / TICKS_PER_uSEC)
 638 #endif
 639
 640 static void timer_set_mode(enum clock_event_mode mode,
 641                            struct clock_event_device *clk)
 642 {
 643         unsigned long ctrl;
 644
 645         switch(mode) {
 646         case CLOCK_EVT_MODE_PERIODIC:
 647                 writel(TIMER_RELOAD, timer0_va_base + TIMER_LOAD);
 648
 649                 ctrl = TIMER_CTRL_PERIODIC;
 650                 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE | TIMER_CTRL_ENABLE;
 651                 break;
 652         case CLOCK_EVT_MODE_ONESHOT:
 653                 /* period set, and timer enabled in 'next_event' hook */
 654                 ctrl = TIMER_CTRL_ONESHOT;
 655                 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE;
 656                 break;
 657         case CLOCK_EVT_MODE_UNUSED:
 658         case CLOCK_EVT_MODE_SHUTDOWN:
 659         default:
 660                 ctrl = 0;
 661         }
 662
 663         writel(ctrl, timer0_va_base + TIMER_CTRL);
 664 }
 665
 666 static int timer_set_next_event(unsigned long evt,
 667                                 struct clock_event_device *unused)
 668 {
 669         unsigned long ctrl = readl(timer0_va_base + TIMER_CTRL);
 670
 671         writel(evt, timer0_va_base + TIMER_LOAD);
 672         writel(ctrl | TIMER_CTRL_ENABLE, timer0_va_base + TIMER_CTRL);
 673
 674         return 0;
 675 }
 676
 677 static struct clock_event_device timer0_clockevent =     {
 678         .name           = "timer0",
 679         .shift          = 32,
 680         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 681         .set_mode       = timer_set_mode,
 682         .set_next_event = timer_set_next_event,
 683         .rating         = 300,
 684         .cpumask        = cpu_all_mask,
 685 };
 686
 687 static void __init realview_clockevents_init(unsigned int timer_irq)
 688 {
 689         timer0_clockevent.irq = timer_irq;
 690         timer0_clockevent.mult =
 691                 div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift);
 692         timer0_clockevent.max_delta_ns =
 693                 clockevent_delta2ns(0xffffffff, &timer0_clockevent);
 694         timer0_clockevent.min_delta_ns =
 695                 clockevent_delta2ns(0xf, &timer0_clockevent);
 696
 697         clockevents_register_device(&timer0_clockevent);
 698 }
 699
 700 /*
 701  * IRQ handler for the timer
 702  */
 703 static irqreturn_t realview_timer_interrupt(int irq, void *dev_id)
 704 {
 705         struct clock_event_device *evt = &timer0_clockevent;
 706
 707         /* clear the interrupt */
 708         writel(1, timer0_va_base + TIMER_INTCLR);
 709
 710         evt->event_handler(evt);
 711
 712         return IRQ_HANDLED;
 713 }
 714
 715 static struct irqaction realview_timer_irq = {
 716         .name           = "RealView Timer Tick",
 717         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 718         .handler        = realview_timer_interrupt,
 719 };
 720
 721 static cycle_t realview_get_cycles(struct clocksource *cs)
 722 {
 723         return ~readl(timer3_va_base + TIMER_VALUE);
 724 }
 725
 726 static struct clocksource clocksource_realview = {
 727         .name   = "timer3",
 728         .rating = 200,
 729         .read   = realview_get_cycles,
 730         .mask   = CLOCKSOURCE_MASK(32),
 731         .shift  = 20,
 732         .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
 733 };
 734
 735 static void __init realview_clocksource_init(void)
 736 {
 737         /* setup timer 0 as free-running clocksource */
 738         writel(0, timer3_va_base + TIMER_CTRL);
 739         writel(0xffffffff, timer3_va_base + TIMER_LOAD);
 740         writel(0xffffffff, timer3_va_base + TIMER_VALUE);
 741         writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
 742                 timer3_va_base + TIMER_CTRL);
 743
 744         clocksource_realview.mult =
 745                 clocksource_khz2mult(1000, clocksource_realview.shift);
 746         clocksource_register(&clocksource_realview);
 747 }
 748
 749 /*
 750  * Set up the clock source and clock events devices
 751  */
 752 void __init realview_timer_init(unsigned int timer_irq)
 753 {
 754         u32 val;
 755
 756         /*
 757          * set clock frequency:
 758          *      REALVIEW_REFCLK is 32KHz
 759          *      REALVIEW_TIMCLK is 1MHz
 760          */
 761         val = readl(__io_address(REALVIEW_SCTL_BASE));
 762         writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) |
 763                (REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) |
 764                (REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) |
 765                (REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) | val,
 766                __io_address(REALVIEW_SCTL_BASE));
 767
 768         /*
 769          * Initialise to a known state (all timers off)
 770          */
 771         writel(0, timer0_va_base + TIMER_CTRL);
 772         writel(0, timer1_va_base + TIMER_CTRL);
 773         writel(0, timer2_va_base + TIMER_CTRL);
 774         writel(0, timer3_va_base + TIMER_CTRL);
 775
 776         /*
 777          * Make irqs happen for the system timer
 778          */
 779         setup_irq(timer_irq, &realview_timer_irq);
 780
 781         realview_clocksource_init();
 782         realview_clockevents_init(timer_irq);
 783 }