arch/arm/mach-realview/core.c

   1 /*
   2  *  linux/arch/arm/mach-realview/core.c
   3  *
   4  *  Copyright (C) 1999 - 2003 ARM Limited
   5  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21 #include <linux/init.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/sysdev.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/amba/bus.h>
  27 #include <linux/amba/clcd.h>
  28
  29 #include <asm/system.h>
  30 #include <asm/hardware.h>
  31 #include <asm/io.h>
  32 #include <asm/irq.h>
  33 #include <asm/leds.h>
  34 #include <asm/hardware/arm_timer.h>
  35 #include <asm/hardware/icst307.h>
  36
  37 #include <asm/mach/arch.h>
  38 #include <asm/mach/flash.h>
  39 #include <asm/mach/irq.h>
  40 #include <asm/mach/time.h>
  41 #include <asm/mach/map.h>
  42 #include <asm/mach/mmc.h>
  43
  44 #include <asm/hardware/gic.h>
  45
  46 #include "core.h"
  47 #include "clock.h"
  48
  49 #define REALVIEW_REFCOUNTER     (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_24MHz_OFFSET)
  50
  51 /*
  52  * This is the RealView sched_clock implementation.  This has
  53  * a resolution of 41.7ns, and a maximum value of about 179s.
  54  */
  55 unsigned long long sched_clock(void)
  56 {
  57         unsigned long long v;
  58
  59         v = (unsigned long long)readl(REALVIEW_REFCOUNTER) * 125;
  60         do_div(v, 3);
  61
  62         return v;
  63 }
  64
  65
  66 #define REALVIEW_FLASHCTRL    (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)
  67
  68 static int realview_flash_init(void)
  69 {
  70         u32 val;
  71
  72         val = __raw_readl(REALVIEW_FLASHCTRL);
  73         val &= ~REALVIEW_FLASHPROG_FLVPPEN;
  74         __raw_writel(val, REALVIEW_FLASHCTRL);
  75
  76         return 0;
  77 }
  78
  79 static void realview_flash_exit(void)
  80 {
  81         u32 val;
  82
  83         val = __raw_readl(REALVIEW_FLASHCTRL);
  84         val &= ~REALVIEW_FLASHPROG_FLVPPEN;
  85         __raw_writel(val, REALVIEW_FLASHCTRL);
  86 }
  87
  88 static void realview_flash_set_vpp(int on)
  89 {
  90         u32 val;
  91
  92         val = __raw_readl(REALVIEW_FLASHCTRL);
  93         if (on)
  94                 val |= REALVIEW_FLASHPROG_FLVPPEN;
  95         else
  96                 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
  97         __raw_writel(val, REALVIEW_FLASHCTRL);
  98 }
  99
 100 static struct flash_platform_data realview_flash_data = {
 101         .map_name               = "cfi_probe",
 102         .width                  = 4,
 103         .init                   = realview_flash_init,
 104         .exit                   = realview_flash_exit,
 105         .set_vpp                = realview_flash_set_vpp,
 106 };
 107
 108 static struct resource realview_flash_resource = {
 109         .start                  = REALVIEW_FLASH_BASE,
 110         .end                    = REALVIEW_FLASH_BASE + REALVIEW_FLASH_SIZE,
 111         .flags                  = IORESOURCE_MEM,
 112 };
 113
 114 struct platform_device realview_flash_device = {
 115         .name                   = "armflash",
 116         .id                     = 0,
 117         .dev                    = {
 118                 .platform_data  = &realview_flash_data,
 119         },
 120         .num_resources          = 1,
 121         .resource               = &realview_flash_resource,
 122 };
 123
 124 static struct resource realview_smc91x_resources[] = {
 125         [0] = {
 126                 .start          = REALVIEW_ETH_BASE,
 127                 .end            = REALVIEW_ETH_BASE + SZ_64K - 1,
 128                 .flags          = IORESOURCE_MEM,
 129         },
 130         [1] = {
 131                 .start          = IRQ_ETH,
 132                 .end            = IRQ_ETH,
 133                 .flags          = IORESOURCE_IRQ,
 134         },
 135 };
 136
 137 struct platform_device realview_smc91x_device = {
 138         .name           = "smc91x",
 139         .id             = 0,
 140         .num_resources  = ARRAY_SIZE(realview_smc91x_resources),
 141         .resource       = realview_smc91x_resources,
 142 };
 143
 144 #define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)
 145
 146 static unsigned int realview_mmc_status(struct device *dev)
 147 {
 148         struct amba_device *adev = container_of(dev, struct amba_device, dev);
 149         u32 mask;
 150
 151         if (adev->res.start == REALVIEW_MMCI0_BASE)
 152                 mask = 1;
 153         else
 154                 mask = 2;
 155
 156         return readl(REALVIEW_SYSMCI) & mask;
 157 }
 158
 159 struct mmc_platform_data realview_mmc0_plat_data = {
 160         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 161         .status         = realview_mmc_status,
 162 };
 163
 164 struct mmc_platform_data realview_mmc1_plat_data = {
 165         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 166         .status         = realview_mmc_status,
 167 };
 168
 169 /*
 170  * Clock handling
 171  */
 172 static const struct icst307_params realview_oscvco_params = {
 173         .ref            = 24000,
 174         .vco_max        = 200000,
 175         .vd_min         = 4 + 8,
 176         .vd_max         = 511 + 8,
 177         .rd_min         = 1 + 2,
 178         .rd_max         = 127 + 2,
 179 };
 180
 181 static void realview_oscvco_set(struct clk *clk, struct icst307_vco vco)
 182 {
 183         void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET;
 184         void __iomem *sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC4_OFFSET;
 185         u32 val;
 186
 187         val = readl(sys_osc) & ~0x7ffff;
 188         val |= vco.v | (vco.r << 9) | (vco.s << 16);
 189
 190         writel(0xa05f, sys_lock);
 191         writel(val, sys_osc);
 192         writel(0, sys_lock);
 193 }
 194
 195 struct clk realview_clcd_clk = {
 196         .name   = "CLCDCLK",
 197         .params = &realview_oscvco_params,
 198         .setvco = realview_oscvco_set,
 199 };
 200
 201 /*
 202  * CLCD support.
 203  */
 204 #define SYS_CLCD_NLCDIOON       (1 << 2)
 205 #define SYS_CLCD_VDDPOSSWITCH   (1 << 3)
 206 #define SYS_CLCD_PWR3V5SWITCH   (1 << 4)
 207 #define SYS_CLCD_ID_MASK        (0x1f << 8)
 208 #define SYS_CLCD_ID_SANYO_3_8   (0x00 << 8)
 209 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
 210 #define SYS_CLCD_ID_EPSON_2_2   (0x02 << 8)
 211 #define SYS_CLCD_ID_SANYO_2_5   (0x07 << 8)
 212 #define SYS_CLCD_ID_VGA         (0x1f << 8)
 213
 214 static struct clcd_panel vga = {
 215         .mode           = {
 216                 .name           = "VGA",
 217                 .refresh        = 60,
 218                 .xres           = 640,
 219                 .yres           = 480,
 220                 .pixclock       = 39721,
 221                 .left_margin    = 40,
 222                 .right_margin   = 24,
 223                 .upper_margin   = 32,
 224                 .lower_margin   = 11,
 225                 .hsync_len      = 96,
 226                 .vsync_len      = 2,
 227                 .sync           = 0,
 228                 .vmode          = FB_VMODE_NONINTERLACED,
 229         },
 230         .width          = -1,
 231         .height         = -1,
 232         .tim2           = TIM2_BCD | TIM2_IPC,
 233         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 234         .bpp            = 16,
 235 };
 236
 237 static struct clcd_panel sanyo_3_8_in = {
 238         .mode           = {
 239                 .name           = "Sanyo QVGA",
 240                 .refresh        = 116,
 241                 .xres           = 320,
 242                 .yres           = 240,
 243                 .pixclock       = 100000,
 244                 .left_margin    = 6,
 245                 .right_margin   = 6,
 246                 .upper_margin   = 5,
 247                 .lower_margin   = 5,
 248                 .hsync_len      = 6,
 249                 .vsync_len      = 6,
 250                 .sync           = 0,
 251                 .vmode          = FB_VMODE_NONINTERLACED,
 252         },
 253         .width          = -1,
 254         .height         = -1,
 255         .tim2           = TIM2_BCD,
 256         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 257         .bpp            = 16,
 258 };
 259
 260 static struct clcd_panel sanyo_2_5_in = {
 261         .mode           = {
 262                 .name           = "Sanyo QVGA Portrait",
 263                 .refresh        = 116,
 264                 .xres           = 240,
 265                 .yres           = 320,
 266                 .pixclock       = 100000,
 267                 .left_margin    = 20,
 268                 .right_margin   = 10,
 269                 .upper_margin   = 2,
 270                 .lower_margin   = 2,
 271                 .hsync_len      = 10,
 272                 .vsync_len      = 2,
 273                 .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
 274                 .vmode          = FB_VMODE_NONINTERLACED,
 275         },
 276         .width          = -1,
 277         .height         = -1,
 278         .tim2           = TIM2_IVS | TIM2_IHS | TIM2_IPC,
 279         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 280         .bpp            = 16,
 281 };
 282
 283 static struct clcd_panel epson_2_2_in = {
 284         .mode           = {
 285                 .name           = "Epson QCIF",
 286                 .refresh        = 390,
 287                 .xres           = 176,
 288                 .yres           = 220,
 289                 .pixclock       = 62500,
 290                 .left_margin    = 3,
 291                 .right_margin   = 2,
 292                 .upper_margin   = 1,
 293                 .lower_margin   = 0,
 294                 .hsync_len      = 3,
 295                 .vsync_len      = 2,
 296                 .sync           = 0,
 297                 .vmode          = FB_VMODE_NONINTERLACED,
 298         },
 299         .width          = -1,
 300         .height         = -1,
 301         .tim2           = TIM2_BCD | TIM2_IPC,
 302         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 303         .bpp            = 16,
 304 };
 305
 306 /*
 307  * Detect which LCD panel is connected, and return the appropriate
 308  * clcd_panel structure.  Note: we do not have any information on
 309  * the required timings for the 8.4in panel, so we presently assume
 310  * VGA timings.
 311  */
 312 static struct clcd_panel *realview_clcd_panel(void)
 313 {
 314         void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
 315         struct clcd_panel *panel = &vga;
 316         u32 val;
 317
 318         val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
 319         if (val == SYS_CLCD_ID_SANYO_3_8)
 320                 panel = &sanyo_3_8_in;
 321         else if (val == SYS_CLCD_ID_SANYO_2_5)
 322                 panel = &sanyo_2_5_in;
 323         else if (val == SYS_CLCD_ID_EPSON_2_2)
 324                 panel = &epson_2_2_in;
 325         else if (val == SYS_CLCD_ID_VGA)
 326                 panel = &vga;
 327         else {
 328                 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
 329                         val);
 330                 panel = &vga;
 331         }
 332
 333         return panel;
 334 }
 335
 336 /*
 337  * Disable all display connectors on the interface module.
 338  */
 339 static void realview_clcd_disable(struct clcd_fb *fb)
 340 {
 341         void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
 342         u32 val;
 343
 344         val = readl(sys_clcd);
 345         val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 346         writel(val, sys_clcd);
 347 }
 348
 349 /*
 350  * Enable the relevant connector on the interface module.
 351  */
 352 static void realview_clcd_enable(struct clcd_fb *fb)
 353 {
 354         void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
 355         u32 val;
 356
 357         /*
 358          * Enable the PSUs
 359          */
 360         val = readl(sys_clcd);
 361         val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 362         writel(val, sys_clcd);
 363 }
 364
 365 static unsigned long framesize = SZ_1M;
 366
 367 static int realview_clcd_setup(struct clcd_fb *fb)
 368 {
 369         dma_addr_t dma;
 370
 371         fb->panel               = realview_clcd_panel();
 372
 373         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
 374                                                     &dma, GFP_KERNEL);
 375         if (!fb->fb.screen_base) {
 376                 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
 377                 return -ENOMEM;
 378         }
 379
 380         fb->fb.fix.smem_start   = dma;
 381         fb->fb.fix.smem_len     = framesize;
 382
 383         return 0;
 384 }
 385
 386 static int realview_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
 387 {
 388         return dma_mmap_writecombine(&fb->dev->dev, vma,
 389                                      fb->fb.screen_base,
 390                                      fb->fb.fix.smem_start,
 391                                      fb->fb.fix.smem_len);
 392 }
 393
 394 static void realview_clcd_remove(struct clcd_fb *fb)
 395 {
 396         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
 397                               fb->fb.screen_base, fb->fb.fix.smem_start);
 398 }
 399
 400 struct clcd_board clcd_plat_data = {
 401         .name           = "RealView",
 402         .check          = clcdfb_check,
 403         .decode         = clcdfb_decode,
 404         .disable        = realview_clcd_disable,
 405         .enable         = realview_clcd_enable,
 406         .setup          = realview_clcd_setup,
 407         .mmap           = realview_clcd_mmap,
 408         .remove         = realview_clcd_remove,
 409 };
 410
 411 #ifdef CONFIG_LEDS
 412 #define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
 413
 414 void realview_leds_event(led_event_t ledevt)
 415 {
 416         unsigned long flags;
 417         u32 val;
 418
 419         local_irq_save(flags);
 420         val = readl(VA_LEDS_BASE);
 421
 422         switch (ledevt) {
 423         case led_idle_start:
 424                 val = val & ~REALVIEW_SYS_LED0;
 425                 break;
 426
 427         case led_idle_end:
 428                 val = val | REALVIEW_SYS_LED0;
 429                 break;
 430
 431         case led_timer:
 432                 val = val ^ REALVIEW_SYS_LED1;
 433                 break;
 434
 435         case led_halted:
 436                 val = 0;
 437                 break;
 438
 439         default:
 440                 break;
 441         }
 442
 443         writel(val, VA_LEDS_BASE);
 444         local_irq_restore(flags);
 445 }
 446 #endif  /* CONFIG_LEDS */
 447
 448 /*
 449  * Where is the timer (VA)?
 450  */
 451 #define TIMER0_VA_BASE           __io_address(REALVIEW_TIMER0_1_BASE)
 452 #define TIMER1_VA_BASE          (__io_address(REALVIEW_TIMER0_1_BASE) + 0x20)
 453 #define TIMER2_VA_BASE           __io_address(REALVIEW_TIMER2_3_BASE)
 454 #define TIMER3_VA_BASE          (__io_address(REALVIEW_TIMER2_3_BASE) + 0x20)
 455
 456 /*
 457  * How long is the timer interval?
 458  */
 459 #define TIMER_INTERVAL  (TICKS_PER_uSEC * mSEC_10)
 460 #if TIMER_INTERVAL >= 0x100000
 461 #define TIMER_RELOAD    (TIMER_INTERVAL >> 8)
 462 #define TIMER_DIVISOR   (TIMER_CTRL_DIV256)
 463 #define TICKS2USECS(x)  (256 * (x) / TICKS_PER_uSEC)
 464 #elif TIMER_INTERVAL >= 0x10000
 465 #define TIMER_RELOAD    (TIMER_INTERVAL >> 4)           /* Divide by 16 */
 466 #define TIMER_DIVISOR   (TIMER_CTRL_DIV16)
 467 #define TICKS2USECS(x)  (16 * (x) / TICKS_PER_uSEC)
 468 #else
 469 #define TIMER_RELOAD    (TIMER_INTERVAL)
 470 #define TIMER_DIVISOR   (TIMER_CTRL_DIV1)
 471 #define TICKS2USECS(x)  ((x) / TICKS_PER_uSEC)
 472 #endif
 473
 474 /*
 475  * Returns number of ms since last clock interrupt.  Note that interrupts
 476  * will have been disabled by do_gettimeoffset()
 477  */
 478 static unsigned long realview_gettimeoffset(void)
 479 {
 480         unsigned long ticks1, ticks2, status;
 481
 482         /*
 483          * Get the current number of ticks.  Note that there is a race
 484          * condition between us reading the timer and checking for
 485          * an interrupt.  We get around this by ensuring that the
 486          * counter has not reloaded between our two reads.
 487          */
 488         ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff;
 489         do {
 490                 ticks1 = ticks2;
 491                 status = __raw_readl(__io_address(REALVIEW_GIC_DIST_BASE + GIC_DIST_PENDING_SET)
 492                                      + ((IRQ_TIMERINT0_1 >> 5) << 2));
 493                 ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff;
 494         } while (ticks2 > ticks1);
 495
 496         /*
 497          * Number of ticks since last interrupt.
 498          */
 499         ticks1 = TIMER_RELOAD - ticks2;
 500
 501         /*
 502          * Interrupt pending?  If so, we've reloaded once already.
 503          *
 504          * FIXME: Need to check this is effectively timer 0 that expires
 505          */
 506         if (status & IRQMASK_TIMERINT0_1)
 507                 ticks1 += TIMER_RELOAD;
 508
 509         /*
 510          * Convert the ticks to usecs
 511          */
 512         return TICKS2USECS(ticks1);
 513 }
 514
 515 /*
 516  * IRQ handler for the timer
 517  */
 518 static irqreturn_t realview_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 519 {
 520         write_seqlock(&xtime_lock);
 521
 522         // ...clear the interrupt
 523         writel(1, TIMER0_VA_BASE + TIMER_INTCLR);
 524
 525         timer_tick(regs);
 526
 527 #if defined(CONFIG_SMP) && !defined(CONFIG_LOCAL_TIMERS)
 528         smp_send_timer();
 529         update_process_times(user_mode(regs));
 530 #endif
 531
 532         write_sequnlock(&xtime_lock);
 533
 534         return IRQ_HANDLED;
 535 }
 536
 537 static struct irqaction realview_timer_irq = {
 538         .name           = "RealView Timer Tick",
 539         .flags          = IRQF_DISABLED | IRQF_TIMER,
 540         .handler        = realview_timer_interrupt,
 541 };
 542
 543 /*
 544  * Set up timer interrupt, and return the current time in seconds.
 545  */
 546 static void __init realview_timer_init(void)
 547 {
 548         u32 val;
 549
 550         /*
 551          * set clock frequency:
 552          *      REALVIEW_REFCLK is 32KHz
 553          *      REALVIEW_TIMCLK is 1MHz
 554          */
 555         val = readl(__io_address(REALVIEW_SCTL_BASE));
 556         writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) |
 557                (REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) |
 558                (REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) |
 559                (REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) | val,
 560                __io_address(REALVIEW_SCTL_BASE));
 561
 562         /*
 563          * Initialise to a known state (all timers off)
 564          */
 565         writel(0, TIMER0_VA_BASE + TIMER_CTRL);
 566         writel(0, TIMER1_VA_BASE + TIMER_CTRL);
 567         writel(0, TIMER2_VA_BASE + TIMER_CTRL);
 568         writel(0, TIMER3_VA_BASE + TIMER_CTRL);
 569
 570         writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);
 571         writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_VALUE);
 572         writel(TIMER_DIVISOR | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC |
 573                TIMER_CTRL_IE, TIMER0_VA_BASE + TIMER_CTRL);
 574
 575         /*
 576          * Make irqs happen for the system timer
 577          */
 578         setup_irq(IRQ_TIMERINT0_1, &realview_timer_irq);
 579 }
 580
 581 struct sys_timer realview_timer = {
 582         .init           = realview_timer_init,
 583         .offset         = realview_gettimeoffset,
 584 };